A Review of Silicon-Based Wafer Bonding Processes, An Approach To Realize The Monolithic Integration of Si-CMOS and III-V-on-Si Wafers

Journal of Semiconductors
(2021) 42, 023106

REVIEWS doi: 10.1088/1674-4926/42/2/023106
A review of silicon-based wafer bonding processes, an approach

to realize the monolithic integration of Si-CMOS and III–V-on-Si
wafers
Shuyu Bao1, ‡, †, Yue Wang1, ‡, Khaw Lina1, Li Zhang1, Bing Wang1, 2, †, Wardhana Aji Sasangka1,
Kenneth Eng Kian Lee1, Soo Jin Chua1, 3, Jurgen Michel1, 4, Eugene Fitzgerald1, 5,
Chuan Seng Tan1, 6, and Kwang Hong Lee1, †
1Low Energy Electronic Systems (LEES), Singapore-MIT Alliance for Research and Technology (SMART), Singapore 138602, Singapore
2School of Electronics and Information Technology, Sun Yat-Sen University, Guangzhou 510006, China
3Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576, Singapore
4Materials Research Laboratories, Massachusetts Institute of Technology, Cambridge, MA, 02139, USA
5Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA
6School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore
Abstract: The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in
the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control cir-
cuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mis-
match issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at
wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this
paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-,
double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Mean-
while, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.
Key words: material; thin film; integrated circuit
Citation: S Y Bao, Y Wang, K Lina, L Zhang, B Wang, W A Sasangka, K E K Lee, S J Chua, J Michel, E Fitzgerald, C S Tan, and K H Lee,
A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si
wafers[J]. J. Semicond., 2021, 42(2), 023106. http://doi.org/10.1088/1674-4926/42/2/023106
1. Introduction for their unique electrical properties and superior high mobil-
ity transistors[4, 5]. In addition, most of the III–V materials have
The silicon (Si) complementary metal–oxide–semiconduct- direct bandgaps and are commonly used as lighting materi-
or (CMOS) is the most dominant component in the semicon-
als for LEDs and lasers. Compared to III–V materials, Si is an in-
ductor industry and the miniaturization of Si-CMOS is the
direct bandgap material and it is difficult to fabricate an effi-
main trend to further improve its speed, power consumption
cient lighting device using Si. Therefore, III–V materials-based
and production cost[1]. However, as the Si-CMOS is scaled to
light sources are used as a hybrid solution in a silicon photon-
smaller devices, the issues of device reliability, such as short
ics platform for data transmission[6–10]. Meanwhile, this hy-
channel effects and random fluctuations, become more
brid technology opens up numerous possibilities to develop
severe, and the lithography and etching processes are more
new integrated circuit designs and applications in the fields
complex and costly[2, 3]. As the benefits of scaling subside, the
of high-speed computation and sensing.
device's performance will be more and more materials-driv-
Epitaxial integration of growing III–V materials directly on
en. Thus, the development of new materials systems, which
are compatible with the Si-CMOS platform, can be the next Si substrates is the most desirable approach to integrate the
generation of semiconductor technologies to break the bottle- III–V transistor with the Si platform. However, this method ex-
neck of Si-CMOS scaling. periences many issues due to the large lattice mismatch and
The performance improvement of a transistor is driven the difference in coefficient of thermal expansion (CTE)
by the carrier mobility enhancement in the channel. The between the III–V compound semiconductor and Si. Thus, it re-
Group IV materials, such as SiGe and Ge, and the Group III–V mains a challenge to form thin III–V layers on Si while retain-
compound materials, such as GaAs and InP, are well-known ing excellent crystal quality. In addition, the growth of III–V ma-
terials requires a high temperature condition (650–1350 °C, de-
Shuyu Bao and Yue Wang contributed equally to this work.
pending on the materials systems).
Correspondence to: S Y Bao, shuyu@smart.mit.edu; B Wang, Compared to the epitaxial integration method, direct
wangb266@mail.sysu.edu.cn; K H Lee, leek0046@e.ntu.edu.sg wafer bonding (DWB) is a more straightforward and practical
Received 18 MAY 2020; Revised 18 JUNE 2020. approach to achieve the heterogeneous integration between
©2021 Chinese Institute of Electronics III–V and the Si substrate without the exposure of Si-CMOS to
2 Journal of Semiconductors doi: 10.1088/1674-4926/42/2/023106
high temperature[11–13]. One of the most prominent applica- and compound semiconductors. Fortunately, the anneal tem-
tions of DWB is to make silicon-on-insulator (SOI) substrates, perature can be significantly reduced with plasma-activated
of which the technique can be extended to X-on-insulator sub- or other special wafer surface treatments. Meanwhile, the
strates, such as Ge-OI, GeSn-OI, SiC-OI or other III–V-OI[14–18]. thermal stress is significantly reduced when lowering the an-
In addition, the wafer bonding technique enables separate nealing temperature, and the low temperature process also
wafer processing of III–V materials and CMOS in their respect- makes it compatible with back-end CMOS processing.
ive foundries and then to be integrated at final stages. This Besides annealing and plasma treatment, there are some
separate processing method can avoid the cross-contamina- stringent requirements in the process flow to ensure a success-
tion between III–V materials and Si-CMOS in wafer pro- ful wafer bonding, such as bonding energy, surface cleanli-
cessing tools in the Si foundries. ness, roughness and flatness. Firstly, the bonding is initiated
In Section 2 of this paper, several mainstream bonding by applying a physical force at one point on the wafer, allow-
techniques, including their applications and challenges, will ing the bond front to propagate. The propagation of the
be reviewed. In Section 3, our recent progress of single-, bond front to a sealed interface is dependent on the balance
double- and multi-DWB bonding techniques will be dis- between the surface energy dissipation to form the bond and
cussed in detail. After that, various applications enabled by the strain energy to deform the wafers[23]. Secondly, a clean
these techniques, such as CMOS-driven HEMT, LED, and oth- surface is essential in wafer bonding processes[20]. The pres-
er novel applications will be shown at the end of this paper. ence of organic and metallic contaminations and particles
can affect the structural and electrical properties of the bond-
2. Wafer bonding techniques
ing interface. Therefore, the pre-steps of proper surface clean-
In this section, various mainstream approaches in wafer- ing must be applied. Additionally, it is essential to ensure
scale bonding will be reviewed, including DWB, surface-activ- that the cleaning method will not cause severe surface rough-
ated bonding, thermocompression bonding, eutectic bond- ening. The bonding surface cleaning method, named Radio
ing, glass frit bonding, adhesive bonding and anodic bond- Corporation of America (RCA) cleaning, is commonly used in
ing. Among these bonding techniques, the DWB is the most the semiconductor industry. There are two hydrogen perox-
promising approach for wafer-scale III–V on Si integration ide based steps: RCA1 or SC1 (NH4OH : H2O2 : H2O = 1 : 1 : 5)
and Si-CMOS integrated devices due to its strong bonding and RCA2 or SC2 (HCl : H2O2 : H2O = 1 : 1 : 6). RCA1 is de-
strength, reliable bonding interface and low temperature pro- signed to remove the organic contaminants, especially hydro-
cessing conditions. This section will present these bonding carbon, by oxidizing action from H2O2 and solvating action of
techniques in more details. NH4OH. Apart from RCA1, strong oxidizer periodic acid
2.1. Direct wafer bonding (H5IO6) can also be used to remove hydrocarbon residual at
Heterogeneous integration technologies show great po- the wafer surface. RCA2 is aimed at removing metallic (ionic)
tential in the applications of novel materials, MEMS devices contaminants. It is suggested to have a low ratio of NH4OH
and 3D packaging. In the past, wire bonding, flip-chip and epi- for surface cleaning to avoid the surface roughening caused
taxial integration were commonly used for heterogeneous in- by the ammonia from RCA1. Due to this concern, UV/ozone
tegrations. However, due to the concerns of process complex- cleaning and plasma treatments are also employed to treat
ity, scalability and materials quality, these integration applica- the surface before bonding without degrading the surface[22].
tions were ruled out by the traditional materials science and Besides organic and metallic contaminations, particles can
semiconductor processing technology[19]. DWB has shown act as spacers, preventing intimate wafer contact and creat-
great potential for heterogeneous integration by directly bonding intrinsic voids. Since the presence of a small particle can
ing two similar or dissimilar materials and devices at the result in a large void, ultraclean environment is preferred dur-
wafer-level. As a result, DWB has enabled numerous new ap- ing wafer bonding. Thirdly, wafer surface roughness is anoth-
plications, such as SOI, silicon-based sensors and actuators, er crucial parameter for DWB. It is suggested that if the root
and III–V optical and electrical devices[20]. Direct wafer bond- mean square (RMS) roughness is less than 1 nm, it poses no
ing is also known as “wafer bonding” or “direct bonding”, obstacles in DWB at room temperature via hydrogen
which was first proposed in 1985 by Lasky et al.[21]. It is bonds[20]. Fortunately, the current semiconductor techno-
known that when two materials with clean and flat surfaces logy is able to produce prime Si wafers with roughness less
are brought into intimate contact, the two materials will ad- than 0.1 nm. The post-process surface roughening can also
here and form bonds across the interface without the need be reduced by a technique, named chemical-mechanical pol-
of an intermediate layer[22]. The adhesion between two mat- ishing (CMP). CMP polishes the surface at wafer-level to
ing surfaces is through van der Waals interactions or hydro- achieve the bonding required roughness level. Lastly, surface
gen bridge bonds[19]. A similar phenomenon was also ob- flatness is another important factor in DWB. By assuming the
served when two mirror-polished wafers were brought into back surface is flat, the flatness is the deviation of the front sur-
close proximity, so that the wafers are directly bonded. As face to a reference plane, which can be quantified by the
the strength of such adhesion is much weaker than covalent total thickness variation (TTV)[20]. TTV is defined as the height
bond, annealing at high temperature is commonly applied difference between the highest and lowest sites on the top
after the room temperature pre-bond step to strengthen the wafer surface. If two wafers with different TTVs need to be bon-
wafer bonding. In the silicon-to-silicon direct hydrophilic bond- ded, they will be deformed into a common shape during the
ing, good bond strength is only obtained with a high temperat- bonding processes[23]. If the TTV is small, the bonding can be
ure anneal at above 800 °C. Such high temperatures are un- successful by simply bringing two polished wafers into intim-
desirable for many applications, especially for metallization ate contact at room temperature. When TTV is large, the gap
S Y Bao et al.: A review of silicon-based wafer bonding processes, an approach to realize the monolithic ......
Journal of Semiconductors doi: 10.1088/1674-4926/42/2/023106 3
prevents the wafers from bonding, resulting in large unboun- smooth surface with high surface flatness is desirable as it pro-
ded areas. Though the deposition of nitride or metal layers motes the interatomic attractions. Metals with a high diffu-
on the wafer backside can introduce external stress to re- sion rate are used in this bonding technique. The most com-
duce the TTV, there is no established method to fully resolve monly used metals are Au, Al and Cu[32–36]. They can be depos-
this issue as it changes significantly with wafer materials, di- ited through evaporation, sputtering or electroplating. A thin
mensions, layer structures and fabrication conditions. adhesion layer is deposited first, not only improving the adhe-
When the wafers are bonded, bonding defects may exist, sion strength, but also reducing the bonding temperature
causing the failures of device fabrication in the later pro- and pressure. Three mains steps in thermocompression bond-
cessing steps. Therefore, it is important to detect these bonding are metal film deposition, surface pre-treatment for organ-
ing defects at early stages. One of the most commonly used ic and oxide removal, and bonding under heat and pressure.
methods is the IR imaging. As silicon is transparent at IR In Au–Au thermocompression bonding, a thin oxide diffu-
wavelength range (> 1.1 μm), the bonding defects, such as sion barrier layer and Ti adhesion layer are deposited prior to
dark spots, interferential lines and voids, are visible under IR Au layer deposition, in which the oxide layer is to block Si
imaging. IR imaging is a fast and cheap method to detect from diffusion into the Au surface. A successful wafer-level
bonding defects, but its resolution is limited. For small bond- Au–Au bonding has been obtained at the bonding temperat-
ing defects, c-mode scanning acoustic microscopy (C-SAM) is ure of 300 °C and the compressive pressure of 7 MPa[33]. In
a more efficient method compared to IR imaging. Acoustic Al–Al and Cu–Cu bondings, a slightly higher bonding temperat-
wave propagates across the bonding structure and is reflec- ure is required. The bonding temperature is in the range of
ted when meeting voids and bubbles. The reflections ampli- 400–500 °C for Al–Al thermocompression bonding[32] and
fy the beam energy locally, and an acoustic image of the bond- 250–400 °C for Cu–Cu bonding[35]. An increase in bonding pres-
ing defect is formed. In addition, the acoustic spectroscopy sure is necessary when reducing the bonding temperature is
can also be used for bonding quality detection in metallic needed. Thermocompression bonding is a well-established
bonding, while metals are opaque to infrared radiation. Apart wafer-level hermetical sealing method of MEMS devices with
from these two non-destructive defect detection methods, small form factor. It is also very attractive in 3D integrations
wafer thinning is another approach to detect the defects. The as it can provide electrical contacts. However, the main disad-
bonded wafers are thinned down by etching until the bond- vantages are the relatively high bonding temperature and
ing defects can be observed. This method provides an extra di- bonding pressure. A large bonding force is required when in-
mension in depth to visualize the bonding defects, com- creasing the wafer size, which can cause wafer fracture dur-
pared to IR imaging and C-SAM. ing bonding.
2.2. Surface activated bonding (SAB) 2.4. Eutectic bonding
In SAB, the bonding reaction is driven by the cohesive Eutectic wafer bonding is a widespread method in MEMS
and adhesive energy of solids. Wafer surfaces are sputter- systems for hermetically sealed packaging and 3D integra-
cleaned and activated with argon fast atom beam (FAB) be- tions. Compared to thermocompression bonding between
fore being brought into close contact in an ultrahigh vacu- two metals, eutectic bonding is based on a eutectic system of
um (~10−5–10−6 Pa) chamber. Then, large bonding pressure alloys used as the intermediate bonding layer to bond two
of a few tens of mega-pascal is applied to the close-contac- wafers together via diffusion mechanism. In the eutectic sys-
ted wafer pair. The bonding strength achievable at room tem- tem, their mixture can melt or solidify at a lower temperat-
perature is close to the bulk fracture energy of the ure than the melting point of the individual component materi-
materials[24]. Hence, further heat treatment is not necessary in als. There is a wide range of material combinations for eutect-
the surface activated bonding. Wafer-level room temperat- ic wafer bonding, such as Au–In, Au–Ge, Au–Sn, Au–Si, Al–Ge
ure bonding is applicable to dissimilar semiconductors, and Cu–Sn[37–40]. Among these combinations, Au–Si system is
metals and insulators[24–28], and III–V optical and electronic the most commonly used one. Before the Au–Si eutectic bond-
device bonding have also been demonstrated without using ing process begins, a surface pre-treatment process is re-
the high temperature annealing process[27, 29]. Therefore, the quired. It is an essential step as the native oxides of metals
potential damages by the annealing process, such as doping
can prevent the bonding. After the pre-treatment, a silicon-
profile change, thermal stress induction, and new defect gener-
cap wafer and a wafer deposited with Au layer are placed
ation, can be eliminated. Additionally, experimental results
face-to-face and loaded into the bonding chamber. The bond-
from TEM and electrical conductivity measurements show
ing starts to occur at the temperatures higher than their eu-
that SAB enables oxide-free semiconductors and metal bond-
tectic temperature of 363 °C. The typical bonding condition is
ing interfaces[26, 29, 30]. This is very beneficial for stacked solar-
to use 410–450 °C chamber temperature and 0.2–0.5 MPa
cell and 3D integrations. However, some ionic materials, like
bonding pressure[41]. Bonding uniformity continues to in-
glass to SiO2 and SiO2–SiO2 show a polarized surface after
crease with the increasing chamber pressure. However, the
FAB bombardment, which inhibits the bonding[31]. Another
bonding strength and bonding yield can decrease when the
disadvantage of SAB is its restricted requirement of surface
contact pressure is too high. This is caused by the metal
conditions, in terms of smoothness and flatness, which
squeezing-out at the bonding interface[42]. Benefiting from
strongly affect the bonding results.
the lithography process to define the bonding sites, small
2.3. Thermocompression bonding device packaging with a relatively small seal ring pattern is
Thermocompression bonding, also known as diffusion possible. Eutectic bonding, similar to thermocompression
bonding, is a metal-based bonding technique that brings two bonding, has electrically conductive bonds, compatible with
surfaces into atomic contact under heat and pressure. A electronic components integration. However, it also has disad-
(a) (b) Cathode

Cathode
Borosilicate glass Si substrate
Borosilicate glass
Si substrate
Bonding Si substrate
Bonding Anode interface
interface Anode
Temperature: 200−400 °C Temperature: 200−400 °C
Fig. 1. Schematic views of (a) silicon–glass anodic bonding and (b) silicon–silicon anodic bonding mediated with a borosilicate glass layer.
vantages, such as non-uniform bonding, complicated bond- lowed by the steps of polymer heat or ultraviolet light pre-cur-
ing process, and high bonding temperature. In addition, as eu- ing, room temperature pre-bonding and low temperature an-
tectic bonding occurs at elevated temperatures, the large nealing. The polymer adhesives are normally in a liquid, semi-
thermal budget is detrimental to the electronic and MEMS liquid or viscoelastic phase during the bonding, then trans-
devices. Localized heating with focused laser beam heating formed into a low viscous phase, and finally into the solid
at the contact sites is a viable approach[43]. The exposed area phase to achieve strong and stable bonds[50]. In order to im-
to high temperature is significantly reduced. prove the bonding strength and quality, the bonding pro-
cesses, such as film deposition methods, pre-curing condi-
2.5. Glass frit bonding
tions, bonding and chamber pressures, need to be carefully
Glass frit bonding is a wafer-level encapsulation and pack- chosen. One of the advantages using the adhesive bonding
aging technology. It allows strong hermetic wafer bonds with technique is its low temperature conditions (typically not ex-
a high process yield, especially designed for MEMS resonat- ceeding 250 °C), making it suitable for 3D MEMS, nano-elec-
ors and micosensors[44, 45]. Recent research shows laser-as- tromechanical systems (NEMS), photonic circuits integration
sisted glass frit bonding is a suitable encapsulation techno- and CMOS integrated devices. Another major advantage is
logy for inorganic quantum dot light-emitting devices the soft and deformable features of poly adhesives. On one
(QLED)[46]. In glass frit bonding, there are three major steps: i) hand, the intermediate adhesive layer can flow easily to
the deposition of glass paste on the wafer surface by spay- avoid the microvoids formation by compensating the extrins-
ing, screen-printing, or spin coating, ii) the conditioning or ic interface particles (particles with the diameter smaller than
pre-sintering of the paste to remove the organic binders, and the layer thickness) and the CMP caused imperfections. On
iii) the bonding step allowing hermetic bonds to form the other hand, the intermediate layer thickness can also be
between the wafers. Low melting glass (lead or lead silicate) varied in a wide range from nm to μm. A sufficiently thick inter-
as an intermediate material in the bonding is milled into fine mediate layer can be used to planarize the surface and even
powder. Then the powder is mixed with an organic binder, encapsulate the high topography structures. Thus, adhesive
which promotes the deposition of the glass on wafer surface. bonding applications are also applied in wafer-to-wafer align-
The thermal expansion coefficient can be modified by adding ment. However, the wafer alignment accuracy is significantly
inorganic fillers into the glass paste, making it compatible reduced due to the unavoidable sheer force during the bond-
with silicon-based MEMS devices. During the bonding steps, ing process. When two mating wafers are brought into close
heat is applied to enable glass paste reflowing and wetting contact and stacked, the deforming intermediate layer is not
over the bonding frames. A strong and stable bond is formed strong enough to counteract the sheer force at the bonding in-
after cooling down. The main advantage of the glass frit bond- terface and the bonding process causes alignment shifts. To re-
ing is its applicability to nearly all surfaces regardless of the sur- duce the shift, surface structures are introduced at the wafer
face materials and roughness. No wafer surface activation or edge to increase the friction[51]. The use of partially cross-
special preparation process is necessary. Other advantages in- linked polymer adhesives can also help to improve the align-
clude high bond strength, good process stability, particle com- ment accuracy as they do not reflow during the bonding pro-
pensation, selective area bonding and hermetical sealing. cess. It has been demonstrated that the shift can be attained
However, the large sealing ring and relatively low sealing as low as 1 μm by using the partially cured BCB[52].
frame precision make glass frit bonding less superior than eu-
2.7. Anodic bonding
tectic bonding. Additionally, uncontrolled flowing of glass
paste into the undesired region is a main problem using Anodic bonding, also referred to as field assisted bond-
glass frit bonding. A special design to block reflowing and op- ing or electrostatic bonding, joins ion conductive materials
timization in glass paste deposition can help to solve this prob- to metal or silicon through a sufficiently strong electrical
lem in the future. field[53, 54]. It is a well-established technology used in the semi-
conductor industry for microsensors fabrication and MEMS
2.6. Adhesive bonding packaging. Alkali ion containing borosilicate glass (traded as
Adhesive bonding utilizes polymer adhesives such as ben- Pyrex® 7740) is often used in metal-glass and silicon-glass
zocyclobutene (BCB), spin-on glass (SOG), resists and polyim- bonding. Silicon–silicon bonding is also possible with anodic
ides as the intermediate layer for bonding[47–50]. Wafer-scale bonding when mediated with a thin layer of the sputter-depos-
bonding with the substrate diameter up to 200 mm has been ited borosilicate glass[55]. The schematic process of silicon–silic-
successfully demonstrated using BCB as the adhesive materi- on anodic bonding is shown in Fig. 1(b). The bonding temper-
al[48]. In adhesive bonding process, a thin layer of the poly- ature used ranges from 200 to 400 °C[56], which needs to be
mer adhesive is applied on one of the two mating wafers fol- sufficiently high to render the non-conductive material electric-
ally conducting. The electrostatic voltage in the range of (a) (b)

200–1000 V is applied[57]. In silicon–glass anodic bonding Si
pair, the silicon side and the glass side are biased as the an-
PECVD SiOx
ode and the cathode, respectively. When the sandwiched an-
ode–silicon–glass–cathode structure is subjected to a strong Bond
electrostatic field, the mobile alkali ions in the glass are drif- PECVD SiOx
ted away from the bonding interface, leaving a few-micron-
Si
thick depletion region. The charges left in the glass create a
large electric field. The wafer surfaces are pulled into contact
by the large electric field[57]. Therefore, anodic bonding is not Fig. 2. (Color online) (a) Schematic of the DWB process via SiO2 dielec-
strongly relying on the surface smoothness and ultraclean en- tric layers, and (b) shows the IR image of the bonded wafer.
vironment thanks to the large pulling forces. In addition, anod-
ic bonding has the advantages of low process temperature (a) (b)
and high bond strength of 10–25 MPa. However, anodic bond-
ing is limited to joining ion conductive materials with metals
or semiconductors. A sufficient amount of mobile charge carri-
ers are required, which makes it incompatible with some
MEMS devices. Thermal mismatch between the ion conduct-
ive material and the anode material is another major con-
cern. Even a small thermal mismatch can induce a noticeable
distortion in devices. Contamination from mobile charge ions
is also a challenge using anodic bonding.
Fig. 3. IR images of a bonded wafer with SiO2 dielectric layers (a) as bon-
3. Wafer bonding technique and applications ded, and (b) after post-bond annealing.
Our group has successfully demonstrated the monolithic tion. During this reaction, Si–OH groups react with each oth-
integration of Si-CMOS on SOI and III–V device layers on Si us- er and form Si–O–Si groups and H2O, as expressed by the fol-
ing wafer bonding and layer transfer techniques. In this sec- lowing formula[58]:
tion, we will discuss various DWB techniques, such as single-,
double- and multiple-bonding techniques, and their possible Si–OH + HO–Si → Si–O–Si + H O. (1)
applications. Since the high temperature growth of III–V
wafers can be completed without the presence of Si-CMOS lay- The H2O and absorbed moisture can be trapped and accu-
ers, DWB provides more temperature tolerance to pre-bond- mulated at the bonding interface to form voids.
ing processes. In addition, a plasma activation step is used to 3.1.2. Si3N4 to Si3N4 bonding
increase the surface hydrophilicity of bonding dielectric lay- To address the void formation issue after post-bond an-
ers, and it can be performed at room temperature and atmo- nealing, an additional thin Six Ny layer a capping layer was ad-
sphere pressure. Therefore, DWB also avoids the thermal dam- ded to SiO2 layers by PECVD, as shown in Fig. 4(a)[59]. The Si-
age to Si-CMOS devices during the bonding processes. NH groups from Six Ny layers react to reduce the incorpora-
3.1. Direct wafer bonding using various types of tion of –OH groups and the moisture absorption, as ex-
pressed as the following[58]:
bonding dielectrics
3.1.1. SiO2 to SiO2 bonding Si–NH + HN–Si → Si–N–Si + H . (2)
Silicon oxide (SiO2) is a widely used dielectric material in
the semiconductor industry, deposited by plasma-enhanced The IR images of the as-bonded and post-bond anneal-
chemical vapor deposition (PECVD). In this experiment, two Si ing wafers pairs with Six Ny intermediate layers are shown
wafers were pre-cleaned using standard RCA to remove organ- Figs. 4(b) and 4(c).
ic and metallic contaminants, followed by the deposition of To verify the function of the additional nitride layer, Fouri-
SiO2 by PECVD. Then additional densification was applied to re- er transform infrared (FTIR) spectra were used. From Fig. 5,
move the gas molecules or by-product residuals. After densific- the vibration mode at 3750 cm−1 for the wafers with nitride
ation, the oxide surface was polished by CMP to smoothen films stays almost flat after four days of storage compared to
the oxide surface to obtain a nearly atomically flat surface. the wafer with SiO2 film only, indicating the capping nitride lay-
After an RCA-based post-CMP cleaning step, a particle-free hy- er was acting as a moisture barrier.
drophilic surface was obtained. By bringing two wafers into in- The film stress can be determined by using a stress meas-
timate contact at room temperature, the wafers were bon- urement system, it shows that the compressive stress in Six Ny
ded. Fig. 2(a) shows the schematic of this bonding process, layers becomes tensile stress, and the tensile stress is very
and Fig. 2(b) shows the IR image of the bonded wafers. An an- stable after 10 days of storage, as shown in Fig. 6. This also in-
nealing step at 300 °C was applied after bonding to enhance dicates that the Six Ny layers block the moisture absorption
the bonding strength[11, 12]. after annealing. This can be explained by the higher density
However, as shown in Fig. 3, there are many voids after and mechanical strength, compared to SiO2.
post-bond annealing. These voids are caused by the inc- 3.1.3. AlN to AlN bonding
reased incorporation of hydroxyl groups (–OH) during anneal- AlN can also be used as the bonding dielectric, due to
ing, which can be explained by the silanol polymerization reac- its excellent properties, such as good temperature stability
(a) (b) (c)

Si
PECVD SiOx
SiN
Bond
SiN
PECVD SiOx
Si
Fig. 4. (Color online) (a) Schematic of the bonding process with an additional thin deposited Six Ny layer, and the IR images of (b) as-bonded
wafers and (c) after post-bond annealing.
100.2 crease the bonding strength. The schematic process and the
IR images are shown in Fig. 7. In Fig. 7, the unbonded areas ap-
Annealed SiOx + SiN + 4 days of storage
peared after bonding due to the presence of particles. After
100.1
post-bond annealing, there was no new formation of voids. Al-
Transmission (%)
Annealed SiOx + 4 days of storage though the performance of AlN to AlN bonding is excellent,
100.0 its bonding mechanism is not well established. We suspect
that the bonding reaction is a polymerization process of
Al–NH groups after the surface is passivated by H in DI water
99.9
rinse.
During the pre-annealing step for outgassing in a fur-
99.8 nace, the AlN thin film was prone to oxidation when ex-
3200 3400 3600 3800 4000
Wavenumber (cm−1) posed to ambient, and the high temperature at 450 °C also ac-
celerated the oxidation. With this concern, the composition
Fig. 5. (Color online) The comparison of FTIR spectral changes at the vi- of AlN thin films was verified by XPS measurement. Fig. 8
bration mode at 3750 cm–1 between the SiOx + Six Ny and SiO2 films shows the atomic concentration against the sputtering
after annealing and four-day storage under cleanroom environments. depth. The atomic ratio of Al and N are close to 1 : 1, indicat-
ing the expected composition of AlN. The surface region
400
shows a slight stoichiometry mismatch, which is possibly
20
caused by the partial oxidation by H2O or O2 in the air.
3.1.4. Al2O3 to Al2O3 bonding
200
We also investigated Al2O3 as the bonding dielectric[61–64].
Stress (MPa)
Bow (μm)
15
Tensile Al2O3 was chosen due to its higher thermal conductivity than
that of SiO2 (Al2O3: 30 Wm−1K−1 and SiO2: 1.4 Wm−1K−1). In
0
this experiment, two wafers are prepared: (i) Ge/Si wafer fabric-
10
Compressive ated by Ge directly epitaxial grown on Si (001) substrate, and
450 °C, 1 week +5 days +10 days (ii) Si (001) wafer. A 10 nm Al2O3 film was deposited on both
−200 Before anealing Ge/Si and Si (001) wafers by ALD, as shown in Fig. 9. A 15 s
5
O2 plasma activation treatment was applied, followed by DI
Fig. 6. Change in the Six Ny layers stress profile. Compressive stress water cleaning and drying on the prepared wafers. The clean-
turns into tensile stress in Six Ny layers after annealing, and its stress ing step covered the wafer surfaces with –OH groups to initi-
and bow stay stable after 10 days of storage, indicating that the mois- ate the Al–O–Al bond formation, of which the reaction is ex-
ture absorption is blocked. pressed as the following:
and high thermal conductivity (AlN: 134 Wm−1K−1 and SiO2: Al–OH + HO–Al → Al–O–Al + H O. (3)
1.4 Wm−1K−1). Similar to SiO2 to SiO2 bonding, two Si wafers
were pre-cleaned, followed by the deposition of 20 nm AlN After bonding, the post-bond annealing at 300 °C in an at-
films by sputtering aluminium in N2 atmosphere at 75 °C us- mospheric N2 ambient for 3 h was performed for bond en-
ing atomic layer deposition (ALD)[60]. After the deposition, a hancement.
pre-annealing step at 450 °C for 1 h in N2 environment was car- Fig. 10 shows a cross-section transmission electron micro-
ried out. This annealing step densifies the AlN film to sup- scope (TEM) image of the bonded wafer pair to verify the
press the void formation. Then 15 s Ar plasma activation was bonding quality at the Al2O3 bonding interface. As shown in
applied to enhance the surface hydrophilicity, followed by the TEM images, the Al2O3 bonding interface is uniform and
de-ionized (DI) water cleaning and spin rinse drying (SRD). As seamless with no sign of micro-voids. In addition, the O2
mentioned previously, the plasma activation of AlN to AlN plasma activation modified the stoichiometry of the Al2O3,
bonding was initiated at room temperature and atmospheric causing contrast differences in the Al2O3 layers.
pressure. Then, a relatively low post-bond annealing temperat- 3.1.5. Applications (‘X’-OI)
ure at 300 °C in N2 ambient for 3 h was used to further in- Silicon-on-insulator (SOI) has many advantages over Si,
(a) Ar plasma activation

Si substrate
Pre-anneal
AIN AIN AIN
Si substrate Si substrate Si substrate
Sputtering Activation Bonding & annealing
(b) (c)
Fig. 7. (Color online) (a) Schematic of AlN to AlN bonding process and the IR images of (b) as-bonded wafers, and (c) after post-bond annealing.
100 source in a silicon photonic system. In addition, since Si is the

handle wafer, some of the CMOS tools and processes can be
Al 2p
shared with these new insulators.
Atomic concentration (%)
80 N 1s
O 1s In this section, we present a scalable method to fabric-
Si 2p ate high-quality Ge-OI wafers[61–64]. The fabrication involves
60
the processes of direct Ge epitaxial growth on Si, fusion bond-
40 ing, and layer transfer. The fabrication of GaAs-OI and GaN-OI
wafers will also be discussed.
20 In the Ge-OI fabrication experiment, two sets of wafers
were prepared: (i) Ge films epitaxially grown on 200 mm Si
0
donor wafer using a metal organic vapor deposition
0 10 20 30 40 50 60 (MOCVD), and (ii) Si (001) handle wafer. A 10 nm thin Al2O3 lay-
Sputtering depth (nm)
er was deposited on each prepared wafer by ALD.
Fig. 8. (Color online) XPS Atomic concentration profiles of pre-an- The bonding process was similar to Al2O3 to Al2O3 bond-
nealed AlN. ing as described previously. SiO2 can be used as the bonding
dielectric as well. After bonding and post-bond annealing,
Bond the donor Si substrate was removed through mechanical grind-
ing and selective wet etching in 80 °C tetramethylammoni-
um hydroxide (TMAH) solution, which etch-stopped at the Ge
Al2O3 layer. The backside of the handle wafer was protected with
Ge/GaAs Al2O3 spin-coated ProTEK® B3-25 films during TMAH etching. Then
the O2 plasma with the power of 800 W was applied to re-
Si donor wafer Si handle wafer move the protective coating. The schematic of the Ge-OI fabric-
ation process flow is shown in Fig. 11.
The Ge-OI substrate was annealed at 850 °C in O2 environ-
Fig. 9. (Color online) Schematic of Al2O3 to Al2O3 bonding process. ment for 4 h, followed by CMP process, to reduce the misfit dis-
location by oxidation, and the threading dislocation densit-
(a) (b) ies (TDDs) by annihilation. After that, HF etching (49% HF :
21.97 nm H2O = 1 : 20, by volume) for 30 s to remove the oxidized Ge
Si 4.22 nm
layer, a Ge film with a low TDD of mid-106 cm–2 was
1300.29 nm 6.39 nm achieved. This TDD level of the Ge is good enough for the Ge
Ge film is good enough for most electronic and optoelectronic
5.02 nm
device applications.
500 nm Ge TEM and etch-pit density (EPD) methods were used to
Al2O3 5 nm 6.29 nm
Si
characterize the Ge film quality. Plan view TEM shows the Ge-
Fig. 10. Cross-sectional TEM images of (a) the bonded wafer pair, and OI surface before and after O2 annealing, as shown in Fig. 12.
(b) the bonding interface. It shows that the TDD was reduced by 1 order of magnitude
after annealing. As EPD is a fast and cheap method, it was
such as reduced parasitic capacitances and short channel ef- used to quantify the TDD of the Ge film after annealing and
fects. Similar to SOI, the germanium-on-insulator (Ge-OI) and CMP by etching the sample in iodine solution for 1 s. As
other III–V materials-on-insulator (‘X’-OI) are not only used as shown in Fig. 13, the EPD counted TDD was reduced by two
the substrates, but also as active layers, such as the light orders of magnitudes from (5.2 ± 0.45) × 108 to (2.5 ± 0.4) ×
Bond Si donor wafer Etch by

TMAH
Ge
Al2O3 Al2O3 Ge
Ge Al2O3
Al2O3 Si handle wafer
Si donor wafer Si handle wafer Si handle wafer
ProTEK® B3-25
Fig. 11. (Color online) Schematics of Ge-OI fabrication process.
Before annealing After annealing Ge-OI GaAs-OI GaN-OI

~20 treading dislocations ~2−3 treading dislocations
200 nm 200 nm GaAs: 310 nm GaN: 300 nm

SiO2: 320 nm SiO2: 500 nm
Ge: 1200 nm
Fig. 12. Plan view TEM images of the Ge surface of Ge-OI before and Al2O3: 30 nm Si substrate Si substrate
after O2 annealing. Si substrate
TDD: 2.4 × 106 cm−2 TDD: 5.3 × 106 cm−2 TDD: 4.0 × 108 cm−2
Before annealing After annealing + CMP FWHM (004): 150″ FWHM (004): 155″ FWHM (102): 400″
5.8 × 108 cm−2 2.4 × 106 cm−2 Roughness: 0.3 nm Roughness: 0.4 nm Roughness: 28 nm
Fig. 15. (Color online) The fabricated 200 mm Ge-OI, GaAs-OI and
GaN-OI substrate wafers.
removed by etching and subsequent O2 annealing, therefore

5 μm 5 μm Ge is no longer constrained by Si, which led to a nearly
stress-free state.
Fig. 13. The EPD determined TDD of the Ge of Ge-OI before annealing GaAs-OI and GaN-OI substrate can also be fabricated
and after annealing + CMP. through similar bonding processes as shown in Fig. 15. De-
pending on applications, various bonding dielectrics (SiO2,
8000
Without annealing Al2O3 or AlN) can be chosen.
O2 annealing
Bulk Ge In summary, the ‘X’-OI substrate can be fabricated
6000 through buffer-less III–V epitaxy, bonding and layer transfer.
This method is scalable to various wafer sizes and makes the
Intensity (a.u.)
Ge−Ge CMOS devices with III–V/Si integration on common Si wafers

4000 become possible.
peak
3.2. Double bonding and layer transfer for Si-CMOS
2000 290 295 300 305 310 and III–V/Si integration
Raman shift (cm−1) Si−Ge peak
With the optimized bonding processes as described previ-
0 ously, in this section, we demonstrate a method to integrate
250 300 350 400 450
Raman shift (cm−1)
III–V compound semiconductor materials with SOI-CMOS on
a common Si substrate[11–13, 65, 66]. Firstly, the SOI-CMOS layer
Fig. 14. (Color online) Raman spectroscopy of the Ge film on Ge-OI be- is temporarily bonded on a Si handle wafer. Then, the III–V
fore and after annealing. on Si wafer is bonded to the SOI-CMOS + Si handle wafer. Fi-
nally, the SOI-CMOS on III–V/Si hybrid structure on a com-
106 cm–2 after annealing and CMP.
mon Si substrate is realized by releasing the Si handle wafer.
To determine the alloy composition and strain of the Ge With this double bonding and layer transfer method, several is-
film, Raman spectroscopy was used. As shown in Fig. 14, sues encountered with SOI-CMOS and III–V/Si integration can
there was no signal of the Si–Si vibration mode as the Si from be addressed: (i) the cross-contamination issue between
the donor wafer was removed completely by TMAH. After O2 CMOS and III–V materials in foundries processes, and (ii) high
annealing, the signal of the Si–Ge vibration mode disap- temperature CMOS processes which may cause serious dam-
peared as the Si/Ge intermixed layer was removed. The inset age for III–V material systems such as arsenide (As)/phos-
figure shows a blue shift of the Ge–Ge vibration peak from phide (P) containing III–V materials (e.g., InGaAs, InP, etc.).
296 to 302 cm−1 after O2 annealing, indicating the Ge film of Hence, with this double bonding and layer transfer method,
the Ge-OI was nearly stress-free after annealing. This may due III–V material growth can be completely separated with
to the amorphous nature of Al2O3 layer which acts as a CMOS processes, thus the damage to both the III–V layer and
stress-free buffer. Also, the Si and Ge/Si intermixed layer were CMOS layer can be avoided.
1st bonding
Bottom Si substrate
Thermally oxidized Si removal
handle wafer
SiO2 (BOX) SiO2
Thermally oxidized Si
handle wafer
SOI-CMOS SiO2 (BOX)
SiO2
(Donor)
Si SiO2 (BOX)
SOI/BOX = 1 μm/0.4 μm
2nd bonding
Handle wafer release Thermally oxidized Si

handle wafer
SiO2 (BOX)
SiO2
III−V SiO2 (BOX)
III−V
Substrate
Substrate
Fig. 16. (Color online) Schematic flow of the double bonding and layer transfer process.
(a) Patterned SOI (b)

particles from the III–V/Si may also contribute to the unboun-
Si handle wafer
SiO2
ded area.
SiO2 (BOX) 3.2.2. Replacement of the BOX layer with PECVD oxide
SiO2 (BOX)
SOI-CMOS To tackle the pin-holes issue associated with the BOX lay-
(Donor) SOI-CMOS
(Donor) er, the BOX surface was planarized by CMP process. Right
Fig. 17. (Color online) (a) Schematic flow of the first bonding process after the CMP step, RCA-based cleaning was carried out, fol-
between SOI and thermally oxidized Si handle wafer and (b) IR image lowed by a de-ionized (DI) water rinse and spin dry using
of the bonded wafer pair. spin rinse dryer (SRD). However, the pin-hole problem be-
came more obvious and was worse after the CMP process, as
In this experiment, three sets of wafers were prepared: shown in Fig. 20.
(i) p-type 200 mm Si (001) prime-grade wafers (as Si handle The next attempt to address the pin-hole problem was
wafer), (ii) patterned silicon-on-insulator (SOI) wafer, with Si to use an additional 50 nm SiO2 deposited by plasma-en-
and buried oxide (BOX, thermal SiO2), and (iii) III–V on Si hanced CVD (PECVD), as a compensation layer on top of the
wafer (e.g., InGaAs/GaAs/Ge-on-Si or GaN-on-Si) wafers. The BOX layer. The addition of the PECVD oxide roughens the ox-
schematic flow diagram of the process is shown in Fig. 16. ide surface, which prevents a successful wafer bonding in the
3.2.1. First bonding (between SOI wafer and thermal subsequent step. Therefore, after the PECVD oxide, densifica-
tion was carried out and followed by the CMP process to
oxidized Si handle)
planarize the oxide surface. However, after the second bond-
The first bonding was between the patterned SOI wafer
ing, there are still many unbonded areas observed in the bon-
and thermally oxidized Si handle wafer. The bonding quality
ded wafer pair, as shown in Fig. 21.
was justified using the IR camera, where any interface voids
Then the third attempt to avoid the pin-holes problem
formed between the bonded wafer pair can be observed. As
was to remove the BOX layer completely and replace it with
shown in Fig. 17, no significant voids or particles are ob-
PECVD oxide. The sub-standard quality BOX layer was re-
served from the IR image, which indicates an excellent bond-
moved by diluted HF solution (with volume ratio HF : H2O =
ing quality between the SOI wafer and thermally oxidized Si
1 : 10), and followed by PECVD oxide deposition. CMP was car-
handle wafer.
ried out to smoothen the PECVD oxide for the second bond-
After the first bonding, the Si from the SOI-CMOS donor
ing process. Then, the wafer with the PECVD oxide was bon-
wafer was ground down to 50 μm, followed by TMAH chemic-
ded to another Si prime wafer (no III–V layers). The bonding
al etching to completely remove the remaining Si, which
quality is verified with the IR image. No significant void is ob-
etched stopped at the BOX layer. However, the BOX layer is
served, as shown in Fig. 22.
slightly damaged by the TMAH solution, and a lot of pin-
holes are formed and can be observed, as shown in Fig. 18. 3.2.3. Second bonding (between SOI-handle pair and Si
We believed that this could be due to the slight etching on prime wafer)
the sub-standard quality BOX, where the thermal oxide of the The second bonding was performed between the SOI-
BOX is grown using relatively low-quality wet oxidation in- handle pair and a Si prime wafer. The Si handle wafer was
stead of higher quality dry oxidation. then completely removed by grinding and chemical etching.
After the first layer transfer, the SOI-CMOS is now on the With the CMP-on-BOX method, after the double bonding and
Si handle wafer. The second bonding is performed between layer transfer process, delamination is observed on the sur-
the patterned SOI and III–V/Si wafer. The IR images of the In- face of the bonded SOI–Si wafer. The delamination area is cor-
GaAs and GaN are shown in Fig. 19. Unbounded areas are ob- responding to the un-bonded area due to the pin-hole issue.
served due to pin-holes on the BOX layer. In addition, the A similar delamination issue is also expected for the PECVD-ox-
(a) Botttem Si substrate (b)

Patterned SOI Si handle wafer removal
SiO2
SiO2 (BOX)
Si handle wafer
SiO2 (BOX)
SOI-CMOS
(Donor) SOI-CMOS
(Donor) SiO2 (BOX)
Fig. 18. (Color online) (a) Schematic flow of the first bonding and substrate removal and (b) optical image of the bonded pair after substrate remov-
al where pin-holes are observed.
Botttem Si substrate
Patterned SOI Si handle wafer removal
SiO2
SiO2 (BOX)
Si handle wafer
SiO2 (BOX)
SOI-CMOS
(Donor) SOI-CMOS
(Donor) SiO2 (BOX)
(a) (b)
2nd bonding
Si handle wafer
SiO2 (BOX)
PEVCD SiO2
III−V
Substrate
Fig. 19. (Color online) Schematic flow of the double bonding process. (a) IR image of bonded SOI –InGaAs pair and (b) IR image of bonded
SOI–GaN pair.
(a) 1st bonding (b)
Si handle wafer
SiO2 (BOX) SiO2
SiO2 (BOX)
Si
Si
Removal the botttem

Si of SOI
Si handle wafer Si handle wafer

SiO2 SiO2
SiO2 (BOX) SiO2 (BOX)
Fig. 20. (Color online) (a) Schematic flow of 1st bonding with CMP-ed BOX layer. (b) Optical image of the resultant wafer after the process, where
pin-holes are observed.
ide-on-BOX method. By completely removing the BOX layer ing method.

and replacing it with PECVD oxide, a clean surface with an al- The Si handle wafer was then removed by mechanical
most defect-free SOI–Si wafer pair is successfully demon- grinding and wet chemical etching as described previously.
strated after the second bonding and removal of the handle Film peeling was observed from the SOI–Si wafer as shown in
wafer. Fig. 23 (the bottom row). The delaminated area is even lar-
Fig. 23 (the top row) shows a comparison after the ger than the unbounded area before Si handle removal, due
second bonding. For the CMP-on-BOX method, unbonded to the weak bonding strength around the unbounded area,
areas are observed across the entire wafer. Many unbonded which leads to easier film delamination when the handle
areas can be observed for the PECVD SiO2 (-on-BOX) method wafer is released.
as well. Almost defect-free wafer is observed for the BOX etch- Cross-sectional TEM is used to exam the quality of SOI–Si
(a) 1st bonding

Removal the botttem
Si from SOI
Si handle wafer
SiO2 (BOX)
SiO2 Si handle wafer
SiO2 (BOX)
Si SiO2
Si SiO2 (BOX)
(b)
2nd bonding
Si handle wafer
Si handle wafer
SiO2
SiO2
SiO2 (BOX)
SiO2 (BOX) PECVD SiO2
PECVD SiO2
Si prime wafer
·CMP is carried out
Fig. 21. (Color online) (a) Schematic flow of the double bonding process with additional SiO2 layers. (b) IR image of the bonded wafer pair.
(a) 1st bonding

Removal the botttem
Si from SOI
Si handle wafer
SiO2 (BOX) SiO2 Si handle wafer

Si SiO2 (BOX)
SiO2
Si SiO2 (BOX)
(b)
2nd bonding
Si handle wafer
Si handle wafer
SiO2
SiO2
PECVD SiO2
PECVD SiO2
Si prime wafer
·CMP is required.
Fig. 22. (Color online) (a) Schematic flow of double bonding process with BOX layer completely replaced by PECVD oxide. (b) IR image of the bon-
ded pair. No pin-holes are observed.
CMP on BOX PECVD SiO2 BOX etching (a) (b)
Si
~1 μm
SiO2
150 nm
Si prime wafer
0.5 μm 5 nm
Fig. 24. Cross-sectional bright field TEM images of the bonded SOI-Si
wafer pairs. (a) The overall view and (b) the bonding interface
between PECVD oxide and Si prime wafer.
the microscale level with the PECVD-oxide-only method has

Fig. 23. (Color online) IR images and optical images of wafers after
been successfully achieved.
double bonding and layer transfer using different methods.
3.2.4. Applications: Bonding approach for Si-CMOS +
bonding interface after double bonding and layer transfer pro- III–As/P or III–N HEMT/LED wafers
cess using BOX etching method, as shown in Fig. 24. The bond- We use the same process flow as described previously to
ing interface between PECVD oxide and Si prime wafer are demonstrate the integration of Si-CMOS + III–As/P HEMT or
smooth and uniform, with no significant micro-voids are ob- LED wafer. Now the actual Si-CMOS devices wafer and the
served in the field of view. Therefore, a seamless bonding at III–As/P with device layers are used instead of the prime Si
(a) Bottom Si substrate (b)

Si handle wafer removal
S G D SiO
STI
2
Si handle wafer
SiO2 (BOX)
SiO2 (BOX)
CMOS-SOI
(Donor) SOI-CMOS
(Donor) SiO2 (BOX)
(a) (c)
(b)
Si handle removal 2nd bonding

Si handle wafer BOX removal and PEVCD
SiO2 + SiN deposition (c)
PECVD SiO2
SiN
PECVD SiO2
III−As/P HEMT or LED PECVD SiO2 Si handle wafer

SiN
PECVD SiO2
III−As/P HEMT or LED

Si (001) wafer PECVD SiO2
SiN
Si (001) wafer (d)

(f)
(e)
Fig. 25. (Color online) (a) Updated schematic diagram of the double bonding and layer transfer process. (b) IR image and (c) optical image of the
resultant SOI–III–V/Si integrated wafer.
(a) Before bonding (b) After bonding with Si-CMOS

(004) RSM (004) RSM
Qz (nm) in [001] direction

7.10 7.10
D G S p-AlGaInP
STI Si STI 7.05 7.05
Ge + GaAs
Bonding dielectrics 7.00 n-AlGaInP 7.00
6.95 6.95
0.74 0.76 0.78 0.80 0.74 0.76 0.78 0.80
AlGaInP MQW Qx (nm) in [110] direction Qx (nm) in [110] direction
(c) Before bonding (d) After bonding with Si-CMOS

(224) RSM (224) RSM
7.65 7.65
Ge buffer p-AlGaInP
7.60 7.60
1 μm Ge + GaAs
Si substrate 7.55 n-AlGaInP 7.55
Fig. 26. Cross-sectional TEM image of the Si-CMOS/III–V/Si wafer after 7.50 7.50
double bond and layer transfer.
−4.25 −4.20 −4.15 −4.10 −4.25 −4.20 −4.15
Qx (nm) in [110] direction Qx (nm) in [110] direction
wafer. Therefore, the second bonding Si3N4 to Si3N4 bonding
discussed in the previous section will be used. The updated Fig. 27. (Color online) Symmetric (004) reciprocal space map (RSM) of
an AlInGaP LED structure measured from XRD (a) before and (b) after
schematic flow is shown in Fig. 25 below.
bonding with Si-CMOS. Asymmetric (224) RSM of the AlInGaP LED struc-
Three sets of 200 mm wafers were prepared for this expe-
ture (c) before and (d) after bonding with Si-CMOS.
riment: (i) Si (001) wafers, (ii) Si-CMOS/SOI wafers that have
undergone front-end-of-line (FEOL) processing only in Si
clean the wafers and to populate the surface with hydroxyl
foundries, (iii) InGaAs HEMT or AlInGaP LED epitaxial films
(–OH) groups at a sufficiently high density to initiate wafer
which were grown directly on GaAs/Ge/Si (001) wafers with
bonding. The post-bonding was performed at 300 °C in an at-
6° off-cut toward the [110] direction by MOCVD.
The Si-CMOS/SOI wafer was first deposited with 500 nm mospheric pressure N2 ambient for 3 h to further increase the
PECVD SiO2 layer, followed by densification process in N2 envir- bond strength. The Si substrate from the SOI wafer was then
onment to eliminate the residual gas molecules and by- completely removed by mechanical grinding and wet chemic-
products incorporated into the layer during oxide deposition. al etching in trtramethylammonium hydroxide (TMAH) solu-
Then the oxide surface was planarized by chemical mechanic- tion, to realize the first layer transfer.
al planarization (CMP). Before the first bonding, both the SOI For the second bonding and layer transfer process, the
wafer and Si handle wafers were subjected to O2 plasma expos- BOX layer was first removed in HF solution and replaced with
ure to increase the surface hydrophilicity. Then both wafers PECVD oxide, followed by densification and planarization,
were rinsed with de-ionized (DI) water and spin-dried to and additional PECVD Si3N4 (with densification) layer depos-
Si (001) donor 2 Removal of Si (111)

PECVD SiO2
III−N HEMT or LED Si (001) donor 2

PECVD SiO2
Buffer layers III−N HEMT or LED
Buffer layers PECVD SiO2
Si (111) donor III−N HEMT or LED

Si (111) donor 1 Buffer layers
Removal of Si (111) donor 2 Si (001) donor 2

PECVD SiO2 Si (001) donor 2
III−N HEMT or LED
PECVD SiO2
Buffer layers PECVD SiO2
PECVD SiO2 III−N HEMT or LED III−N HEMT or LED

SiN
PECVD SiO2/SOG Buffer layers Buffer layers
PECVD SiO2/SOG
PECVD SiO2/SOG SiN
SiN
Si (001) carrier PECVD SiO2
Si (001) carrier
Fig. 28. (Color online) Schematic flow of replacing Si (111) substrate by Si (001) substrate for GaN HEMT/LED wafer.
ition, to address the pin-holes and outgassing issues. Then,

the III–V/Si wafers (InGaAs HEMT, AlGaInP LED epitaxial films
on Si) were also subjected to the same PECVD oxide and ni-
tride deposition processes. After that, the two sets of wafer
pairs were bonded together, followed by Si handle release to
realize the Si-CMOS/III–V on Si wafer.
The cross-sectional TEM image in Fig. 26 shows the stack
of Si-CMOS + InGaP LED on a common Si platform. A smooth
and clean bonding interface can be observed with no micro-
voids between two PECVD Si3N4 layers. A uniform and seam-
less bonding at the microscale level is successfully demon-
strated.
Non-destructive X-ray diffraction (XRD) measurements
were used to characterize the properties of the AlInGaP LED
wafer before and after the bonding process. There is no signi- Fig. 29. IR image of a bonded GaN/Si wafer pair after substrate replace-
ficant change in the peak positions and full widths at half max- ment.
imum (FWHMs) of the active p-AlGaInP and n-AlGaInP layers,
as well as the Ge + GaAs buffer layers, as shown in the recip- up the stress levels on the Si (111) substrate which ulti-
rocal space map (RSM) from Fig. 27. This confirms that the mately makes the Si substrate even more fragile.
bonding process does not significantly compromise the film Although minimizing the radical temperature difference
quality. across the Si (111) wafer during the III–N growth will reduce
Similar double bonding and layer transfer process de- the slip line formation and improve the wafer fragility, it is
scribed above was also applied for the integration of Si- impossible to fully eliminate vertical temperature differen-
CMOS + III–N (e.g., GaN) HEMT or LED wafers. However, due ces through the wafer during the growth. In our MOCVD re-
to the high-temperature MOCVD grown GaN on Si (111) actor, because the heating is only performed from the back-
wafers, the Si-CMOS + GaN HEMT/LED transfer yield is only side of the wafer. Thus, to address this issue, we introduced
~50%. an additional wafer bonding and layer transfer processes, to re-
This is mainly because during the high temperature GaN place the fragile Si (111) substrate by a new Si (001) sub-
growth, slip lines formed at the wafer edge which propag- strate, the process flow of this substrate replacement is
ated towards the center of the wafer weakens the Si (111) shown in Fig. 28.
wafer and makes the wafer brittle. In addition, for the direct First, a PECVD SiO2 layer was deposited onto the III–N
epitaxially grown GaN-on-Si wafer, the AlGaN buffer layers HEMT/LED on the Si (111) (donor 1) wafer, followed by densific-
and GaN layers contribute different levels of stress and build ation and CMP processes. Then, a Si (001) (donor 2) wafer
(a) (b) (c)
GaN with buffer (4 μm) GaN with buffer (4 μm)

GaN with buffer (4 μm)
Si (111) Si (111)
Si (111)
GaN-on-Si wafer
GaN-on-Si wafer GaN-on-Si wafer
Fig. 30. (Color online) Schematic flow of the diamond CMP process. (a) After oxide deposition, (b) after CMP using slurry with the addition of dia-
mond particles, and (c) another oxide deposition and CMP processes to smoothen the oxide surface which was roughened from the previous
step.
was bonded to the III–N HEMT/LED wafer, followed by post- (a) (b)
bonding annealing. After that, the Si (111) (donor 1) sub-
strate was completely removed through a combination of
mechanical grinding and wet-chemical etching in HNA solu-
tion (hydrofluoric + nitric + acetic acids). The bonded wafer
and a new Si (001) (carrier) substrate were then subject to
PECVD SiO2 deposition, and the subsequent densification,
CMP and Si3N4 deposition processes, as described previously.
The two wafers were then bonded and annealed. The III–N
HEMT/LED on a fresh Si (001) (carrier) substrate was realized Fig. 31. (a) IR image, (b) optical image of Si-CMOS and GaN LED bon-
by removing the Si (001) (donor 2) wafer. It was then can be ded pair on Si (001) substrate.
bonded to the Si-CMOS-containing wafer to realize the Si-
CMOS + III–N HEMT/LED integration. 3.2.5. Applications: GaN LED-on-quartz
Through this Si (111) substrate replacement method, the With the successful demonstration of Si-CMOS + GaN
yield of the integrated Si-CMOS + GaN HEMT/LED wafers is al- LED integration, there are two issues need to be addressed:
most 100% after the subsequent bonding and transfer pro- (i) surface protrusions (which has been addressed in the previ-
cesses without additional precautions. ous section), and (ii) lower light-emitting efficiency of the
For Si-CMOS + III–N bonding, particle issue is another prob- GaN LEDs due to the absorption of photons by the Si sub-
lem that needs to be addressed. These particles found at the strate. In this section, we address the second issue by repla-
III-N surfaces are mainly melt-back etching and hillock sites cing the absorbing Si substrate with a transparent quartz sub-
come from the showerhead MOCVD reactor growth. The strate[67, 68], to achieve brighter GaN LEDs.
melt-back etching is characterized as a void on the surface of Three sets of wafers were prepared in this experiment: (i)
the wafer and a large surrounding area of materials with sur- Si (001) wafers, (ii) quartz substrate and (iii) GaN LED on Si
face protrusions containing polycrystalline III–nitride and Si (111) substrates epitaxially grown by metalorganic chemical va-
eutectic. In the epitaxy process of III–nitride, hillocks or por deposition (MOCVD). The schematic flow of the bonding
hexagonal voids could be created due to material defects process is shown in Fig. 32 below.
such as inversion domain boundary, stacking faults and thre- First, a 500 nm PECVD oxide layer was deposited on the
ading dislocations. Since these particles are big protrusions GaN LED wafers to serve as a capping layer for CMP process
on the wafer surface with the size of several micrometers, as well as a bonding interface, followed by the densification
this affects the quality of the subsequent wafer bonding as process at 600 °C in N2 environment. After densification, the
shown in the IR image below, see Fig. 29. To solve this prob- oxide surface was CMP-ed, and subjected to O2 plasma to in-
lem, we use diamond containing slurry for CMP to flatten the crease the surface hydrophilicity, followed by DI water rinse
surface. and spin-dried to clean the surfaces and to populate the sur-
With PECVD SiO2 deposition on the as-grown III–nitride face with hydroxyl (–OH) groups to initiate wafer bonding.
wafers, the height difference caused by surface protrusions The bonded wafer pair was then subjected to post-bond-
will remain after the PECVD process as illustrated in the schem- ing annealing at 300 °C in an atmospheric pressure N2 ambi-
atic drawing, Fig. 30(a). To remove the hard III–nitride ent for 3 h to further increase the bond strength. The Si (111)
particles, additional diamond particles were added into the substrate was then completely removed by mechanical grind-
normal SiO2 slurry. As a result, melt-back sites and hillocks ing and wet-etching in HNA solution (hydrofluoric + nitric +
were all reduced to about the same height as the remaining acetic acids). The GaN LED epilayers were temporarily at-
SiO2, as shown in Fig. 30(b). A thin remaining layer of SiO2 tached to the Si handle wafer.
was left behind to protect the GaN surface from being dam- Another 500 nm of PECVD oxide was deposited on the
aged by the CMP process. After that, a thin layer of PECVD GaN LED + Si bonded pair, followed by 50 nm PECVD Si3N4 de-
SiO2 is deposited and CMP-ed for the subsequent bonding pro- position and densification. The quartz substrate was also sub-
cess. jected to the same PECVD oxide and the nitride deposition pro-
With the substrate replacement and diamond CMP processes. After that, the GaN-LED-handle wafer was bonded to
cesses, robust and void-free bonding of Si-CMOS-containing quartz substrates. Similar grinding and wet-etching pro-
wafer + III–nitride HEMT/LED on Si (001) substrate can be real- cesses (TMAH solution was used in this case) were per-
ized, as shown in Fig. 31. formed to remove the Si handle wafer to realize the GaN-LED
Si handle wafer
GaN LED Si handle wafer
PECVD SiO2
Si (111) GaN LED PECVD SiO2
GaN LED
(a) Si (111)
(c)
(b)
Si handle wafer
GaN LED Si handle wafer
PECVD SiO2 PECVD SiO2
PECVD SiO2
PECVD Si3N4 GaN LED
GaN LED
PECVD SiO2 PECVD SiO2
PECVD SiO2
Quartz PECVD Si3N4 PECVD Si3N4
Bonding
(f) PECVD SiO2 interface (d)
Quartz
(e)
Fig. 32. (Color online) Schematic of the process flow to realize the GaN LED on quartz substrate. (a) A GaN LED epitaxial film on a Si (111) sub-
strate. (b) First wafer bonding between the GaN LED on Si (111) and a Si handle wafers. (c) Removal of the Si (111) substrate. (d) Deposition of
SiO2 and Si3N4 layers. (e) Second wafer bonding between the GaN LED-containing handle and a quartz substrate. (f) GaN LED on quartz sub-
strate is realized by releasing the Si handle wafer.
(a) (b)
PECVD oxide
GaN LED
(c) (d)
SiO2/Si3N4/SiO2
Quartz substrate
5 μm
SMART LEES
Fig. 34. SEM image of the cross-sectional view of the bonded GaN LED
on the quartz substrate.
Fig. 33. (Color online) (a) IR image of a bonded GaN LED/Si (111) sub-
(a) (b)
strate and a Si handle wafer after step Fig. 32(b). (b) Photograph of
the GaN LED layers temporarily attached to the Si handle wafer after
Si (111) substrate removal, step Fig. 32(c). (c) IR image of the bonded
GaN LED layers containing Si handle wafer and a quartz substrate
after step Fig. 32(e). (d) Photograph of the GaN LED transferred to the
quartz substrate, step Fig. 32(f).
on the quartz substrate.

As shown in the IR image in Fig. 33(a), the bonding qual-
ity between GaN LED on Si (111) substrate and a Si handle Fig. 35. (Color online) Light-up photo of the GaN LED devices on (a) Si
wafer is excellent with no observable voids or particles. and (b) quartz substrates.
Fig. 33(c) shows the GaN LED-containing handle wafer has an
excellent bonding yield after the Si (111) substrate was re- between the two PECVD Si3N4 layers. This indicates a success-
moved completely. The bonding quality is slightly degraded ful bonding at the microscale level, with a smooth and uni-
due to the presence of undesired particles which cause un- form bonding interface.
bounded areas. The light-up GaN LEDs on Si and quartz substrate are
The SEM image shows the cross-sectional view of the lay- shown in Fig. 35. The light emitting efficiency is greatly en-
er stack of the GaN LED on the quartz substrate, see Fig. 34. hanced when the GaN LED epitaxial layers are transferred to
No micro-voids were observed at the bonding interface the quartz substrate.
Botttem Si substrate
Si handle wafer removal
SiO2
Si Si handle wafer
SiO2 (BOX)
SiO2 (BOX)
SOI-CMOS
(Donor 1) SOI-CMOS
(Donor 1) SiO2 (BOX)
3rd bonding 2nd bonding

Si donor 2 release
Si handle wafer
Si handle wafer
Si handle wafer
PEVCD SiO2 PEVCD SiO2

SiN SiN
PEVCD SiO2 PEVCD SiO2
PEVCD SiO2
GaAs/Ge SiN
PEVCD SiO2
GaAs/Ge
PEVCD SiO2
SiN
PEVCD SiO2
GaAs/Ge
GaN Si donor 2
AlGaN buffers
AIN
Si (111) carrier
Si handle removal
Si
PEVCD SiO2
SiN
PEVCD SiO2
GaAs/Ge
PEVCD SiO2
SiN
PEVCD SiO2
GaN
AlGaN buffers
AIN
Si (111) carrier
Fig. 36. (Color online) Schematic flow of the multi-bonding and layer transfer process for integration of Si-CMOS and GaAs and GaN together on
a common 200 mm Si platform.
3.3. Multi-bonding and layer transfer for multi-wafer ic flow of the bonding and layer transfer process is shown in
Fig. 36.
stacking
The SOI wafer was first deposited with a 500 nm PECVD
We have successfully demonstrated the integration of oxide, followed by the densification process in a furnace and
the Si-CMOS and III–V/Si or III–N/Si on a common 200 mm Si planarization process by a CMP machine. Then the CMP-ed
platform through a double bonding and layer transfer pro- SOI wafer and Si handle wafers were subjected to O2 plasma
cess in the above section. In this section, we would like to fur- exposure to increase the surface hydrophilicity, followed by
ther extend the bonding capabilities to multi-layer stacking. rinsing with de-ionized water and spin-dried to clean the
Through this method, the integration of Si-CMOS control cir- wafer surface. After bonding, the same post-bonding anneal-
cuitry, III–As/P and III–N functional materials can be stacked to- ing and Si substrate removal process were carried out, to real-
gether on a single 200 mm Si platform[69], to realize more com- ize the SOI layer on Si handle wafer. The details have been dis-
plexed functionalities. cussed in previous sections.
Four sets of wafers were prepared in this experiment: (i) The BOX layer was removed on the SOI containing the Si
Si handle wafer, (ii) silicon-on-insulator (SOI) wafer (with 1.3 handle to address the pin-holes issue as discussed previously.
μm Si, and 0.4 μm thermally oxidized BOX), (iii) GaAs/Ge/Si Then both the SOI and GaAs/Ge/Si donor wafer were subjec-
(001) donor wafer (GaAs/Ge layer were epitaxially grown on ted to PECVD oxide and nitride deposition processes for the
Si(001) wafer with 6° off-cut toward the [110] direction by subsequent bonding. The second bonding process was simil-
MOCVD), and (iv) GaN/Si (111) carrier wafer (GaN layer were ar to that described above. After a combination of grinding
epitaxially grown on Si (111) wafer by MOCVD). The schemat- and chemical etching processes to remove the Si donor
(a) (b)
Un-bonded due
to particle
Si from SOI
(c) (d)
GaAs
Ge
Un-bonded due
to particle
Fig. 37. (Color online) IR image of (a) the first bonding between SOI
and Si handle wafer, (b) the second bonding between the SOI-handle GaN
and the GaAs/Ge/Si substrate, (c) the third bonding between the
GaAs/Ge-SOI-handle and the GaN/Si substrate, and (d) optical image
of the SOI-GaAs/Ge/GaN/Si substrate after the triple-bond process.
The red circle indicates the defects from the backside of the wafer dur-
AlGaN buffers
ing TMAH etching caused by the poor adhesion of the protective lay-
er, not affecting the bonding quality.
AIN buffers
wafer from the GaAs/Ge/Si substrate, the GaAs/Ge-SOI-contain-
ing handle wafer was realized.
The same process was repeated for the third bonding
Si (111) substrate
between GaAs/Ge-SOI-handle and GaN/Si carrier substrate. Fi-
nally, the SOI-GaAs/Ge/GaN/Si substrate was realized. 0.5 μm
From the IR image, as shown in Fig. 37(a), the quality of
the first bonding is excellent and no significant voids or Fig. 38. The cross-sectional TEM of the SOI –GaAs/Ge/GaN/Si stack
particles are observed. For the second bonding, as shown in after the triple-bonding and layer transfer process.
Fig. 37(b), some unbonded areas are observed, especially at
the wafer edge. This is due to the presence of particles Si CMOS GaN PA GaAs HEMT
trapped between the bonded pairs, which degrade the over- ILD W
all bonding quality. For the third bonding, as shown in Si
Bonding dielectrics
Fig. 37(c), more unbonded areas are observed due to the pres-
III−As/P
ence of particles from the GaN/Si surface and the unboun-
Bonding dielectrics
ded areas originating from the second bonding. Fig. 37(d)
III−N
shows the optical image of the final SOI-GaAs/Ge/GaN/Si
wafer stack.
Si substrate
Cross-sectional TEM is used to assess the quality of the
SOI–GaAs/Ge/GaN/Si wafer after the triple-bonding and layer
transfer process, as shown in Fig. 38. A smooth and uniform Fig. 39. (Color online) The schematic of Si-CMOS, high frequency GaAs
surface with no micro-voids is observed at the two bonding in- HEMT, and high power GaN PA integrated on a single piece of wafer.
terfaces, indicating a successful bonding at the microscale
level. been demonstrated successfully. The associated pin-holes is-
Through this multi-bonding and layer transfer process, dif- sues, surface roughness issues, bonding yield issues and
ferent group III–V and group IV materials with different func- particle issues have been addressed.
tionalities can be integrated on a single Si platform. As By the DWB and layer transfer processes, integration of
shown in Fig. 39, it is possible to integrate the Si-CMOS con- Si-CMOS (on SOI) and III–V or III–N compound semiconduct-
trol circuitry, high-frequency devices (e.g., HEMTs on a GaAs ors (e.g., InGaAs HEMT, AlInGaP LED, GaN HEMT, or InGaN
layer), and high-power devices (e.g., power amplifier (PA) on LED) on a common Si substrate is demonstrated. In addition,
a GaN layer) vertically onto a common substrate. high temperature III–V or III–N materials growth can be com-
pleted without the presence of the CMOS layer, hence dam-
4. Summary and conclusion age to the CMOS layer can be avoided.
In this paper, single-bonding, double-bonding, multi-bond- The monolithic integration of Si-CMOS + III–V devices on
ing and layer transfer processes, and its applications have a common Si platform enables a new generation of systems
with more functionality, better energy efficiency, and smaller Devices Meeting (IEDM), 2019, 12.5. 1
form factor. This paves the way for new circuits and applica- [19] Gösele U, Tong Q Y. Semiconductor wafer bonding. Annu Rev Ma-
tions such as ultra-efficient circuits for handheld, mobile or re- ter Sci, 1998, 28, 215
mote applications, self-sensing and self-tuning/self-configur- [20] Tong Q Y, Gösele U. Semiconductor wafer bonding: Recent devel-
ing circuits, and RGB (red, green, blue) micro-LED arrays with opments. Mater Chem Phys, 1994, 37, 101
control circuitry, etc. [21] Lasky J B, Stiffler S R, White F R, et al. Silicon-on-insulator (SOI) by
bonding and ETCH-back. 1985 Int Electron Devices Meet, 1985,
684
References [22] Plößl A. Wafer direct bonding: Tailoring adhesion between brittle
materials. Mater Sci Eng R, 1999, 25, 1
[1] Deleonibus S. Physical and technological limitations of nano
[23] Turner K T, Spearing S M. Modeling of direct wafer bonding: Ef-
CMOS devices to the end of the roadmap and beyond. Eur Phys J
fect of wafer bow and etch patterns. J Appl Phys, 2002, 92, 7658
Appl Phys, 2006, 36, 197
[24] Taniyama S, Wang Y H, Fujino M, et al. Room temperature wafer
[2] Ito T, Okazaki S. Pushing the limits of lithography. Nature, 2000,
bonding using surface activated bonding method. 2008 IEEE 9th
406, 1027
VLSI Packag Work Jpn, 2008, 141
[3] Wong H S P, Frank D J, Solomon P M, et al. Nanoscale CMOS. Proc
[25] Takagi H, Kikuchi K, Maeda R, et al. Surface activated bonding of sil-
IEEE, 1999, 87, 537
icon wafers at room temperature. Appl Phys Lett, 1996, 68, 2222
[4] Kim D H, del Alamo J A. 30 nm E-mode InAs PHEMTs for THz and fu-
[26] Howlader M M R, Watanabe T, Suga T. Investigation of the bond-
ture logic applications. 2008 IEEE International Electron Devices ing strength and interface current of p-Si/n-GaAs wafers bonded
Meeting, 2008, 1 by surface activated bonding at room temperature. J Vac Sci Tech-
[5] Passlack M, Zurcher P, Rajagopalan K, et al. High mobility III–V MOS- nol B, 2001, 19, 2114
FETs for RF and digital applications. 2007 IEEE Int Electron [27] Chung T R, Yang L, Hosoda N, et al. Room temperature GaAs–Si
Devices Meet, 2007, 621 and InP–Si wafer direct bonding by the surface activated bond-
[6] Kim R H, Kim D H, Xiao J L, et al. Waterproof AlInGaP optoelectron- ing method. Nucl Instrum Methods Phys Res B, 1997, 121, 203
ics on stretchable substrates with applications in biomedicine [28] Takagi H, Utsumi J, Takahashi M, et al. Room-temperature bond-
and robotics. Nat Mater, 2010, 9, 929 ing of oxide wafers by Ar-beam surface activation. ECS Trans,
[7] Ko H, Takei K, Kapadia R, et al. Ultrathin compound semiconduct- 2019, 16, 531
or on insulator layers for high-performance nanoscale transistors. [29] Essig S, Moutanabbir O, Wekkeli A, et al. Fast atom beam-activ-
Nature, 2010, 468, 286 ated n-Si/n-GaAs wafer bonding with high interfacial transpar-
[8] Yoon J, Jo S, Chun I S, et al. GaAs photovoltaics and optoelectron- ency and electrical conductivity. J Appl Phys, 2013, 113, 203512
ics using releasable multilayer epitaxial assemblies. Nature, 2010, [30] Hinterreiter A P, Rebhan B, Flötgen C, et al. Surface pretreated
465, 329 low-temperature aluminum-aluminum wafer bonding. Microsyst
[9] Lin J J, You T G, Jin T T, et al. Wafer-scale heterogeneous integra- Technol, 2018, 24, 773
tion InP on trenched Si with a bubble-free interface. APL Mater, [31] Suga T, He R, Vakanas G, et al. Direct Cu to Cu bonding and other
2020, 8, 051110 alternative bonding techniques in 3D packaging. In: 3D Microelec-
[10] Lin J J, You T G, Wang M, et al. Efficient ion-slicing of InP thin film tronic Packaging. Cham: Springer International Publishing, 2017,
for Si-based hetero-integration. Nanotechnology, 2018, 29, 129
504002 [32] Malik N, Schjølberg-Henriksen K, Poppe E, et al. AlAl thermocom-
[11] Lee K H, Bao S, Fitzgerald E, et al. Integration of III –V materials pression bonding for wafer-level MEMS sealing. Sens Actuators A,
and Si-CMOS through double layer transfer process. 2014 4th 2014, 211, 115
IEEE Int Work Low Temp Bond 3D Integr LTB-3D, 2014, 32 [33] Tsau C H, Spearing S M, Schmidt M A. Fabrication of wafer-level
[12] Lee K H, Bao S Y, Kohen D, et al. Monolithic integration of III –V thermocompression bonds. J Microelectromechan Syst, 2002, 11,
HEMT and Si-CMOS through TSV-less 3D wafer stacking. 2015 641
IEEE 65th Electronic Components and Technology Conference (EC- [34] Xu D H, Jing E R, Xiong B, et al. Wafer-level vacuum packaging of
TC), 2015, 560 micromachined thermoelectric IR sensors. IEEE Trans Adv Packag,
[13] Lee K H, Bao S Y, Lee K E K, et al. Integration of 200 mm Si-CMOS 2010, 33, 904
and III–V materials through wafer bonding. 2017 5th Internation- [35] Fan J, Lim D F, Tan C S. Effects of surface treatment on the bond-
al Workshop on Low Temperature Bonding for 3D Integration ing quality of wafer-level Cu-to-Cu thermo-compression bond-
(LTB-3D), 2017, 30 ing for 3D integration. J Micromech Microeng, 2013, 23, 045025
[14] Yan Y Q, Huang K, Zhou H Y, et al. Wafer-scale fabrication of 42° ro- [36] Chen K N, Fan A, Reif R. Microstructure examination of copper
tated Y-cut LiTaO3-on-insulator (LTOI) substrate for a SAW resonat- wafer bonding. J Electron Mater, 2001, 30, 331
or. ACS Appl Electron Mater, 2019, 1, 1660 [37] Gao K, Zhang Q Y, Su W G, et al. Patterned Al–Ge wafer bonding
[15] Huang K, Jia Q, You T G, et al. Investigation on thermodynamics for reducing in-process side leakage of eutectic. 2018 IEEE 13th An-
of ion-slicing of GaN and heterogeneously integrating high-qual- nual International Conference on Nano/Micro Engineered and Mo-
ity GaN films on CMOS compatible Si(100) substrates. Sci Rep, lecular Systems (NEMS), 2018, 332
2017, 7, 15017. [38] Tang Y S, Chen H C, Kho Y T, et al. Investigation and optimization
[16] Yi A L, Zheng Y, Huang H, et al. Wafer-scale 4H-silicon carbide-on- of ultrathin buffer layers used in Cu/Sn eutectic bonding. IEEE
insulator (4H-SiCOI) platform for nonlinear integrated optical Trans Compon Packag Manuf Technol, 2018, 8, 1225
devices. Opt Mater, 2020, 107, 109990 [39] Wolffenbuttel R F. Low-temperature intermediate Au-Si wafer
[17] Lei D, Lee K H, Bao S Y, et al. GeSn-on-insulator substrate formed bonding; eutectic or silicide bond. Sens Actuators A, 1997, 62,
by direct wafer bonding. Appl Phys Lett, 2016, 109, 022106 680
[18] Xu W H, Wang Y, You T G, et al. First demonstration of waferscale [40] Cheng Y T, Lin L, Najafi K. Localized silicon fusion and eutectic
heterogeneous integration of Ga2O3 MOSFETs on SiC and Si sub- bonding for MEMS fabrication and packaging. J Microelec-
strates by ion-cutting process. 2019 IEEE International Electron tromechan Syst, 2000, 9, 3
[41] Quero J M, Perdigones F, Aracil C. Microfabrication technologies al film in a germanium-on-insulator wafer by annealing in oxy-
used for creating smart devices for industrial applications. In: gen ambient. APL Mater, 2015, 3, 016102
Smart Sensors and MEMs. Amsterdam: Elsevier, 2018, 291 [65] Lee K H, Tan C S, Wang Y, et al. Monolithic integration of Si-CMOS
[42] Li D L, Shang Z G, She Y, et al. Investigation of Au/Si eutectic and III–V-on-Si through direct wafer bonding process. IEEE J Elec-
wafer bonding for MEMS accelerometers. Micromachines, 2017, tron Devices Soc, 2018, 6, 571
8, 158 [66] Lee K H, Zhang L, Wang B, et al. Integration of Si-CMOS and III–V
[43] Mescheder U M, Alavi M, Hiltmann K, et al. Local laser bonding for materials through multi-wafer stacking. 2017 IEEE SOI-3D-Sub-
low temperature budget. Sens Actuators A, 2002, 97/98, 422 threshold Microelectronics Technology Unified Conference (S3S),
[44] Knechtel R. Glass frit bonding: An universal technology for wafer 2017, 1
level encapsulation and packaging. Microsyst Technol, 2005, 12, [67] Lee K H, Wang Y, Zhang L, et al. GaN LED on quartz substrate
63 through wafer bonding and layer transfer processes. ECS Trans,
[45] Wu G Q, Xu D H, Xiong B, et al. Wafer-level vacuum packaging for 2018, 86, 31
MEMS resonators using glass frit bonding. J Microelectromechan [68] Lee K H, Zhang L, Wang Y, et al. High bonding yield and brighter in-
Syst, 2012, 21, 1484 tegrated GaN LED and Si-CMOS. 2019 6th International Work-
[46] Tian R, Cao F, Li Y, et al. Application of laser-assisted glass frit bond- shop on Low Temperature Bonding for 3D Integration (LTB-3D),
ing encapsulation in all inorganic quantum dot light emitting 2019, 33
devices. Mol Cryst Liq Cryst, 2018, 676, 59 [69] Lee K H, Bao S Y, Zhang L, et al. Integration of GaAs, GaN, and Si-
[47] Niklaus F, Enoksson P, Kalvesten E, et al. Low-temperature full CMOS on a common 200 mm Si substrate through multilayer trans-
wafer adhesive bonding. J Micromechan Microeng, 2001, 11, 100 fer process. Appl Phys Express, 2016, 9, 086501
[48] Dragoi V, Glinsner T, Mittendorfer G, et al. Adhesive wafer bond-
ing for MEMS applications. Proc SPIE 5116, Smart Sensors, Actuat- Shuyu Bao received her B.Eng. (Hons.) degree
ors, and MEMS, 2003, 5116, 160 in 2013 in Materials Engineering and Ph.D de-
[49] Bleiker S J, Dubois V, Schröder S, et al. Adhesive wafer bonding gree in 2018 in Electrical & Electronic Engineer-
with ultra-thin intermediate polymer layers. Sens Actuators A, ing from Nanyang Technological University
2017, 260, 16 (NTU), Singapore. Currently, she is a senior
[50] Niklaus F, Stemme G, Lu J Q, et al. Adhesive wafer bonding. J Ap- postdoctoral researcher in Singapore-MIT alli-
pl Phys, 2006, 99, 031101 ance for research and technology (SMART).
[51] Niklaus F, Enoksson P, Kälvesten E, et al. A method to maintain Her research interests include low temperat-
wafer alignment precision during adhesive wafer bonding. Sens ure wafer bonding and development of multi-
Actuators A, 2003, 107, 273 color LED and CMOS-driven LED through het-
[52] Niklaus F, Kumar R J, McMahon J J, et al. Adhesive wafer bonding erogeneous material integration.
using partially cured benzocyclobutene for three-dimensional in-
tegration. J Electrochem Soc, 2006, 153, G291
[53] Pomerantz D I. Anodic bonding. Google Patents, 1968 Yue Wang received her B.Eng. (Hons.) degree
[54] Henmi H, Shoji S, Shoji Y, et al. Vacuum packaging for micro- in 2010 and Ph.D degree in 2016 in Electrical
sensors by glass-silicon anodic bonding. Sens Actuators A, 1994, & Computer Engineering from National Uni-
43, 243 versity of Singapore. Currently, she is a re-
[55] Hanneborg A, Nese M, Ohlckers P. Silicon-to-silicon anodic bond- search scientist in Singapore-MIT alliance for re-
ing with a borosilicate glass layer. J Micromech Microeng, 1991, search and technology (SMART). Her research
1, 139 interest is the monolithic integration of III-V
[56] Lee T M H, Hsing I M, Liaw C Y N. An improved anodic bonding pro- electronic and optoelectronic devices on silic-
cess using pulsed voltage technique. J Microelectromechan Syst, on.
2000, 9, 469
[57] Schmidt M A. Wafer-to-wafer bonding for microstructure forma-
tion. Proc IEEE, 1998, 86, 1575 Khaw Lina received her B.Eng. (Hons.) degree
[58] Tong Q Y, Gösele U. A model of low-temperature wafer bonding in 2010 in Materials Engineering from Nan-
and its applications. J Electrochem Soc, 2019, 143, 1773 yang Technological University (NTU), Singa-
[59] Lee K H, Bao S Y, Wang Y, et al. Suppression of interfacial voids pore. Her research interest is on wafer bond-
formation during silane (SiH4)-based silicon oxide bonding with a ing for integrated LED and HEMT/Si CMOS plat-
thin silicon nitride capping layer. J Appl Phys, 2018, 123, 015302 form.
[60] Bao S, Lee K H, Chong G Y, et al. AlN–AlN layer bonding and its
thermal characteristics. ECS J Solid State Sci Technol, 2015, 4,
P200
[61] Bao S Y, Lee K H, Wang C, et al. Germanium-on-insulator virtual
substrate for InGaP epitaxy. Mater Sci Semicond Process, 2017,
58, 15 Li Zhang received his B.Eng. (Hons.) and B.A. de-
grees in electrical engineering and econom-
[62] Lee K H, Bao S Y, Chong G Y, et al. Fabrication and characteriza-
ics from National University of Singapore in
tion of germanium-on-insulator through epitaxy, bonding, and lay-
2010 and Ph.D. degree from NUS graduate
er transfer. J Appl Phys, 2014, 116, 103506
school for integrative science and engineer-
[63] Lee K H, Bao S Y, Chong G Y, et al. Fabrication of germanium-on-in-
ing from National University of Singapore in
sulator (GOI) with improved threading dislocation density (TDD)
2016. His research interest is GaN-on-Si epi-
via buffer-less epitaxy and bonding. 2014 7th Int Silicon-Ger Techn- taxy and integrated GaN LED/Si CMOS plat-
ol Device Meet ISTDM, 2014, 51 form.
[64] Lee K H, Bao S Y, Chong G Y, et al. Defects reduction of Ge epitaxi-
Bing Wang is Assoc. Professor in the School of Jurgen Michel is a Senior Research Scientist in
Electronics and Information Technology at the the Microphotonics Center and a Senior Lec-
Sun Yat-Sen University, China. He received his turer in the Department of Materials Science
B. S. degree in Electronic Science and Techno- and Engineering at the Massachusetts Insti-
logy from Zhengzhou University, Zhengzhou, tute of Technology. He leads research
China, in 2005, M.S. degree in Optical Engineer- projects in silicon-based photonic materials
ing from Huazhong University of Science and and devices as well as advanced solar cell
Technology, Wuhan, China, in 2007, and Ph.D. designs. His main focus is currently on on-
degree in Communication and Information Sys- chip WDM devices, Ge-based high perform-
tems, from Peking University, Beijing, China, ance detectors and modulators, and Ge-based
in 2012. His research interests cover optoelec- lasers with the goal to implement active
tronic devices, integrated photonics, and optic- photonics devices in CMOS based chips.
al interconnect systems.
Eugene Fitzgerald is the Merton C. Flemings
Wardhana Aji Sasangka received his Ph.D in ad- SMA Professor of Materials Engineering at the
vanced materials science for micro- and nano- Massachusetts Institute of Technology. He is
system from Nanyang Technological Uni- Chief Executive Officer and Director of the
versity in 2012. He has broad research in- Singapore–MIT alliance for research and techno-
terests such as GaN reliability, nanowires logy (SMART), Singapore. He is also the Lead
growth, thin film interdiffusion, and crystal de- Principal Investigator (PI) of SMART Low En-
fect characterization. He is an active member ergy Electronic Systems (LEES) Interdisciplin-
of organizing committee in International Sym- ary Research Group (IRG).
posium on the Physical and Failure Analysis of
Integrated Circuits (IPFA).
Chuan Seng Tan is a Professor with the School
of Electrical and Electronic Engineering, Nan-
Kenneth Eng Kian Lee is the Senior Scientific yang Technological University, Singapore. He
Director of the Low Energy Electronic Sys- received the Ph.D. degree in electrical engineer-
tems (LEES) center of the Singapore-MIT Alli- ing from Massachusetts Institute of Techno-
ance for Research and Technology (SMART). logy, Cambridge, in 2006. His research in-
He drives the core program effort to create a terests are semiconductor process techno-
hybrid III-V + CMOS integrated circuit plat- logy and device physics. Currently he is work-
form based on foundry-standard CMOS pro- ing on process technology of three-dimension-
cess flows, to enable new integrated electron- al integrated circuits (3-D ICs), as well as engin-
ic and photonic systems. He had prior stints in eered substrate (Si/Ge/Sn) for group-IV photon-
Singapore’s Ministry of Defence, Temasek ics.
Laboratories at NTU, and DSO National Laborat-
ories. He received his BS and MS degrees from
UIUC in 1998 and 1999, respectively, and his Kwang Hong Lee received the B.Eng. (Hons.)
PhD from MIT in 2009, all in Electrical Engineer- and Ph.D. degrees in materials science and en-
ing. gineering from Nanyang Technological Uni-
versity, Singapore, in 2006 and 2011, respect-
ively. He was a Principal Research Scientist
Soo Jin Chua is a Professor in the Depart with the Singapore–MIT Alliance for Research
ment of Electrical Engineering, National Uni- and Technology, working on creating novel
versity of Singapore, Principal Scientist in the In- combinations of materials with silicon for use
stitute of Materials Research and Engineering in monolithic processes.
(IMRE) and Principal Investigator in
SMART. His research area is in Semiconductor
Optoelectronics.

A Review of Silicon-Based Wafer Bonding Processes, An Approach To Realize The Monolithic Integration of Si-CMOS and III-V-on-Si Wafers

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A Review of Silicon-Based Wafer Bonding Processes, An Approach To Realize The Monolithic Integration of Si-CMOS and III-V-on-Si Wafers

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Journal of Semiconductors

(2021) 42, 023106

A review of silicon-based wafer bonding processes, an approach

(a) (b) Cathode

ally conducting. The electrostatic voltage in the range of (a) (b)

(a) (b) (c)

(a) Ar plasma activation

Sputtering Activation Bonding & annealing

100 source in a silicon photonic system. In addition, since Si is the

Bond Si donor wafer Etch by

Fig. 11. (Color online) Schematics of Ge-OI fabrication process.

Before annealing After annealing Ge-OI GaAs-OI GaN-OI

200 nm 200 nm GaAs: 310 nm GaN: 300 nm

removed by etching and subsequent O2 annealing, therefore

Ge−Ge CMOS devices with III–V/Si integration on common Si wafers

Handle wafer release Thermally oxidized Si

(a) Patterned SOI (b)

(a) Botttem Si substrate (b)

(a) 1st bonding (b)

Removal the botttem

Si handle wafer Si handle wafer

SiO2 (BOX) SiO2 (BOX)

ide-on-BOX method. By completely removing the BOX layer ing method.

(a) 1st bonding

(a) 1st bonding

SiO2 (BOX) SiO2 Si handle wafer

CMP on BOX PECVD SiO2 BOX etching (a) (b)

the microscale level with the PECVD-oxide-only method has

(a) Bottom Si substrate (b)

Si handle removal 2nd bonding

III−As/P HEMT or LED PECVD SiO2 Si handle wafer

III−As/P HEMT or LED

Si (001) wafer (d)

(a) Before bonding (b) After bonding with Si-CMOS

Qz (nm) in [001] direction

Qz (nm) in [001] direction

Bonding dielectrics 7.00 n-AlGaInP 7.00

(c) Before bonding (d) After bonding with Si-CMOS

Qz (nm) in [001] direction

Si (001) donor 2 Removal of Si (111)

III−N HEMT or LED Si (001) donor 2

Si (111) donor III−N HEMT or LED

Removal of Si (111) donor 2 Si (001) donor 2

PECVD SiO2 III−N HEMT or LED III−N HEMT or LED

ition, to address the pin-holes and outgassing issues. Then,

(a) (b) (c)

GaN with buﬀer (4 μm) GaN with buﬀer (4 μm)

on the quartz substrate.

3rd bonding 2nd bonding

PEVCD SiO2 PEVCD SiO2

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