STM32 U5 Axxx

STM32U5Axxx
Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,

240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI®DSI, crypto
Datasheet - production data
Features
Includes ST state-of-the-art patented
technology LQFP64 (10 x 10 mm)
LQFP100 (14 x 14 mm)
WLCSP150
(5.38 x 5.47 mm)
UFBGA132 (7 x 7 mm)
TFBGA169 (7 x 7 mm)
Ultra-low-power with FlexPowerControl

LQFP144 (20 x 20 mm) WLCSP208 TFBGA216 (13 x 13 mm)
(5.38 x 5.47 mm)
• 1.71 V to 3.6 V power supply • 655 CoreMark® (4.09 CoreMark®/MHz)

• - 40 °C to + 85/125 °C temperature range • 369 ULPMark™-CP
• Low-power background autonomous mode • 89 ULPMark™-PP
(LPBAM): autonomous peripherals with DMA,
functional down to Stop 2 mode • 47.2 ULPMark™-CM
• VBAT mode: supply for RTC, 32 x 32-bit backup • 120000 SecureMark™-TLS

registers and 2-Kbyte backup SRAM Memories
• 150 nA Shutdown mode (24 wake-up pins) • 4-Mbyte flash memory with ECC, 2 banks read-
• 195 nA Standby mode (24 wake-up pins) while-write, including 512 Kbytes with
• 480 nA Standby mode with RTC 100 kcycles
• 2 μA Stop 3 mode with 40-Kbyte SRAM • With SRAM3 ECC off: 2514-Kbyte RAM
including 66 Kbytes with ECC
• 8.2 μA Stop 3 mode with 2.5-Mbyte SRAM
• With SRAM3 ECC on: 2450-Kbyte RAM
• 4.65 µA Stop 2 mode with 40-Kbyte SRAM including 322 Kbytes with ECC
• 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM • External memory interface supporting SRAM,
• 18.5 μA/MHz Run mode at 3.3 V PSRAM, NOR, NAND, and FRAM memories
Core • 2 Octo-SPI memory interfaces
• Arm® 32-bit Cortex®-M33 CPU with • 16-bit HSPI memory interface up to 160 MHz
TrustZone®, MPU, DSP, and FPU
Rich graphic features
ART Accelerator
• Neo-Chrom GPU (GPU2D) accelerating any
• 32-Kbyte ICACHE allowing 0-wait-state angle rotation, scaling, and perspective correct
execution from flash and external memories: texture mapping
frequency up to 160 MHz, 240 DMIPS • 16-Kbyte DCACHE2
• 16-Kbyte DCACHE1 for external memories • Chrom-ART Accelerator (DMA2D) for smooth
motion and transparency effects
Power management
• Chrom-GRC (GFXMMU) allowing up to 20 %
• Embedded regulator (LDO) and SMPS of graphic resources optimization
step-down converter supporting switch
on-the-fly and voltage scaling • MIPI® DSI host controller with two DSI lanes
running at up to 500 Mbit/s each
Benchmarks • LCD-TFT controller (LTDC)
• 1.5 DMIPS/MHz (Drystone 2.1) • Digital camera interface
July 2023 DS13543 Rev 2 1/390

This is information on a product in full production. www.st.com
STM32U5Axxx
General-purpose input/outputs basic, 4 low-power 16-bit (available in Stop

mode), 2 SysTick timers, and 2 watchdogs
• Up to 156 fast I/Os with interrupt capability
most 5V-tolerant and up to 14 I/Os with • RTC with hardware calendar, alarms, and
independent supply down to 1.08 V calibration
Clock management Up to 25 communication peripherals

• 4 to 50 MHz crystal oscillator • 1 USB Type-C®/USB power delivery controller
• 32 kHz crystal oscillator for RTC (LSE) • 1 USB OTG high-speed with embedded PHY
• Internal 16 MHz factory-trimmed RC (± 1 %) • 2 SAIs (serial audio interface)
• Internal low-power 32 kHz RC (± 5 %) • 6 I2C FM+(1 Mbit/s), SMBus/PMBus™
• 2 internal multispeed 100 kHz to 48 MHz • 7 USARTs (ISO 7816, LIN, IrDA, modem)
oscillators, including one autotrimmed by LSE • 3 SPIs (6x SPIs with OCTOSPI/HSPI)
(better than ±0.25 % accuracy)
• 1 CAN FD controller
• Internal 48 MHz
• 2 SDMMC interfaces
• 5 PLLs for system clock, USB, audio, ADC, DSI
• 1 multifunction digital filter (6 filters) + 1 audio
Security and cryptography digital filter with sound-activity detection
• SESIP3 and PSA Level 3 Certified Assurance • Parallel synchronous slave interface
Target Mathematical coprocessor
• Arm® TrustZone® and securable I/Os,
• CORDIC for trigonometric functions
memories, and peripherals
acceleration
• Flexible life cycle scheme with RDP and
• FMAC (filter mathematical accelerator)
password-protected debug
• Root of trust thanks to unique boot entry and Rich analog peripherals (independent
secure hide-protection area (HDP) supply)
• Secure firmware installation (SFI) thanks to • 2 14-bit ADC 2.5-Msps with hardware
embedded root secure services (RSS) oversampling
• Secure data storage with hardware unique key • 1 12-bit ADC 2.5-Msps, with hardware
(HUK) oversampling, autonomous in Stop 2 mode
• Secure firmware upgrade support with TF-M • 12-bit DAC (2 channels), low-power sample,
and hold, autonomous in Stop 2 mode
• 2 AES coprocessors including one with DPA
resistance • 2 operational amplifiers with built-in PGA
• Public key accelerator, DPA resistant • 2 ultra-low-power comparators
• On-the-fly decryption of Octo-SPI external
memories
ECOPACK2 compliant packages
• HASH hardware accelerator
Table 1. Device summary
• True random number generator, NIST
SP800-90B compliant Reference Part numbers
• 96-bit unique ID STM32U5A5AJ, STM32U5A5QI,

STM32U5A5QJ, STM32U5A5RJ,
• 512-byte OTP (one-time programmable)
STM32U5Axxx STM32U5A5VJ, STM32U5A5ZJ,
• Active tampers STM32U5A9BJ, STM32U5A9NJ,
STM32U5A9VJ, STM32U5A9ZJ
Up to 17 timers, 2 watchdogs and RTC
• 19 timers: 2 16-bit advanced motor-control,
4 32-bit, 3 16-bit general purpose, 2 16-bit
2/390 DS13543 Rev 2

STM32U5Axxx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Arm Cortex-M33 core with TrustZone and FPU . . . . . . . . . . . . . . . . . . . . 23
3.2 ART Accelerator (ICACHE and DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Data cache (DCACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1 Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.2 Additional flash memory protections when TrustZone activated . . . . . . 28
3.4.3 FLASH privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5 Embedded SRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.1 SRAMs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.5.2 SRAMs privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6 TrustZone security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6.1 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6.2 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 Global TrustZone controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.9.4 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.5 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.9.6 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.10 Peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.11 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.11.1 RCC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.12 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Contents STM32U5Axxx
3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.13.1 GPIOs TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.14 Low-power general-purpose inputs/outputs (LPGPIO) . . . . . . . . . . . . . . 52
3.14.1 LPGPIO TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.15 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.16 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . . . . 53
3.17 General purpose direct memory access controller (GPDMA) . . . . . . . . . 53
3.18 Low-power direct memory access controller (LPDMA) . . . . . . . . . . . . . . 55
3.19 Neo-Chrom GPU (GPU2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.20 Chrom-ART Accelerator controller (DMA2D) . . . . . . . . . . . . . . . . . . . . . . 58
3.21 Chrom-GRC (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.22 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.22.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 59
3.22.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 60
3.23 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 60
3.24 CORDIC co-processor (CORDIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.25 Filter math accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.26 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 61
3.26.1 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.26.2 FSMC TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.27 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.27.1 OCTOSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.28 OCTOSPI I/O manager (OCTOSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.29 Delay block (DLYB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.30 Hexadeca-SPI interface (HSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.30.1 HSPI TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.31 Analog-to-digital converters (ADC1, ADC2, and ADC4) . . . . . . . . . . . . . . 65
3.31.1 Analog-to-digital converters (ADC1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.31.2 Analog-to-digital converter 4 (ADC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.31.3 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.31.4 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.31.5 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.32 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.33 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4/390 DS13543 Rev 2

3.34 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.35 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.36 Multi-function digital filter (MDF) and audio digital filter (ADF) . . . . . . . . . 71
3.36.1 Multi-function digital filter (MDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.36.2 Audio digital filter (ADF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.37 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.38 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . 75
3.39 LCD-TFT display controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.40 DSI Host controller (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.41 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.42 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.43 Secure advanced encryption standard hardware accelerator (SAES)
and encryption standard hardware accelerator (AES) . . . . . . . . . . . . . . . 78
3.44 HASH hardware accelerator (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.45 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.46 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.47 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.47.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.47.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,
TIM16,TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.47.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.47.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4) . . . . . . . . . . . . 85
3.47.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.47.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.47.7 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.47.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.48 Real-time clock (RTC), tamper and backup registers . . . . . . . . . . . . . . . 86
3.48.1 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.48.2 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.49 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.50 Universal synchronous/asynchronous receiver transmitter (USART/UART)
and low-power universal asynchronous receiver transmitter (LPUART) . 89
3.50.1 Universal synchronous/asynchronous receiver transmitter
(USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.50.2 Low-power universal asynchronous receiver transmitter (LPUART) . . . 91
3.51 Serial peripheral interfaces (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DS13543 Rev 2 5/390

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3.52 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.53 Secure digital input/output and MultiMediaCards interface (SDMMC) . . . 95
3.54 Controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.55 USB on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.56 USB Type-C /USB Power Delivery controller (UCPD) . . . . . . . . . . . . . . . 98
3.57 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.57.1 Serial-wire/JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.57.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4 Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . 100

4.1 Pinout/ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . 189
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 190
5.3.4 SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
5.3.5 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.3.7 Wake-up time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
5.3.8 External clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 244
5.3.9 Internal clock timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
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5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

5.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
5.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
5.3.17 Extended interrupt and event controller input (EXTI) characteristics . . 273
5.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.3.19 14-bit analog-to-digital converter (ADC12) characteristics . . . . . . . . . 273
5.3.20 12-bit analog-to-digital converter (ADC4) characteristics . . . . . . . . . . 280
5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
5.3.22 VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
5.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
5.3.24 Digital-to-analog converter characteristics . . . . . . . . . . . . . . . . . . . . . . 287
5.3.25 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 290
5.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
5.3.27 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 294
5.3.28 Temperature and backup domain supply thresholds monitoring . . . . . 298
5.3.29 ADF/MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
5.3.30 DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
5.3.31 PSSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
5.3.32 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 305
5.3.33 MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
5.3.34 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
5.3.35 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
5.3.36 OCTOSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
5.3.37 HSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
5.3.38 SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics . . . . 338
5.3.39 Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
5.3.40 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
5.3.41 USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
5.3.42 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
5.3.43 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
5.3.44 OTG_HS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
5.3.45 UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
5.3.46 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 351
DS13543 Rev 2 7/390

8
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

6.1 LQFP64 package information (5W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
6.2 LQFP100 package information (1L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
6.3 UFBGA132 package information (A0G8) . . . . . . . . . . . . . . . . . . . . . . . . 362
6.4 LQFP144 package information (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
6.5 WLCSP150 package information (B0DX) . . . . . . . . . . . . . . . . . . . . . . . 370
6.6 TFBGA169 package information (B0MA) . . . . . . . . . . . . . . . . . . . . . . . . 373
6.7 WLCSP208 package information (B0DV) . . . . . . . . . . . . . . . . . . . . . . . 376
6.8 TFBGA216 package information (A0L2) . . . . . . . . . . . . . . . . . . . . . . . . 380
6.9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
6.9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
8/390 DS13543 Rev 2

STM32U5Axxx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32U5Axxx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Access status versus protection level and execution modes when TZEN = 0 . . . . . . . . . . 26
Table 4. Access status versus protection level and execution modes when TZEN = 1 . . . . . . . . . . 27
Table 5. Example of memory map security attribution versus SAU configuration regions . . . . . . . . 30
Table 6. Boot modes when TrustZone is disabled (TZEN = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Boot modes when TrustZone is enabled (TZEN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. STM32U5Axxx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 10. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 11. GPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 12. GPDMA1 autonomous mode and wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . 55
Table 13. LPDMA1 channels implementation and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 14. LPDMA1 autonomous mode and wake-up in low-power modes . . . . . . . . . . . . . . . . . . . . 57
Table 15. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 16. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 17. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 18. MDF features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 19. AES/SAES features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 20. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 21. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 22. USART, UART and LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 23. SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 24. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 25. SDMMC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 26. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 27. STM32U5Axxx pin/ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 28. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 29. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 30. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 31. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 32. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 33. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 34. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 35. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 36. SMPS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 37. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 38. Current consumption in Run mode on LDO, code with data processing
running from flash memory, ICACHE ON in 1-way, prefetch ON . . . . . . . . . . . . . . . . . . . 194
Table 39. Current consumption in Run mode on SMPS, code with data processing
running from flash memory, ICACHE ON in 1-way, prefetch ON . . . . . . . . . . . . . . . . . . . 195
running from flash memory, ICACHE ON in 1-way, prefetch ON, VDD = 3.0 V . . . . . . . . 196
Table 41. Typical current consumption in Run mode on LDO, with different codes
running from flash memory, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . . . . . . . . . . 197
Table 42. Typical current consumption in Run mode on SMPS, with different codes
running from flash memory, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . . . . . . . . . . 199
Table 43. Typical current consumption in Run mode on LDO, with different codes running
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List of tables STM32U5Axxx
from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . 200
Table 44. Typical current consumption in Run mode on SMPS, with different codes running
from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON. . . . . . . . . . . 201
Table 45. Current consumption in Sleep mode on LDO, flash memory in power down . . . . . . . . . . 202
Table 46. Current consumption in Sleep mode on SMPS, flash memory in power down. . . . . . . . . 203
Table 47. Current consumption in Sleep mode on SMPS,
flash memory in power down, VDD = 3.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 48. SRAM1/SRAM3/SRAM5 current consumption in Run/Sleep mode with LDO and SMPS 205
Table 49. Static power consumption of flash memory banks when supplied by LDO or SMPS . . . . 208
Table 50. Current consumption in Stop 0 mode on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 51. Current consumption in Stop 0 mode on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 55. SRAM static power consumption in Stop 2 when supplied by LDO . . . . . . . . . . . . . . . . . 216
Table 57. SRAM static power consumption in Stop 2 when supplied by SMPS. . . . . . . . . . . . . . . . 219
Table 59. SRAM static power consumption in Stop 3 when supplied by LDO . . . . . . . . . . . . . . . . . 223
Table 61. SRAM static power consumption in Stop 3 when supplied by SMPS. . . . . . . . . . . . . . . . 226
Table 62. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 63. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 64. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 65. Typical dynamic current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 66. Low-power mode wake-up timings on LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 67. Low-power mode wake-up timings on SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 68. Regulator mode transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 69. Wake-up time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 70. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 71. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 72. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 73. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 74. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Table 75. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 76. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Table 77. SHSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 78. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 79. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 80. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 81. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Table 82. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 83. EMI characteristics (for fHSE = 8 MHz, fHCLK = 160 MHz) . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 84. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 85. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 86. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 87. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 88. Output voltage characteristics (all I/Os except FT_t I/Os in VBAT mode,
and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 89. Output voltage characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os . . . . . . . . 266
Table 90. Output AC characteristics, HSLV OFF (all I/Os except FT_c,
FT_t in VBAT mode, and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
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STM32U5Axxx List of tables
Table 91. Output AC characteristics, HSLV ON (all I/Os except FT_c,

FT_t in VBAT mode, and FT_o I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Table 92. Output AC characteristics for FT_c I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 93. Output AC characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os . . . . . . . . . . . . 271
Table 94. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 95. EXTI input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 96. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 97. 14-bit ADC12 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 98. Maximum RAIN for 14-bit ADC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 99. 14-bit ADC12 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 100. 12-bit ADC4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 101. Maximum RAIN for 12-bit ADC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 102. 12-bit ADC4 accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 103. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 104. VCORE monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 105. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 106. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 107. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 108. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 109. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 110. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 111. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 112. ADF characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 113. MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 114. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 115. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 116. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 117. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Table 118. MIPI D-PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 119. MIPI D-PHY AC characteristics LP mode and HS/LP transitions . . . . . . . . . . . . . . . . . . . 308
Table 120. DSI-PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 121. DSI current consumption characteristics on VDDDSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 122. DSI current consumption characteristics on VDD11DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Table 123. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 124. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 125. WWDG min/max timeout value at 160 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 126. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 314
Table 127. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 314
Table 128. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 315
Table 129. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 316
Table 130. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 131. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 317
Table 132. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 133. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 319
Table 134. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 135. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Table 136. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 137. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Table 138. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 139. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 140. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Table 141. OCTOSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
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Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . 329

Table 143. HSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 144. HSPI characteristics in DTR mode (no DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 145. HSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . . . . . 334
Table 146. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Table 147. e•MMC characteristics (VDD = 1.71 V to 1.9 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Table 148. Delay block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Table 149. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Table 150. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Table 151. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Table 152. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 153. OTG_HS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 154. OTG_HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 155. OTG_HS PHY BCD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 156. OTG_HS current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Table 157. UCPD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Table 158. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Table 159. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Table 160. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Table 161. LQFP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Table 162. UFBGA132 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Table 163. UFBGA132 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 363
Table 164. LQFP144 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Table 165. WLCSP150 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Table 166. WLCSP150 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Table 167. TFBGA169 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Table 168. TFBGA169 - Example of PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . 375
Table 169. WLCSP208 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Table 170. WLCSP208 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Table 171. TFBGA216 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Table 172. TFBGA216 - Example of PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . 383
Table 173. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Table 174. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
12/390 DS13543 Rev 2

STM32U5Axxx List of figures
List of figures
Figure 1. STM32U5Axxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 2. STM32U5AxxxxxQ power supply overview (with SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 3. STM32U5Axxx power supply overview (without SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 4. Power-up /down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 5. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 6. VREFBUF block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 7. LQFP64_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 8. LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 9. LQFP100_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 10. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 11. UFBGA132_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 12. UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 13. LQFP144_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 14. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 15. WLCSP150_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 16. WLCSP150_DSI_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 17. TFBGA169_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 18. TFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 19. WLCSP208_DSI_SMPS ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 20. TFBGA216_DSI_SMPS pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 21. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 22. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 23. STM32U5Axxx power supply scheme (without SMPS) . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 24. STM32U5AxxxxxQ power supply scheme (with SMPS). . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 25. Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 26. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 27. AC timing diagram for high-speed external clock source (digital mode). . . . . . . . . . . . . . 245
Figure 28. AC timing diagram for high-speed external clock source (analog mode) . . . . . . . . . . . . . 246
Figure 29. AC timing diagram for low-speed external square clock source . . . . . . . . . . . . . . . . . . . . 246
Figure 30. AC timing diagram for low-speed external sinusoidal clock source . . . . . . . . . . . . . . . . . 247
Figure 31. Typical application with a 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 32. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 33. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 34. I/O input characteristics (all I/Os except BOOT0 and FT_c). . . . . . . . . . . . . . . . . . . . . . . 264
Figure 35. Output AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 36. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 37. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 38. Typical connection diagram when using the ADC
with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 39. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 40. VREFBUF_OUT versus temperature (VRS = 000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 44. OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ . . . . . . . . . . . . . . . . . . . . 297
Figure 45. OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ . . . . . . . . . . . . . . . . . . 298
Figure 46. ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 47. MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
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Figure 48. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Figure 49. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 50. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Figure 51. LTDC horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 52. LTDC vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 53. MIPI D-PHY HS/LP clock lane transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 54. MIPI D-PHY HS/LP data lane transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 313
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 315
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 60. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 63. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 64. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 65. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 326
Figure 66. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 326
Figure 67. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 68. OCTOSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 69. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 70. OCTOSPI HyperBus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 71. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 72. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 73. HSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 74. HSPI timing diagram - DTR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 75. HSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 76. HSPI HyperBus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 77. HSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 78. SD high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 80. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 81. USART timing diagram in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 82. USART timing diagram in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 83. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 84. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 85. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 86. SAI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 87. SAI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 88. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 89. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Figure 90. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 91. LQFP64 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 92. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 93. LQFP100 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 94. LQFP100 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 95. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 96. UFBGA132 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Figure 97. UFBGA132 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Figure 98. UFBGA132 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
Figure 99. LQFP144 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
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STM32U5Axxx List of figures
Figure 100. LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Figure 101. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Figure 102. WLCSP150 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Figure 103. WLCSP150 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 104. WLCSP150 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 105. TFBGA169 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 106. TFBGA169 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
Figure 107. TFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 108. WLCSP208 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Figure 109. WLCSP208 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Figure 110. WLCSP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 111. TFBGA216 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 112. TFBGA216 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Figure 113. TFBGA216 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
DS13543 Rev 2 15/390

15
Introduction STM32U5Axxx
1 Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32U5Axxx microcontrollers.
For information on the Arm®(a) Cortex®-M33 core, refer to the Cortex®-M33
Technical Reference Manual, available from the www.arm.com website.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32U59xxx and STM32U5Axxx errata sheet (ES0553).
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
16/390 DS13543 Rev 2

STM32U5Axxx Description
2 Description
The STM32U5Axxx devices belong to an ultra-low-power microcontrollers family

(STM32U5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
The Cortex®-M33 core features a single-precision FPU (floating-point unit), that supports all
the Arm® single-precision data-processing instructions and all the data types.
The Cortex®-M33 core also implements a full set of DSP (digital signal processing)
instructions and a MPU (memory protection unit) that enhances the application security.
The devices embed high-speed memories (4 Mbytes of flash memory and 2.5 Mbytes of
SRAM), a FSMC (flexible external memory controller) for static memories (for devices with
packages of 100 pins and more), two Octo-SPI and one Hexadeca-SPI memory interfaces
(at least one Quad-SPI available on all packages) and an extensive range of enhanced I/Os
and peripherals connected to three APB buses, three AHB buses and a 32-bit multi-AHB
bus matrix.
The devices offer security foundation compliant with the TBSA (trusted-based security
architecture) requirements from Arm®. It embeds the necessary security features to
implement a secure boot, secure data storage and secure firmware update. Besides these
capabilities, the devices incorporate a secure firmware installation feature, that allows the
customer to secure the provisioning of the code during its production. A flexible life cycle is
managed thanks to multiple levels of readout protection and debug unlock with password.
Firmware hardware isolation is supported thanks to securable peripherals, memories and
I/Os, and privilege configuration of peripherals and memories.
The devices feature several protection mechanisms for embedded flash memory and
SRAM: readout protection, write protection, secure and hide protection areas.
The devices embed several peripherals reinforcing security: a fast AES coprocessor,
a secure AES coprocessor with DPA resistance and hardware unique key that can be
shared by hardware with fast AES, a PKA (public key accelerator) with DPA resistance,
an on-the-fly decryption engine for Octo-SPI external memories, a HASH hardware
accelerator, and a true random number generator.
The devices offer active tamper detection and protection against transient and
environmental perturbation attacks, thanks to several internal monitoring generating secret
data erase in case of attack. This helps to fit the PCI requirements for point of sales
applications.
The devices offer two fast 14-bit ADCs (2.5 Msps), one 12-bit ADC (2.5 Msps), two
comparators, two operational amplifiers, two DAC channels, an internal voltage reference
buffer, a low-power RTC, four 32-bit general-purpose timers, two 16-bit PWM timers
dedicated to motor control, three 16-bit general-purpose timers, two 16-bit basic timers and
four 16-bit low-power timers.
The devices offer a rich set of graphic features: Neo-Chrom GPU (GPU2D) for fast texture
mapping, scaling and rotation, Chrom-ART (DMA2D) for smooth motion and transparency
effects, Chrom-GRC (GFXMMU) for memory optimization, MIPI® DSI Host controller with
two DSI lanes running at up to 500 Mbit/s each, and LCD-TFT controller (LTDC).
The devices support a MDF (multi-function digital filter) with six filters dedicated to the
connection of external sigma-delta modulators. Another low-power digital filter dedicated to
audio signals is embedded (ADF), with one filter supporting sound-activity detection.
DS13543 Rev 2 17/390

22
Description STM32U5Axxx
The devices embed mathematical accelerators (a trigonometric functions accelerator plus a

filter mathematical accelerator). In addition, up to 22 capacitive sensing channels are
available.
The devices also feature standard and advanced communication interfaces such as: six
I2Cs, three SPIs, four USARTs, two UARTs and one low-power UART, two SAIs, one DCMI
(digital camera interface), two SDMMCs, one FDCAN, one USB OTG high-speed, one
USB Type-C™/USB Power Delivery controller, and one generic synchronous 8-/16-bit PSSI
(parallel data input/output slave interface).
The devices operate in the –40 to +85 °C (+ 105 °C junction) and –40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V power supply.
A comprehensive set of power-saving modes allow the design of low-power applications.
Many peripherals (including communication, analog, timers and audio peripherals) can be
functional and autonomous down to Stop mode with direct memory access, thanks to
LPBAM support (low-power background autonomous mode).
Some independent power supplies are supported like an analog independent supply input
for ADC, DACs, OPAMPs and comparators, a 3.3 V dedicated supply input for USB and
up to 14 I/Os, that can be supplied independently down to 1.08 V. A VBAT input is available
for connecting a backup battery in order to preserve the RTC functionality and to backup
32 32-bit registers and 2-Kbyte SRAM.
The devices offer ten packages from 64 to 216 pins.
Table 2. STM32U5Axxx features and peripheral counts

STM32U5A5QJ/II
STM32U5A5AJH
STM32U5A9NJH
STM32U5A9BJY
STM32U5A5RJT
STM32U5A5VJT
STM32U5A9VJT
STM32U5A5ZJY
STM32U5A9ZJY
STM32U5A5ZJT
STM32U5A9ZJT
Peripherals
Flash memory
4
(Mbytes)
System
2512(768+64+832+16+832)
(Kbytes)
SRAM
Backup
2048 backup SRAM + 128 backup registers
(bytes)
External memory
controller for static No Yes(1)
memories (FSMC)
OCTOSPI 2(2) 2
HSPI No Yes
18/390 DS13543 Rev 2

Table 2. STM32U5Axxx features and peripheral counts (continued)
STM32U5A5QJ/II
STM32U5A5AJH
STM32U5A9NJH
STM32U5A9BJY
STM32U5A5RJT
STM32U5A5ZJY
STM32U5A9ZJY
STM32U5A5VJT
STM32U5A9VJT
STM32U5A5ZJT
STM32U5A9ZJT
Peripherals
Neo-Chrom
No Yes No Yes No Yes No Yes
(GPU2D)
Graphic accelerators
Chrom-GRC
No Yes No Yes No Yes No Yes
(GFXMMU)
Chrom-ART
Yes
(DMA2D)
DSI No Yes No Yes
LTDC No Yes No Yes No Yes No Yes
Adv. control 2 (16 bits)
Gen. purpose 4 (32 bits) and 3 (16 bits)
Basic 2 (16 bits)
Timers
Low power 4 (16 bits)

SysTick timer 2
Watchdog
timers (indep., 2
window)
SPI 3
I2C 6
USART 4
UART 2
Communication interfaces
LPUART 1
SAI 1 2
FDCAN 1
OTG_HS Yes
UCPD Yes
SDMMC 2(3)
Camera Yes/
Yes
interface No(4)
Yes/
PSSI Yes
No(4)
MDF (multi-function
Yes
digital filter)
ADF (audio digital
Yes
filter)
DS13543 Rev 2 19/390

22
STM32U5A5QJ/II
STM32U5A5AJH
STM32U5A9NJH
STM32U5A9BJY
STM32U5A5RJT
STM32U5A5ZJY
STM32U5A9ZJY
STM32U5A5VJT
STM32U5A9VJT
STM32U5A5ZJT
STM32U5A9ZJT
Peripherals
CORDIC co-processor Yes

FMAC (filter
mathematical Yes
accelerator)
RTC (real-time clock) Yes
Tamper pins (without 4/3 8/7 8/8 8/7 NA/7 NA/8 8/8 NA/8
SMPS / with SMPS)
Active tampers (without
3/2 7/6 7/7 7/6 NA/6 NA/7 7/7 NA/7
SMPS / with SMPS)(5)
RNG (true random
Yes
number generator)
SAES, AES Yes
PKA (public key
Yes
accelerator)
HASH (SHA-256) Yes
OTFDEC (on-the-fly
decryption for Yes
OCTOSPI)
GPIOs
(without SMPS / 51/47 82/79 110/106 114/111 NA/111 NA/115 NA/108 136/133 NA/145 NA/156
with SMPS)
Wake-up pins (without
18/17 23/22 24/24 24/23 NA/23 NA/24 NA/24 24/24 NA/24 NA/24
SMPS / with SMPS)
Number of I/Os down
to 1.08 V (without 0/0 0/0 13/10 14/13 NA/13 NA/14 NA/7 14/11 NA/14 NA/14
SMPS / with SMPS)
Capacitive sensing
Number of channels 10/9 19/18 22/22 22/21 NA/21 NA/22 22/22 NA/22
(without SMPS /
with SMPS)
12-bit ADC 1
14-bit ADC 2
Nb of
ADC
channels
(without 17/15 20/18 24/24 24/22 NA/22 NA/24 24/24 NA/24
SMPS /
with SMPS)
20/390 DS13543 Rev 2

STM32U5A5QJ/II
STM32U5A5AJH
STM32U5A9NJH
STM32U5A9BJY
STM32U5A5RJT
STM32U5A5ZJY
STM32U5A9ZJY
STM32U5A5VJT
STM32U5A9VJT
STM32U5A5ZJT
STM32U5A9ZJT
Peripherals
12-bit DAC 1
DAC Nb of 12-bit
2
D-to-A conv.
Internal voltage
No Yes
reference buffer
Analog comparator 2
Operational amplifiers 2
Maximum CPU
160 MHz
frequency
Operating voltage 1.71 to 3.6 V
Ambient operating temperature: –40 to +85 °C / –40 to +125 °C
Operating temperature
Junction temperature: –40 to +105 °C / –40 to +130 °C
LQFP LQFP UFBGA LQFP TFBGA WLCSP TFBGA
Package WLCSP150
64 100 132 144 169 208 216
1. For the LQFP100 package, only FSMC bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 chip select.
2. Two OCTOSPIs are available only in muxed mode.
3. When both are used simultaneously, one supports only SDIO interface.
4. Available on packages without SMPS, not available on packages with SMPS.
5. Active tampers in output sharing mode (one output shared by all inputs).
DS13543 Rev 2 21/390

22
Figure 1. STM32U5Axxx block diagram

CLK, NE[4:1], NL, NBL[1:0],
A[25:0], D[15:0], NOE, NWE,
NJTRST, JTDI, JTCK/SWCLK, JTAG/SW MPU FSMC: SRAM, PSRAM, NOR Flash, FRAM, NAND Flash NWAIT, NCE, INT as AF
JTMS/SWDIO, JTDO
IO[7:0], CLK, NCLK, NCS,
ETM NVIC OTFDEC1 and OCTOSPI1 memory interface
32 Kbytes
DQS as AF
ICACHE
TRACECLK,
OTFDEC2 and OCTOSPI2 memory interface IO[7:0], CLK, NCLK, NCS,
TRACED[3:0] Arm Cortex-M33
C-BUS DQS as AF
160 MHz
TrustZone FPU HSPI1 memory interface IO[15:0], CLK, NCLK, NCS,
DCACHE1
DQS[1:0] as AF
16 Kbytes
S-BUS
Flash memory (up to 4 Mbytes)
AHB bus matrix

RNG
AES
SRAM1 (768 Kbytes) HASH
SAES
DCACHE2 SRAM2 (64 Kbytes)
GPU2D 160 MHz @VDDUSB
16 Kbytes
SRAM3 (832 Kbytes) PKA
FIFO
PHY
DP
USB HS
GFXMMU SRAM5 (832 Kbytes) DM
D[7:0], D[3:1]dir
CMD, CMDdir,CK, CKin SDMMC1 FIFO
D0dir, D2dir DCMI/PSSI D[15:0], CK, CMD as AF
SDMMC2 FIFO AHB2 160 MHz

DMA2D @VDD @VDD
VDD Power management
SHSI
Voltage regulator LDO VDD = 1.71 to 3.6 V
GPDMA1
HSI48 and SMPS VSS
8 groups of 4 channels max TSC MSI @VDD

as AF Reset Supply supervision
SDIN[5:0], CKIN[5:0], CCK0, HSI16 BOR
CCK1 as AF MDF1
VDDIO, VDDUSB, VDDA,
Int
@VSW PLL 1, 2, 3 PVD, PVM VSSA, VDD, VSS, NRST
PA[15:0] GPIO port A
BKPSRAM
PB[15:0] GPIO port B @VDD
(2 Kbytes)
PC[15:13] XTAL OSC OSC_IN
GPIO port C @VSW 4- 50 MHz OSC_OUT
PC[12:0]
LSI IWDG
PD[15:0] GPIO port D
AHB1 160 MHz
PE[15:0] GPIO port E
PF[15:0] GPIO port F Standby

Reset and clock control interface WKUPx (x=1 to 8)
GTZC1
PG[15:2]
GPIO port G
PG[1:0]
TIM2 32b 4 channels, ETR as AF
PH[15:0] GPIO port H CRC
FCLK
HCLKx
PCLKx
PI[15:0] GPIO port I TIM3 32b 4 channels, ETR as AF
CORDIC
PJ[11:0] GPIO port J
CRS TIM4 32b 4 channels, ETR as AF
156 AF EXT IT. WKP FMAC
17xIN @VDDA TIM5 32b 4 channels, ETR as AF

ADC1 ITF
ADC2 smcard
RX, TX, CK, CTS, RTS as AF
USART2 irDA
smcard
USART3 irDA RX, TX, CK, CTS, RTS as AF
R[7:0], G[7:0], B[7:0], CLK,
VSYNC, HSYNC, DE as AF LTDC
smcard
APB1 160 MHz (max)
USART6 irDA RX, TX, CK, CTS, RTS as AF
D1P, D1N, D0P, D0N,
CKP, CKN, TE DSI AHB/APB2 AHB/APB1
UART4 RX, TX, CTS, RTS as AF
3 compl. channels
(TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), TIM1/PWM 16b UART5 RX, TX, CTS, RTS as AF
ETR, BKIN, BKIN2 as AF
MOSI, MISO, SCK, NSS as
3 compl. channels SPI2
AF
(TIM1_CH[1:3]N),
APB2 160 MHz
4 channels (TIM1_CH[1:4]), TIM8/PWM 16b SYSCFG I2C1/SMBUS SCL, SDA, SMBA as AF

ETR, BKIN, BKIN2 as AF
2 channels,
1 compl. channel, BKIN as AF TIM15 16b I2C2/SMBUS SCL, SDA, SMBA as AF
1 channel,
TIM16 16b I2C4/SMBUS SCL, SDA, SMBA as AF
1 compl. channel, BKIN as AF
1 channel, TIM17 16b SCL, SDA, SMBA as AF

WWDG I2C5/SMBUS
1 compl. channel, BKIN as AF
RX, TX, CK,CTS, RTS as AF smcard
USART1 I2C6/SMBUS SCL, SDA, SMBA as AF
irDA
MOSI, MISO, SCK, NSS as
FIFO
AF SPI1 FDCAN1 TX, RX as AF

LPDMA1 SRAM4 (16 Kbytes)
MCLK_A, SD_A, FS_A,
SCK_A, MCLK_B, SD_B,
PHY
SAI1
AHB bus-matrix
UCPD1 CC1, DBCC1, CC2, DBCC2,

FS_B, SCK_B as AF
FRSCC1, FRSCC2 as AF
TIM6 16b
AUDIOCLK as AF
SAI2
MCLK_A, SD_A, FS_A, TIM7 16b IN1, IN2, CH1, CH2,
SCK_A, MCLK_B, SD_B, LPTIM2
ETR as AF
FS_B, SCK_B as AF
@VSW
@VDDA
RTC_OUT1, RTC_OUT2, XTAL 32k
RTC_REFIN, RTC_TS DAC1_OUT1
RTC D/A converter 1
ITF
TAMP_OUT[8:1],
TAMP
TAMP_IN[8:1] D/A converter 2 DAC1_OUT2
@VDDA AHB/APB3
VREF+
VREF buffer @VDDA
APB3 160 MHz
AHB3 160 MHz
@VDDA ITF ADC4 19xIN

INP, INN, OUT
COMP1
COMP2
INP, INN, OUT
@VDDA LPGPIO IO[15:0] as AF

INP, INN, OUT
OPAMP1
OPAMP2
INP, INN, OUT SDIN0, CKIN0, CCK0,
ADF1
CCK1 as AF
IN1, IN2, CH1, CH2,
LPTIM1
ETR as AF
IN1, IN2, CH1, CH2, GTZC2
LPTIM3
ETR as AF
IN1, OUT, ETR as AF LPTIM4
SCL, SDA, SMBA as AF I2C3/SMBUS VDDUSB power VDDIO2 power VDDA power
VDD power domain VSW power domain
domain domain domain
MOSI, MISO, SCK, NSS as SPI3
AF
RX, TX, CTS, RTS_DE as
Note: VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
LPUART1
AF MSv66059V5
22/390 DS13543 Rev 2

STM32U5Axxx Functional overview
3 Functional overview
3.1 Arm Cortex-M33 core with TrustZone and FPU

The Cortex-M33 with TrustZone and FPU is a highly energy-efficient processor designed for
microcontrollers and deeply embedded applications, especially those requiring efficient
security.
The Cortex-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. It features:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and
nonsecure states
• MPUs (memory protection units), supporting up to 16 regions for secure and
non-secure applications
• Configurable SAU (secure attribute unit) supporting up to eight memory regions as
secure or nonsecure
• Floating-point arithmetic functionality with support for single precision arithmetic
The processor supports a set of DSP instructions that allows an efficient signal processing
and a complex algorithm execution.
The Cortex-M33 processor supports the following bus interfaces:
• System AHB bus:
The S-AHB (system AHB) bus interface is used for any instruction fetch and data
access to the memory-mapped SRAM, peripheral, external RAM and external device,
or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus:
The C-AHB (code AHB) bus interface is used for any instruction fetch and data access
to the code region of the Armv8-M memory map.
Figure 1 shows the general block diagram of the STM32U5Axxx devices.
3.2 ART Accelerator (ICACHE and DCACHE)
3.2.1 Instruction cache (ICACHE)

The ICACHE is introduced on C-AHB code bus of Cortex-M33 processor to improve
performance when fetching instruction (or data) from both internal and external memories.
ICACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 C-AHB code
execution port
– Master1 port performing refill requests to internal memories (flash memory and
SRAMs)
– Master2 port performing refill requests to external memories (external flash
memory and RAMs through Octo-SPI and FMC interfaces)
– Second slave port dedicated to ICACHE registers access
DS13543 Rev 2 23/390

99
Functional overview STM32U5Axxx
• Close to zero wait-states instructions/data access performance:

– 0 wait-state on cache hit
– Hit-under-miss capability, allowing to serve new processor requests while a line
refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy, minimizing processor stalls on cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Dual master ports allowing to decouple internal and external memory traffics, on
fast and slow buses, respectively; also minimizing impact on interrupt latency
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of a hit counter and a miss counter
• Extension of cacheable region beyond the code memory space, by means of address
remapping logic that allows four cacheable external regions to be defined
• Power consumption reduced intrinsically (more accesses to cache memory rather to
bigger main memories); even improved by configuring ICACHE as direct mapped
(rather than the default two-ways set-associative mode)
• TrustZone security support
• Maintenance operation for software management of cache coherency
• Error management: detection of unexpected cacheable write access, with optional
interrupt raising
3.2.2 Data cache (DCACHE)

The DCACHE is introduced on S-AHB system bus of Cortex-M33 processor to improve the
performance of data traffic to/from external memories.
DCACHE offers the following features:
• Multi-bus interface:
– Slave port receiving the memory requests from the Cortex-M33 S-AHB system
port
– Master port performing refill requests to external memories (external flash memory
and RAMs through Octo-SPI and FMC interfaces)
– Second slave port dedicated to DCACHE registers access
• Close to zero wait-states external data access performance:
– Zero wait-states on cache hit
– Hit-under-miss capability, allowing to serve new processor requests to cached
data, while a line refill (due to a previous cache miss) is still ongoing
– Critical-word-first refill policy for read transactions, minimizing processor stalls on
cache miss
– Hit ratio improved by two-ways set-associative architecture and pLRU-t
replacement policy (pseudo-least-recently-used, based on binary tree), algorithm
with best complexity/performance balance
– Optimal cache line refill thanks to AHB burst transactions (of the cache line size)
– Performance monitoring by means of two hit counters (for read and write) and two
miss counters (for read and write)
24/390 DS13543 Rev 2

• Supported cache accesses:

– Both write-back and write-through policies supported (selectable with AHB
bufferable attribute)
– Read and write-back always allocated
– Write-through always non-allocated (write-around)
– Byte, half-word and word writes supported
• TrustZone security support
• Maintenance operations for software management of cache coherency:
– Full cache invalidation (non interruptible)
– Address range clean and/or invalidate operations (background task, interruptible)
• Error management: detection of error for master port request initiated by DCACHE (line
eviction or clean operation), with optional interrupt raising
3.3 Memory protection unit

The MPU (memory protection unit) is used to manage the CPU accesses to the memory
and to prevent one task to accidentally corrupt the memory or the resources used by any
other active task. This memory area is organized into up to 16 protected areas.
The MPU regions and registers are banked across secure and nonsecure states.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by a RTOS
(real-time operating system).
If a program accesses a memory location that is prohibited by the MPU, the RTOS can
detect it and take action. In a RTOS environment, the kernel can dynamically update the
MPU area setting based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.4 Embedded flash memory

The devices feature 4 Mbytes of embedded flash memory that is available for storing
programs and data. The flash memory supports 10 000 cycles and up to 100 000 cycles
on 512 Kbytes. A 128-bit instruction prefetch is implemented and can optionally be enabled.
The flash memory interface features:
• Dual-bank operating modes
• Read-while-write (RWW)
This allows a read operation to be performed from one bank while an erase or program
operation is performed to the other bank. The dual-bank boot is also supported. Each bank
contains 256 pages of 8 Kbytes. The flash memory also embeds 512-byte OTP (one-time
programmable) for user data.
The whole non-volatile memory embeds the ECC (error correction code) feature supporting:
• single-error detection and correction
• double-error detection
• ECC fail address report
DS13543 Rev 2 25/390

99
3.4.1 Flash memory protection

The option bytes allow the configuration of flexible protections:
• write protection (WRP) to protect areas against erasing and programming. Two areas
per bank can be selected with 8-Kbyte granularity.
• RDP (readout protection) to protect the whole memory, has four levels of protection
available (see Table 3 and Table 4):
– Level 0: no readout protection
– Level 0.5: available only when TrustZone is enabled
All read/write operations (if no write protection is set) from/to the nonsecure flash
memory are possible. The debug access to secure area is prohibited.
Debug access to nonsecure area remains possible.
– Level 1: memory readout protection
The flash memory cannot be read from or written to if either the debug features
are connected or the boot in RAM or bootloader are selected. If TrustZone is
enabled, the nonsecure debug is possible and the boot in SRAM is not possible.
Regressions from Level 1 to lower levels can be protected by password
authentication.
– Level 2: chip readout protection
The debug features, the boot in RAM and the bootloader selection are disabled.
A secure secret key can be configured in the secure options to allow the
regression capability from Level 2 to Level 1. By default (key not configured), this
Level 2 selection is irreversible and JTAG/SWD interfaces are disabled. If the
secret key was previously configured in lower RDP levels, the device enables the
RDP regression from Level 2 to Level 1 after password authentication through
JTAG/SWD interface.
Note: In order to reach the best protection level, it is recommended to activate TrustZone and to
set the RDP Level 2 with password authentication regression enabled.
Table 3. Access status versus protection level and execution modes when TZEN = 0
User execution
RDP Debug/boot from RAM/ bootloader(1)
Area (boot from flash memory)
level
Read Write Erase Read Write Erase
1 Yes Yes Yes No No No(4)

Flash main memory
2 Yes Yes Yes N/A N/A N/A
1 Yes No No Yes No No
System memory (2)
2 Yes No No N/A N/A N/A
1 Yes Yes(4) N/A Yes Yes(4) N/A

Option bytes(3)
2 Yes No(5) N/A N/A N/A N/A
1 Yes Yes(6) N/A Yes Yes(6) N/A

OTP
2 Yes Yes(6) N/A N/A N/A N/A
26/390 DS13543 Rev 2

Table 3. Access status versus protection level and execution modes when TZEN = 0 (continued)
User execution
RDP Debug/boot from RAM/ bootloader(1)
level
1 Yes Yes N/A No No N/A(7)

Backup registers
2 Yes Yes N/A N/A N/A N/A

SRAM2/backup
RAM
1 Yes Yes Yes No(9) Yes Yes

OTFDEC regions
(Octo-SPI)
1. When the protection level 2 is active, the debug port, the boot from RAM and the boot from system memory are disabled.
2. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
3. Option bytes are only accessible through the flash memory registers and OPSTRT bit.
4. The Flash main memory is erased when the RDP option byte changes from level 1 to level 0.
5. SWAP_BANK option bit can be modified.
6. OTP can only be written once.
7. The backup registers are erased when RDP changes from level 1 to level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.
9. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.
Table 4. Access status versus protection level and execution modes when TZEN = 1
User execution
RDP Debug/ bootloader(1)
level
0.5 Yes Yes Yes Yes(2) Yes(2) Yes(2)
Flash main memory 1 Yes Yes Yes No No No(5)
0.5 Yes No No Yes No No
System memory (3) 1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
0.5 Yes Yes(5) N/A Yes Yes (5) N/A
Option bytes(4) 1 Yes Yes(5) N/A Yes Yes(5) N/A
2 Yes No(6) N/A N/A N/A N/A
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Table 4. Access status versus protection level and execution modes when TZEN = 1 (continued)
User execution
RDP Debug/ bootloader(1)
level
0.5 Yes Yes(7) N/A Yes Yes(7) N/A
OTP 1 Yes Yes(7) N/A Yes Yes(7) N/A
2 Yes Yes(7) N/A N/A N/A N/A
0.5 Yes Yes N/A Yes(2) Yes(2) N/A(8)
Backup registers 1 Yes Yes N/A No No N/A(8)
0.5 Yes Yes N/A Yes(2) Yes(2) N/A(9)

SRAM2/backup
RAM
0.5 Yes Yes Yes No(10) Yes Yes

OTFDEC regions
1 Yes Yes Yes No(10) Yes Yes
(Octo-SPI)
1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Depends on TrustZone security access rights.
3. The system memory is only read-accessible, whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the flash memory registers and OPSTRT bit.
5. The Flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
6. SWAP_BANK option bit can be modified.
7. OTP can only be written once.
8. The backup registers are erased when RDP changes from level 1 to level 0.
9. All SRAMs are erased when RDP changes from level 1 to level 0.
10. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.
3.4.2 Additional flash memory protections when TrustZone activated

When the TrustZone security is enabled through option bytes, the whole flash memory is
secure after reset and the following protections are available:
• non-volatile watermark-based secure flash memory area
The secure area can be accessed only in Secure mode. One area per bank can be
selected with a page granularity.
• secure HDP (hide protection area)
It is part of the flash memory secure area and can be protected to deny an access to
this area by any data read, write and instruction fetch. For example, a software code in
the secure flash memory hide protection area can be executed only once and deny any
28/390 DS13543 Rev 2

further access to this area until next system reset. One area per bank can be selected
at the beginning of the secure area.
• volatile block-based secure flash memory area
Each page can be programmed on-the-fly as secure or nonsecure.
3.4.3 FLASH privilege protection

Each flash memory page can be programmed on the fly as privileged or unprivileged.
3.5 Embedded SRAMs

Six SRAMs are embedded in the STM32U5Axxx devices, each with specific features.
SRAM1, SRAM2, SRAM3 and SRAM5 are the main SRAMs. SRAM4 is in the SRAM used
for peripherals LPBAM (low-power background autonomous mode) in Stop 2 mode.
These SRAMs are made of several blocks that can be powered down in Stop mode to
reduce consumption:
• SRAM1: 12 64-Kbyte blocks (total 768 Kbytes)
• SRAM2: 8-Kbyte + 56-Kbyte blocks (total 64 Kbytes) with optional ECC. In addition
SRAM2 blocks can be retained in Standby mode.
• SRAM3: 13 64-Kbyte blocks (total 832 Kbytes) with optional ECC. When ECC is
enabled, 256 Kbytes support ECC and 512 Kbytes of SRAM3 can be accessed
without ECC.
• SRAM4: 16 Kbytes
• SRAM5: 13 64-Kbyte blocks (total 832 Kbytes)
• BKPSRAM (backup SRAM): 2 Kbytes with optional ECC. The BKPSRAM can be
retained in all low-power modes and when VDD is off in VBAT mode, but not in
Shutdown mode.
3.5.1 SRAMs TrustZone security

When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM1,
SRAM2, SRAM3, SRAM4 and SRAM5 can be programmed as secure or nonsecure by
blocks, using the MPCBB (block-based memory protection controller).
The granularity of SRAM secure block based is a page of 512 bytes. Backup SRAM regions
can be programmed as secure or nonsecure with watermark, using the TZSC (TrustZone
security controller) in the GTZC (global TrustZone controller).
3.5.2 SRAMs privilege protection

The SRAM1, SRAM2, SRAM3, SRAM4 and SRAM5 can be programmed as privileged or
unprivileged by blocks, using the MPCBB. The granularity of SRAM privilege block based is
a page of 512 bytes. Backup SRAM regions can be programmed as privileged or
unprivileged with watermark, using the TZSC (TrustZone security controller) in the GTZC
(global TrustZone controller).
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3.6 TrustZone security architecture

The security architecture is based on Arm TrustZone with the Armv8-M main extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the access permissions based on secure
and nonsecure state.
• SAU: up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition as nonsecure or nonsecure callable
attributes. It is then combined with the results from the SAU security attribution and
the higher security state is selected.
Based on IDAU security attribution, the flash memory, system SRAM and peripheral
memory space is aliased twice for secure and nonsecure states. However, the external
memory space is not aliased.
The table below shows an example of typical SAU region configuration based on IDAU
regions. The user can split and choose the secure, nonsecure or NSC regions for external
memories as needed.
Table 5. Example of memory map security attribution versus SAU configuration regions
SAU security
Region IDAU security Final security
Address range attribution typical
description attribution attribution
configuration
0x0000 0000 Secure or Secure or

Code - external memories Nonsecure
0x07FF FFFF nonsecure or NSC(1) nonsecure or NSC
0x0800 0000
Nonsecure Nonsecure Nonsecure
0x0BFF FFFF
Code - Flash and SRAM
0x0C00 0000
NSC Secure or NSC Secure or NSC
0x0FFF FFFF
0x1000 0000
0x17FF FFFF
Code - external memories Nonsecure
0x1800 0000
Nonsecure
0x1FFF FFFF
0x2000 0000
Nonsecure
0x2FFF FFFF
SRAM
0x3000 0000
0x3FFF FFFF
0x4000 0000
Nonsecure Nonsecure Nonsecure
0x4FFF FFFF
Peripherals
0x5000 0000
0x5FFF FFFF
0x6000 0000 Secure or Secure or
External memories Nonsecure
0xDFFF FFFF nonsecure or NSC nonsecure or NSC
1. NSC = nonsecure callable.
30/390 DS13543 Rev 2

3.6.1 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either securable or
TrustZone-aware type as follows:
• securable: peripheral protected by an AHB/APB firewall gate that is controlled from
TZSC to define security properties
• TrustZone-aware: peripheral connected directly to AHB or APB bus and implementing
a specific TrustZone behavior such as a subset of registers being secure
3.6.2 Default TrustZone security state

The default system security state is detailed below:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address.
• Memory map:
– SAU is fully secure after reset. Consequently, all memory map is fully secure.
Up to eight SAU configurable regions are available for security attribution.
• Flash memory:
– Flash memory security area is defined by watermark user options.
– Flash memory block based area is nonsecure after reset.
• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is secure.
• External memories:
– FSMC, OCTOSPI banks are secure after reset. MPCWMx (memory protection
watermark based controller) is secure.
• Peripherals
– Securable peripherals are nonsecure after reset.
– TrustZone-aware peripherals are nonsecure after reset. Their secure configuration
registers are secure.
• All GPIOs are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and
nonsecure state.
• TZIC: All illegal access interrupts are disabled after reset.
3.7 Boot modes

At startup, a BOOT0 pin, nBOOT0, NSBOOTADDx[24:0] (x = 0,1) and
SECBOOTADD0[24:0] option bytes are used to select the boot memory address that
includes:
• Boot from any address in user flash memory.
• Boot from system memory bootloader.
• Boot from any address in embedded SRAM.
• Boot from RSS (root security services).
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The BOOT0 value comes from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
The bootloader is located in the system memory, programmed by ST during production.
The bootloader is used to reprogram the flash memory by using USART, I2C, SPI, FDCAN
or USB OTG_HS in device mode through the DFU (device firmware upgrade).
The bootloader is available on all devices. Refer to the application note
STM32 microcontroller system memory boot mode (AN2606) for more details.
The RSS are embedded in a flash memory area named secure information block,
programmed during ST production.
For example, the RSS enable the SFI (secure firmware installation), thanks to the RSSe SFI
(RSS extension firmware).
This feature allows customer to produce the confidentiality of the firmware to be provisioned
into the STM32, when production is sub-contracted to untrusted third party.
The RSS are available on all devices, after enabling the TrustZone through the TZEN option
bit. Refer to the application note Overview secure firmware install (SFI) (AN4992)
for more details.
Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and
enabled respectively.
Table 6. Boot modes when TrustZone is disabled (TZEN = 0)

nBOOT0 nSWBOOT0 Boot address
BOOT0 ST programmed
FLASH_ FLASH_ option-byte Boot area
pin PH3 default value
OPTR[27] OPTR[26] selection
Boot address defined by

- 0 1 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Bootloader:
- 1 1 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]
1 - 0 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Bootloader:
0 - 0 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]
When TrustZone is enabled by setting the TZEN option bit, the boot space must be in the
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit, allowing
to boot always at the address selected by SECBOOTADD0[24:0] option bytes. All other boot
options are ignored.
32/390 DS13543 Rev 2

Table 7. Boot modes when TrustZone is enabled (TZEN = 1)

nBOOT0 BOOT0 nSWBOOT0 RSS Boot address ST
BOOT_
FLASH_ pin FLASH_ com- option-byte Boot area programmed
LOCK
OPTR[27] PH3 OPTR[26] mand selection default value
Secure boot address

SECBOOTADD0 defined by user Flash:
- 0 1 0
[24:0] option bytes 0x0C00 0000
SECBOOTADD0[24:0]
RSS:
- 1 1 0 N/A RSS
0x0FF8 0000
Secure boot address
0
1 - 0 0
SECBOOTADD0[24:0]
RSS:
0 - 0 0 N/A RSS
0x0FF8 0000
RSS:
- - - ≠0 N/A RSS
0x0FF8 0000
Secure boot address
1 - - - -
SECBOOTADD0[24:0]
The boot address option bytes allow any boot memory address to be programmed.
However, the allowed address space depends on the flash memory RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot address is forced either in secure flash memory or
nonsecure flash memory, depending on TrustZone security option as described in the table
below.
Table 8. Boot space versus RDP protection

RDP TZEN = 1 TZEN = 0
0 Any boot address Any boot address

0.5 N/A
1 Boot address only in RSS or secure flash memory: Any boot address
0x0C00 0000 - 0x0C3F FFFF Boot address only in flash memory:
2 Otherwise, forced boot address is 0x0FF8 0000. 0x0800 0000 - 0x083F FFFF
Otherwise, forced boot address is 0x0800 0000.
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3.8 Global TrustZone controller (GTZC)

GTZC is used to configure TrustZone and privileged attributes within the full system.
The GTZC includes three different sub-blocks:
• TZSC: TrustZone security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the nonsecure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• TZIC: TrustZone illegal access controller
This sub-block gathers all security illegal access events in the system and generates
a secure interrupt towards NVIC.
• MPCBB: MPCBB: block-based memory protection controller
This sub-block controls secure states of all memory blocks (512-byte pages) of the
associated SRAM. This peripheral aims at configuring the internal RAM in a TrustZone
system product having segmented SRAM with programmable-security and privileged
attributes.
The GTZC main features are:
• Three independent 32-bit AHB interfaces for TZSC, TZIC and MPCBB
• Secure and nonsecure access supported for privileged/unprivileged part of TZSC
• Set of registers to define product security settings:
– Secure/privilege regions for external memories
– Secure/privilege access mode for securable peripherals
– Secure/privilege access mode for securable legacy masters
3.9 Power supply management

The PWR (power controller) main features are:
• Power supplies and supply domains
– Core domain (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– SMPS power stage (VDDSMPS, available only on SMPS packages)
– VDDIO2 domain
– VDDUSB and optional VDD11USB for USB transceiver
– VDDDSI and VDD11DSI for DSI transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
34/390 DS13543 Rev 2

• Power supply supervision

– BOR monitor
– PVD monitor
– PVM monitor (VDDA, VDDUSB, VDDIO2)
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security and privileged protection
3.9.1 Power supply schemes

The devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several independent
supplies can be provided for specific peripherals:
• VDD = 1.71 V to 3.6 V (functionality guaranteed down to VBORx min value)
VDD is the external power supply for the I/Os, the internal regulator and the system
analog such as reset, power management and internal clocks. It is provided externally
through the VDD pins.
• VDDA = 1.58 V (COMPs) / 1.6 V (DACs, OPAMPs) / 1.62 V (ADCs) /
1.8 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for ADCs, DACs, voltage reference buffer,
operational amplifiers and comparators. The VDDA voltage level is independent from
the VDD voltage and must be connected to VDD or VSS pin (preferably to VDD) when
these peripherals are not used.
• VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step-down converter. It is provided
externally through VDDSMPS supply pin. It must be connected to the same supply as
VDD pin when the SMPS is used in the application. When the SMPS is not used, it is
recommended to connect both VDDSMPS and VLXSMPS to GND.
• VLXSMPS is the switched SMPS step down converter output.
Note: The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. VDDUSB
voltage level is independent from the VDD voltage and must be connected to VDD or
VSS pin (preferably to VDD) when the USB is not used.
• VDD11USB = 1.0 V to 1.26 V
VDD11USB is the external power supply for the USB transceiver. This supply is only
available on specific packages and must be connected to VDD11.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level
is independent from the VDD voltage and must be connected to VDD or VSS pin
(preferably to VDD) when PG[15:2] are not used.
• VBAT = 1.65 V to 3.6 V (functionality guaranteed down to VBOR_VBAT min value)
VBAT is the power supply for RTC, TAMP, external and internal 32 kHz oscillators, and
DS13543 Rev 2 35/390

99
backup registers (through power switch) when VDD is not present.

• VDDDSI = 1.71 V to 3.6 V
VDDDSI is the external power supply for the DSI controller. It is provided externally
through VDDDSI supply pin, and must be connected to the same supply as VDD pin.
• VDD11DSI = 1.0 V to 1.26 V
VDD11DSI is the external power supply for the DSI transceiver and must be connected to
VDD11.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports four outputs:
– VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are
bonded to VSSA and VDDA, respectively.
When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disabled.
VREF- must always be equal to VSSA.
The STM32U5Axxx devices embed two regulators: one LDO and one SMPS in parallel to
provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3, SRAM4,
SRAM5 and embedded flash memory. The SMPS generates this voltage on VDD11 (two or
three pins) with a total external capacitor of 4.7 μF typical. SMPS requires an external coil of
2.2 μH typical. The LDO generates this voltage on VCAP (one or two) pin(s) with a total
external capacitor of 4.7 μF typical.
Both regulators can provide four different voltages (voltage scaling) and can operate in
Stop modes. It is possible to switch from SMPS to LDO and from LDO to SMPS on-the-fly
(refer to the product reference manual for more details).
36/390 DS13543 Rev 2

Figure 2. STM32U5AxxxxxQ power supply overview (with SMPS)

VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer
VDDUSB
VDD11USB(1) USB transceiver
VSS
VDDDSI(2)
VDD11DSI(2) DSI transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]
VDD domain
VDDIO1 I/O ring
Reset block
Temperature sensor
3 x PLL VCORE domain
Internal RC oscillators
Core
VSS Standby circuitry

SRAM1
(Wake-up logic, IWDG)
SRAM2
VDD SRAM3
Voltage regulator SRAM4
LDO regulator SRAM5
VCORE
VDD11 Digital
VLXSMPS SMPS regulator peripherals
VDDSMPS
VSSSMPS
Flash memory
Low-voltage detector
Backup domain
VSW LSE crystal 32kHz oscillator
VBAT LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
Notes: RTC
1. Only available on specific packages. TAMP
2. Only available on some devices. BKPSRAM
MSv66057V5
DS13543 Rev 2 37/390

99
Figure 3. STM32U5Axxx power supply overview (without SMPS)
VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer
VDDUSB
VDD11USB(1) USB transceiver
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS PG[15:2]
VDD domain
VDDIO1 I/O ring
VCORE domain
Reset block
Temperature sensor Core
3 x PLL
VSS Internal RC oscillators SRAM1
SRAM2
Standby circuitry SRAM3
VDD (Wake-up logic, IWDG) SRAM4
SRAM5
VCORE
VCAP Digital
LDO regulator peripherals
Flash memory
Low-voltage detector
Backup domain
VBAT VSW LSE crystal 32kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
Note:
TAMP
1. Only available on specific packages.
BKPSRAM
MSv66058V2
In this document, VDDIOx (with x = 1 or 2) refers to the I/O power supply. VDDIO1 is supplied
by VDD. VDDIO2 is the independent power supply for PG[15:2].
VSW = VDD when VDD is above VBOR0, and VSW = VBAT when VDD is below VBOR0.
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
• During the power-down phase, VDD can temporarily become lower than other supplies
only if the energy provided to the MCU remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the
power-down transient phase.
38/390 DS13543 Rev 2

Figure 4. Power-up /down sequence
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.
3.9.2 Power supply supervisor

The devices have an integrated ultra-low-power BOR (Brownout reset) active in all modes
(except for Shutdown mode). The BOR ensures proper operation of the device after power
on and during power down. The device remains in reset mode when the monitored supply
voltage VDD is below a specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71 V at power on, and other higher thresholds can be selected
through option bytes.The devices feature an embedded PVD (programmable voltage
detector) that monitors the VDD power supply and compares it to the VPVD threshold.
An interrupt can be generated when VDD drops below and/or rises above the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
In addition, the devices embed a peripheral voltage monitor that compares the independent
supply voltages VDDA, VDDUSB and VDDIO2 to ensure that the peripheral is in its functional
supply range.
The devices support dynamic voltage scaling to optimize its power consumption in Run
mode. The voltage from the main regulator that supplies the logic (VCORE) can be adjusted
according to the system’s maximum operating frequency.
The main regulator operates in the following ranges:
• Range 1 (VCORE = 1.2 V) with CPU and peripherals running at up to 160 MHz
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3.9.3 Low-power modes

The ultra-low-power STM32U5Axxx devices support seven low-power modes to achieve the
best compromise between low-power consumption, short startup time, available peripherals
and available wake-up sources.
The table below details the related low-power modes.
Table 9. STM32U5Axxx modes overview

Regulator
Mode (1) CPU Flash SRAM Clocks DMA and peripherals(2) Wake-up source
Range 1
All
Range 2
Run Range 3 Yes ON(3) ON Any All except DSI and OTG_HS N/A
All except DSI, LTDC, OTG_HS

Range 4
and UCPD
Range 1
All
Range 2
Any interrupt or
Sleep Range 3 No ON ON(4) Any All except DSI and OTG_HS event
All except DSI, LTDC, OTG_HS
Range 4
and UCPD
Range 1 Reset pin, all I/Os
BOR, PVD, PVM,
Range 2 BOR, PVD, PVM,
RTC, TAMP, IWDG,
Stop 0 RTC, TAMP, IWDG,
Range 3 TEMP (temp. sensor), VREFBUF,
TEMP, ADC4
ADC4(7),
Range 4 DAC1 (2 channels),
DAC1 (2 channels)(8),
COMPx (x = 1, 2),
COMPx (x = 1, 2),
USARTx (x = 1...6),
OPAMPx (x = 1,2),
LSE LPUART1,
USARTx (x = 1...6)(9), LPUART1,
No OFF ON(5) LSI SPIx (x = 1...3),
(6) SPIx (x = 1...3)(10),
I2Cx (x = 1...6),
I2Cx (x = 1...6)(11),
LPTIMx (x = 1...4),
Stop 1 LPR LPTIMx (x = 1...4)(12),
MDF1, ADF1,
MDF1(13), ADF1,
GPDMA1,
GPIO, LPGPIO,
LPDMA1,
GPDMA1(14), LPDMA1
OTG_HS, UCPD
All other peripherals are frozen.
40/390 DS13543 Rev 2

Table 9. STM32U5Axxx modes overview (continued)

Regulator
Mode (1) CPU Flash SRAM Clocks DMA and peripherals(2) Wake-up source
BOR, PVD, PVM, Reset pin, all I/Os

RTC, TAMP, IWDG, BOR, PVD, PVM,
TEMP, VREFBUF, RTC, TAMP, IWDG,
ADC4, TEMP,
DAC1 (2 channels), ADC4,
COMPx (x = 1, 2) , COMPx (x = 1, 2),
OPAMPx (x = 1, 2), LPUART1,
LSE LPUART1, SPI3,
Stop 2 LPR No OFF ON(5)
LSI SPI3, I2C3,
I2C3, LPTIMx (x = 1,3,4),
LPTIMx (x = 1,3,4), ADF1,
ADF1, LPDMA1
LPGPIO,
LPDMA1

BOR, Reset pin,
RTC, TAMP, IWDG, 24 I/Os (WKUPx),
DAC1 (2 static channels), BOR, RTC, TAMP,
OPAMPx (x = 1, 2) IWDG
LSE
Stop 3 LPR No OFF ON(5)
LSI
I/O configuration can be floating,

pull-up or pull-down.
all other SRAMs powered off
Reset pin,
64-, 56- or 8-Kbyte SRAM2
BOR, RTC, TAMP, IWDG

2-Kbyte BKPSRAM(5)
24 I/Os (WKUPx),
All other peripherals are powered BOR, RTC, TAMP,
off. IWDG
LPR
Powered off
LSE I/O configuration can be floating,

Standby OFF
LSI pull-up or pull-down.
Powered
OFF
off
RTC, TAMP Reset pin

24 I/Os (WKUPx)
Powered off
Powered
All other peripherals are powered RTC, TAMP

Shutdown OFF OFF LSE off.
off
I/O configuration can be floating,

pull-up or pull-down(15).
DS13543 Rev 2 41/390

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1. LPR means that the main regulator is OFF and the low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM. One bank can also
be put in power-down mode.
4. The SRAM1, SRAM2, SRAM3, SRAM4, SRAM5 and BKPSRAM clocks can be gated on or off independently.
5. The SRAM can be individually powered off to save power consumption.
6. MSI and HSI16 can be temporary enabled upon peripheral request, for autonomous functions with DMA or wake-up from
Stop event detections.
7. The ADC4 conversion is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on
conversion events.
8. DAC1 is the digital-to-analog (D/A) converter controller instance name. This instance controls two D/A converters also
called "two channels". The DAC conversions are functional and autonomous with DMA in Stop mode.
9. U(S)ART and LPUART transmission and reception is functional and autonomous with DMA in Stop mode, and can
generate a wake-up interrupt on transfer events.
10. SPI transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up
interrupt on transfer events.
11. I2C transmission and reception is functional and autonomous with DMA in Stop mode, and can generate a wake-up
interrupt on transfer events.
12. LPTIM is functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on all events.
13. MDF and ADF are functional and autonomous with DMA in Stop mode, and can generate a wake-up interrupt on events.
14. GPDMA and LPDMA are functional and autonomous in Stop mode, and can generate a wake-up interrupt on events.
15. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
By default, the microcontroller is in Run mode after a system or a power reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop 0, Stop 1, Stop 2, and Stop 3 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. The SRAMs can be totally or partially switched off to further
reduce consumption. All clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16, the HSI48 and the HSE crystal oscillators are disabled. The LSE or LSI is
still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals are autonomous and can operate in Stop mode by requesting their
kernel clock and their bus (APB or AHB) when needed, in order to transfer data with
DMA (GPDMA1 in Stop 0 and Stop 1 modes, LPDMA1 in Stop 0, Stop 1 and Stop 2
modes). Refer to Low-power background autonomous mode (LPBAM) for more details.
LPBAM is not supported in Stop 3 mode.
In Stop 2 and Stop 3 modes, most of the VCORE domain is put in a lower leakage mode.
Stop 0 and Stop 1 modes offer the largest number of active peripherals and wake-up
sources, a smaller wake-up time but a higher consumption than Stop 2 mode.
In Stop 0 mode, the main regulator remains ON, allowing a very fast wake-up time but
with much higher consumption.
Stop 3 is the lowest power mode with full retention, but the functional peripherals and
sources of wake-up are reduced to the same ones than in Standby mode.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 mode can be either MSI
up to 24 MHz or HSI16, depending on software configuration.
42/390 DS13543 Rev 2

• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI, the HSI16, the HSI48 and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The BOR always remains active in Standby mode.
The state of each I/O during Standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAMs and register contents are lost except for registers
and backup SRAM in the Backup domain and Standby circuitry. Optionally, the full
SRAM2 or 8 Kbytes or 56 Kbytes can be retained in Standby mode, supplied by the
low-power regulator (Standby with SRAM2 retention mode).
The BOR can be configured in ultra-low-power mode to further reduce power
consumption during Standby mode.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm,
periodic wake-up, timestamp), or a tamper detection. The tamper detection can be
raised either due to external pins or due to an internal failure detection.
The system clock after wake-up is MSI up to 4 MHz.
• Shutdown mode
The lowest power consumption is achieved in Shutdown mode. The internal regulator
is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the HSI48, the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to backup domain is not supported (VBAT mode is not
supported).
SRAMs and register contents are lost except for registers in the backup domain as long
as VDD is present.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wake-up, timestamp), or a tamper detection.
The system clock after wake-up is MSI at 4 MHz.
Low-power background autonomous mode (LPBAM)

The ultra-low-power STM32U5Axxx devices support LPBAM (low-power background
autonomous mode) that allows peripherals to be functional and autonomous in Stop mode
(Stop 0, Stop 1 and Stop 2 modes), so without any software running.
In Stop 0 and Stop 1 modes, the autonomous peripherals are the following: ADC4, DAC1,
LPTIMx (x = 1 to 4), USARTx (x = 1 to 6), LPUART1, SPIx (x = 1 to 3), I2Cx (x = 1 to 6),
MDF1, ADF1, GPDMA1 and LPDMA1. In these modes, SRAM1, SRAM2, SRAM3, SRAM4
and SRAM5 can be accessed by the GPDMA1, and SRAM4 can be accessed
by the LPDMA1.
In Stop 2 mode, the autonomous peripherals are the following: ADC4, DAC1, LPTIM1,
LPTIM3, LPTIM4, LPUART1, SPI3, I2C3, ADF1 and LPDMA1. In this mode, the SRAM4
can be accessed by the LPDMA1.
DS13543 Rev 2 43/390

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Those peripherals support the features detailed below:

• Functionality in Stop mode thanks to its own independent clock (named kernel clock)
request capability: the peripheral kernel clock is automatically switched on when
requested by a peripheral, and automatically switched off when no peripheral
requests it.
• DMA transfers supported in Stop mode thanks to system clock request capability: the
system clock (MSI or HSI16) automatically switched on when requested by
a peripheral, and automatically switched off when no peripheral requests it. When the
system clock is requested by an autonomous peripheral, the system clock is woken up
and distributed to all peripherals enabled in the RCC. This allows the DMA to access
the enabled SRAM, and any enabled peripheral register (for instance GPIO or LPGPIO
registers).
• Automatic start of the peripheral thanks to hardware synchronous or asynchronous
triggers (such as I/Os edge detection and low-power timer event).
• Wake-up from Stop mode with peripheral interrupt.
The GPDMA and LPDMA are fully functional and the linked-list is updated in Stop mode,
allowing the different DMA transfers to be linked without any CPU wake-up. This can be
used to chain different peripherals transfers, or to write peripherals registers in order to
change their configuration while remaining in Stop mode.
The DMA transfers from memory to memory can be started by hardware synchronous or
asynchronous triggers, and the DMA transfers between peripherals and memories can also
be gated by those triggers.
Here below some use-cases that can be done while remaining in Stop mode:
• A/D or D/A conversion triggered by a low-power timer (or any other trigger)
– wake-up from Stop mode on analog watchdog if the A/D conversion result is out of
programmed thresholds
– wake-up from Stop mode on DMA buffer event
• Audio digital filter data transfer into SRAM
– wake-up from Stop on sound-activity detection
• I2C slave reception or transmission, SPI reception, UART/LPUART reception
– wake-up at the end of peripheral transfer or on DMA buffer event
2
• I C master transfer, SPI transmission, UART/LPUART transmission, triggered by
a low-power timer (or any other trigger):
– example: sensor periodic read
– wake-up at the end of peripheral transfer or on DMA buffer event
• Bridges between peripherals
– example: ADC converted data transferred by communication peripherals
• Data transfer from/to GPIO/LPGPIO to/from SRAM for:
– controlling external components
– implementing data transmission and reception protocols
44/390 DS13543 Rev 2

Table 10. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Stop 3 Standby Shutdown
capability
capability
capability
capability
capability
Peripheral Run Sleep VBAT
Wake-up
Wake-up
Wake-up
Wake-up
Wake-up
- - - - -
CPU Y - - - - - - - - - - - -
Flash memory O(2) O (2)
- - - - - - - - - - -
SRAM1 Y(3)(4) Y(3)(4) O(7) - O(7) - O(7) - - - - - -
O
SRAM2 Y(3)(4) Y(3)(4) O(7) O(5) O(7) - O(7) - (6) - - - -
SRAM3 Y(3)(4) Y(3)(4) O(7) O(5) O(7) - O(7) - - - - - -

(3)(4)
SRAM4 Y Y(3)(4) O(7) - O(7) - O(7) - - - - - -
SRAM5 Y(3)(4) Y(3)(4) O(7) - O(7) - O(7) - - - - - -
BKPSRAM O(4) O(4) O O(5) O O O O
FSMC O O - - - - - - - - - - -
OCTOSPIx (x =1,2) O O - - - - - - - - - - -
HSPI1 O O - - - - - - - - - - -
Backup registers Y Y Y - Y - Y - Y - Y - Y
BOR (Brownout
Y Y Y Y Y Y Y Y Y Y - - -
reset)
PVD (programmable
O O O O O O - - - - - - -
voltage detector)
Peripheral voltage
O O O O O O - - - - - - -
monitor
GPDMA1 O O O O(8) - - - - - - - - -
LPDMA1 O O O O(9) O O(9) - - - - - - -
DMA2D O O
HSI16 (high-speed (10) (10)
O O - - - - - - - - -
internal)
HSI48 oscillator O O - - -
- - - - - - - -
HSE (high-speed
O O - - - - - - - - - - -
external)
LSI (low-speed
O O O - O - O - O - - - O
internal)
LSE (low-speed
O O O - O - O - O - O - O
external)
MSIS and MSIK (10) (10)
O O - - - - - - - - -
(multi-speed internal)
CSS (clock security
O O - - - - - - - - - - -
system)
DS13543 Rev 2 45/390

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Table 10. Functionalities depending on the working mode(1) (continued)

capability
capability
capability
capability
capability
Wake-up
Wake-up
Wake-up
Wake-up
Wake-up
- - - - -
Clock security
O O O O O O O O O O O O O
system on LSE
Backup domain
voltage and
O O O O O O O O O O O O O
temperature
monitoring
RTC/TAMP O O O O O O O O O O O O O
Number of RTC
8 8 8 O 8 O 8 O 8 O 8 O 8
tamper pins
OTG_HS, UCPD O(11) O(11) - O(12) - - - - - - - - -
USARTx
O O O(13) O(13) - - - - - - - - -
(x=1,2,3,4,5,6)
Low-power UART
O O O(13) O(13) O(13) O(13) - - - - - - -
(LPUART1)
I2Cx (x = 1,2,4,5,6) O O O(14) O(14) - - - - - - - - -
I2C3 O O O(14) O (14) O(14) O(14) - - - - - - -
SPIx (x = 1,2) O O O(15) O(15) - - - - - - - - -
(15) O(15) O(15) O(15)
SPI3 O O O
FDCAN1 O O - - - - - - - - - - -
SDMMCx (x = 1,2) O O - - - - - - - - - - -
SAIx (x = 1,2) O O - - - - - - - - - - -
ADCx (x = 1,2) O O - - - - - - - - - - -
ADC4 O O O(16) O(16) O(16) O(16) - - - - - - -
DAC1 (2 converters) O O O - O - - - - - - - -
VREFBUF O O O - O - - - - - - - -
OPAMPx (x = 1,2) O O O - O - - - - - - - -
COMPx (x = 1,2) O O O O O O - - - - - - -
Temperature sensor O O O - O - - - - - - - -
Timers (TIMx) O O - - - - - - - - - - -
LPTIMx (x = 1,3,4) O O O(17) O(17) O(17) O(17) - - - - - - -
LPTIM2 O O O(17) O(17) - - - - - - - - -
IWDG (independent
O O O O O O O O O O - - -
watchdog)
46/390 DS13543 Rev 2

Table 10. Functionalities depending on the working mode(1) (continued)

capability
capability
capability
capability
capability
Wake-up
Wake-up
Wake-up
Wake-up
Wake-up
- - - - -
WWDG (window
O O - - - - - - - - - - -
watchdog)
SysTick timer O O - - - - - - - - - - -
MDF1 (multi-function
O O O(18) O(18) - - - - - - - - -
digital filter)
ADF1 (audio digital
O O O(18) O(18) O(18) O(18) - - - - - - -
filter)
LTDC O O - - - - - - - - - - -
DSI O O - - - - - - - - - - -
GFXMMU O O - - - - - - - - - - -
GPU2D O O - - - - - - - - - - -
DCMI (digital camera
O O - - - - - - - - - - -
interface)
PSSI (parallel
synchronous slave O O
interface)
CORDIC
O O - - - - - - - - - - -
coprocessor
FMAC (filter
mathematical O O - - - - - - - - - - -
accelerator)
TSC (touch sensing
O O - - - - - - - - - - -
controller)
RNG (true random
O O - - - - - - - - - - -
number generator)
AES and secure AES O O - - - - - - - - - - -
PKA (public key
O O - - - - - - - - - - -
accelerator)
OTFDEC (on-the-fly
O O - - - - - - - - - - -
decryption)
HASH accelerator O O - - - - - - - - - - -
CRC calculation unit O O - - - - - - - - - - -
- 24 - 24 - 24
GPIOs O O O O O O (19) (19) (20) -
pins pins pins
1. Y = yes (enabled). O = optional (disabled by default, can be enabled by software). - = not available.
Gray cells highlight the wake-up capability in each mode.
2. The flash memory can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAMs can be powered on or off independently.
4. The SRAM clock can be gated on or off independently.
5. ECC error interrupt or NMI wake-up from Stop mode.
DS13543 Rev 2 47/390

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6. 8-Kbyte, 56-Kbyte or full SRAM2 content can be preserved.

7. Sub-blocks or full SRAM1, SRAM3, and SRAM5, full SRAM2 and SRAM4 can be powered-off to save power consumption.
SRAM1, SRAM2, SRAM3, SRAM4, and SRAM5 can be accessed by GPDMA1 in Stop 0 and Stop 1 modes. SRAM4 can be
accessed by LPDMA1 in Stop 0, Stop 1 and Stop 2 modes.
8. GPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.
9. LPDMA transfers are functional and autonomous in Stop mode, and generates a wake-up interrupt on transfer events.
10. Some peripherals with autonomous mode and wake-up from Stop capability can request HSI16, MSIS or MSIK to be
enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
11. OTG_HS is functional in voltage scaling range 1 and 2.
12. OTG_HS cannot wake up from Stop mode 1.
13. USART and LPUART reception and transmission are functional and autonomous in Stop mode in asynchronous and in SPI
master modes, and generate a wake-up interrupt on transfer events.
14. I2C reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt on transfer
events.
15. SPI reception and transmission are functional and autonomous in Stop mode, and generate a wake-up interrupt on transfer
events.
16. A/D conversion is functional and autonomous in Stop mode, and generates a wake-up interrupt on conversion events.
17. LPTIM is functional and autonomous in Stop mode, and generates a wake-up interrupt on events.
18. MDF and ADF are functional and autonomous in Stop mode, and generate a wake-up interrupt on events.
19. I/Os can be configured with internal pull-up, pull-down or floating in Stop 3 and Standby modes.
20. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.4 Reset mode

In order to improve the consumption under reset, the I/O state under and after reset is
“analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.5 VBAT operation

The VBAT pin allows the device VBAT domain to be powered from an external battery or
an external super-capacitor.
The VBAT pin supplies the RTC with LSE, anti-tamper detection (TAMP), backup registers
and 2-Kbyte backup SRAM. Eight anti-tamper detection pins are available in VBAT mode.
The VBAT operation is automatically activated when VDD is not present. An internal
VBAT battery charging circuit is embedded and can be activated when VDD is present.
Note: When the microcontroller is supplied from VBAT, neither external interrupts nor RTC/TAMP
alarm/events exit the microcontroller from the VBAT operation.
3.9.6 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit, the PWR is switched in
TrustZone security mode.
The PWR TrustZone security secures the following configuration:
• low-power mode
• WKUP (wake-up) pins
• voltage detection and monitoring
• VBAT mode
48/390 DS13543 Rev 2

Some of the PWR configuration bits security is defined by the security of other peripherals:
• The VOS (voltage scaling) configuration is secure when the system clock selection is
secure in RCC.
• The I/O pull-up/pull-down in Standby mode configuration is secure when the
corresponding GPIO is secure.
3.10 Peripheral interconnect matrix

Several peripherals have direct connections between them, that allow autonomous
communication between them and support the saving of CPU resources (thus power supply
consumption). In addition, these hardware connections allow fast and predictable latency.
Depending on the peripherals, these interconnections can operate in Run, Sleep, Stop 0,
Stop 1, and Stop 2 modes.
3.11 Reset and clock controller (RCC)

The RCC manages the different reset types, and generates all clocks for the bus and
peripherals.
The RCC distributes the clocks coming from the different oscillators to the core and to
the peripherals. It also manages the clock gating for low-power modes and ensures the
clock robustness. It features:
• Clock prescaler: in order to get the best trade-off between speed and current
consumption, the clock frequency to the CPU and peripherals can be adjusted by
a programmable prescaler.
• Clock security system: clock sources can be changed safely on-the-fly in Run mode
through a configuration register.
• Clock management: in order to reduce the power consumption, the clock controller
can stop the clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– HSE (4 to 50 MHz high-speed external crystal or ceramic resonator) that can
supply a PLL. The HSE can also be configured in bypass mode for an external
clock.
– HSI16 (16 MHz high-speed internal RC oscillator) trimmable by software, that can
supply a PLL.
– MSI (multispeed internal RC oscillator) trimmable by software, that can generate
16 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
– System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 160 MHz.
• HSI48 (RC48 with clock recovery system) internal 48 MHz clock source that can be
used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output
on the MCO.
• UCPD kernel clock, derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior to the UCPD kernel clock use.
DS13543 Rev 2 49/390

99
• Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the real-time clock:
– LSE (32.768 kHz low-speed external crystal), supporting three drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– LSI (32 kHz low-speed internal RC), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy. The LSI clock can be divided by 128 to
output a 250 Hz as source clock.
• Peripheral clock sources: several peripherals have their own independent clock
whatever the system clock. Three PLLs, each having three independent outputs
allowing the highest flexibility, can generate independent clocks for the ADC, USB,
SDMMC, RNG, MDF, ADF, FDCAN1, OCTOSPIs, HSPI, LTDC, DSI and SAIs.
• Startup clock: after reset, the microcontroller restarts by default with MSI. The prescaler
ratio and clock source can be changed by the application program as soon as the code
execution starts.
• CSS (clock security system): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock automatically switches to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and generates
an interrupt.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
(except VBAT mode).
Several prescalers allow AHB and APB frequencies configuration. The maximum frequency
of the AHB and the APB clock domains is 160 MHz.
50/390 DS13543 Rev 2

Figure 5. Clock tree

LSI RC
LSCO 32 kHz or 128 Hz LSI To IWDG
LSE OSC HSI16

To UCPD1
OSC32_OUT 32.768 kHz
To RTC
Clock LSI
detector LSE
OSC32_IN /32 MSIK x2
HSI16 To LPTIM1, LPTIM3, LPTIM4
LSE
LSI To PWR
MSIS To AHB bus, core, memory and DMA
MCO HSI16
ĺ HSE
SYSCLK AHB HCLK FCLK Cortex free running clock
PRESC
pll1_r_ck / 1,2,..512 LSE
HSI48 LSI To Cortex system timer
MSIK /8
Clock
source
OSC_OUT HSE OSC control APB1 PCLK1
4-50 MHz PRESC
HSE To APB1 peripherals
/ 1,2,4,8,16
OSC_IN Clock
detector x1 or x2
SYSCLK To TIMx
(x = 2 to 7)
HSI RC 16 MHz HSI16 LSE
HSI16 x6
To USARTx
SYSCLK
(x = 2 to 6)
MSI RC MSIS
MSIS 100 kHz – 48 MHz MSIK
MSIK HSI16 To SPI2
MSIK 100 kHz – 48 MHz
SYSCLK
HSI48
HSI48 RC 48 MHz HSI16 x6
SYSCLK To I2Cx
MSIK (x = 1,2,4,5,6)
MSIS
PLL1 /M HSI16
pll1_p_ck HSE LSI
VCO /P LSE To LPTIM2
pll1_q_ck HSI16
/Q
pll1_r_ck HSE
/N /R pll1_q_ck
pll2_p_ck To FDCAN1
MSIS SYSCLK CRS clock

PLL2 /M HSI16
HSE MSIK
pll2_p_ck pll1_q_ck
VCO /P To OCTOSPIx
pll2_q_ck pll2_q_ck (X = 1,2)
/Q
pll2_r_ck PCLK2 To SAES
/N /R
APB2
PRESC
To APB2 peripherals
/ 1,2,4,8,16
MSIS x1 or x2
PLL3 /M HSI16 To TIMx
pll3_p_ck HSE (x = 1,8,15,16,17)
VCO /P
pll3_q_ck
/Q
pll3_r_ck LSE
/N /R HSI16 To USART1
SYSCLK
SHSI RC MSIK
/2 HSI16
SYSCLK To SPI1
pll1_p_ck
pll3_q_ck x2
MSIK To ADF1 and MDF1
AUDIOCLK
pll1_p_ck
pll2_p_ck x2
pll3_p_ck To SAIx
pll1_p_ck HSI16 (X = 1,2)
MSIK To SDMMCx
HSI48 ICLK (X = 1,2)
pll1_q_ck
pll2_q_ck
HSI16
/2
To RNG
PCLK3
SYSCLK APB3
pll1_q_ck PRESC To APB3 peripherals
pll2_q_ck To HSPI / 1,2,4,8,16
pll3_r_ck
MSIK To I2C3
pll2_r_ck HSI16
pll3_r_ck To LTDC
MSIK To SPI3
pll3_p_ck HSI16
DSI PHY To DSI
HSE
PLL
MSIK
HSI16 To LPUART1
HSE LSE
pll1_p_ck OTG_HS
pll2_r_ck
HSE / 2 PHY PLL To OTG_HS
pll1_p_ck / 2 HSE To ADC1, ADC2,
HSI16 LSI ADC4 and DAC1
MSIK
LSE
DAC1 sample and hold clock
MSv65077V1
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3.11.1 RCC TrustZone security

When the TrustZone security is activated by the TZEN option bit, the RCC is switched in
TrustZone security mode.
The RCC TrustZone security secures some RCC system configuration and peripheral
configuration clock from being read or modified by nonsecure accesses: when a peripheral
is secure, the related peripheral clock, reset, clock source selection and clock enable during
low-power modes control bits are secure.
A peripheral is in secure state:
• when its corresponding SEC security bit is set in the TZSC (TrustZone security
controller), for securable peripherals.
• when a security feature of this peripheral is enabled through its dedicated bits, for
TrustZone-aware peripherals.
3.12 Clock recovery system (CRS)

The devices embed a special block that allows automatic trimming of the internal 48 MHz
oscillator to guarantee its optimal accuracy over the whole device operational range. This
automatic trimming is based on the external synchronization signal, that is either derived
from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user
software. For faster lock-in during startup, automatic trimming and manual trimming action
can be combined.
3.13 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13.1 GPIOs TrustZone security

Each I/O pin of GPIO port can be individually configured as secure. When the selected I/O
pin is configured as secure, its corresponding configuration bits for alternate function, mode
selection, I/O data are secure against a nonsecure access. The associated registers bit
access is restricted to a secure software only. After reset, all GPIO ports are secure.
3.14 Low-power general-purpose inputs/outputs (LPGPIO)

The LPGPIO allows dynamic I/O control in Stop 2 mode thanks to LPDMA1. Up to 16 I/Os
can be configured and controlled as input or output (open-drain or push-pull depending on
GPIO configuration).
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3.14.1 LPGPIO TrustZone security

Each I/O pin registers bit of the LPGPIO is configured as secure if the corresponding I/O is
configured as secure in the GPIO.
3.15 Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all the master (CPU, DMA2D, GFXMMU,
GPDMA1, GPU2D, LTDC, OTG_HS, SDMMC1, SDMMC2) and the slave (flash memory,
FMC, HSPI, OCTOSPIs, SRAMs, AHB and APB) peripherals. It also ensures a seamless
and efficient operation even when several high-speed peripherals work simultaneously.
Another multi-AHB bus matrix interconnects two masters (previous AHB bus matrix slave
port and LPDMA1) and all slaves that are functional in Stop 2 modes (SRAM4 and
AHB/APB peripherals functional in Stop 2 mode).
3.16 System configuration controller (SYSCFG)

The STM32U5Axxx devices feature a set of configuration registers. The main purposes of
the system configuration controller are the following:
• Managing robustness feature
• Configuring FPU interrupts
• Enabling/disabling the FMP high-drive mode of some I/Os and voltage booster for I/Os
analog switches
• Managing the I/O compensation cell
• Configuring register security access
• Configuring the OTG_HS PHY
• Adjust the HSPI supply capacitance
• Disable internal SRAMs cacheability by DCACHE2
3.17 General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system
peripheral.
The GPDMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.
The GPDMA main features are:
• Dual bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
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• Transfers arbitration based on a four-grade programmed priority at a channel level:

– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
• Per channel event generation, on any of the following events: transfer complete or half
transfer complete or data transfer error or user setting error, and/or update linked-list
item error or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable
per event
• 16 concurrent DMA channels:
– Per channel FIFO for queuing source and destination transfers
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
reordering, packing or unpacking, padding or truncation, sign extension and
left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– 12 channels with linear source and destination addressing: either fixed or
contiguously incremented addressing, programmed at a block level, between
successive single transfers
– Four channels with 2D source and destination addressing: programmable signed
address offsets between successive burst transfers (non-contiguous addressing
within a block, combined with programmable signed address offsets between
successive blocks, at a second 2D/repeated block level)
– Support for scatter-gather (multi-buffer transfers), data interleaving and
deinterleaving via 2D addressing
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting including FIFO level and event flags
• TrustZone support:
– Support for secure and nonsecure DMA transfers, independently at a first channel
level, and independently at a source/destination and link sub-levels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a nonsecure access
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• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at
channel level
– Privileged-aware AHB slave port.
Table 11. GPDMA1 channels implementation and usage

Hardware parameters
Channel x Features
dma_fifo_ dma_
size[x] addressing[x]
Channel x (x = 0 to 11) is implemented with:

– a FIFO of 8 bytes, 2 words
x = 0 to 11 2 0 – fixed/contiguously incremented addressing
These channels may be also used for GPDMA transfers,
between an APB or AHB peripheral and SRAM.
– a FIFO of 32 bytes, 8 words
x = 12 to 15 4 1 – 2D addressing
These channels may be also used for GPDMA transfers,
between a demanding AHB peripheral and SRAM, or for
transfers from/to external memories.
Table 12. GPDMA1 autonomous mode and wake-up in low-power modes

Feature Low-power modes
Autonomous mode and wake-up GPDMA1 in Sleep, Stop 0 and Stop 1 modes
3.18 Low-power direct memory access controller (LPDMA)

The LPDMA controller is a bus master and system peripheral. The LPDMA is used to
perform programmable data transfers between memory-mapped peripherals and/or
memories via linked-lists, upon the control of an off-loaded CPU.
The LPDMA main features are:
• Single bidirectional AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Transfers arbitration based on a 4-grade programmed priority at channel level:
– One high-priority traffic class, for time-sensitive channels (queue 3)
– Three low-priority traffic classes, with a weighted round-robin allocation for non
time-sensitive channels (queues 0, 1, 2)
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• Per channel event generation, on any of the following events: transfer complete, or
half-transfer complete, or data transfer error, or user setting error, and/or update
linked-list item error, or completed suspension
• Per channel interrupt generation, with separately programmed interrupt enable
per event
• Four concurrent DMA channels:
– Intra-channel DMA transfers chaining via programmable linked-list into memory,
supporting two execution modes: run-to-completion and link step mode
– Intra-channel and inter-channel DMA transfers chaining via programmable DMA
input triggers connection to DMA task completion events
• Per linked-list item within a channel:
– Separately programmed source and destination transfers
– Programmable data handling between source and destination: byte-based
padding or truncation, sign extension and left/right realignment
– Programmable number of data bytes to be transferred from the source, defining
the block level
– Linear source and destination addressing: either fixed or contiguously
incremented addressing, programmed at a block level, between successive
single transfers
– Programmable DMA request and trigger selection
– Programmable DMA half-transfer and transfer complete events generation
– Pointer to the next linked-list item and its data structure in memory, with automatic
update of the DMA linked-list control registers
• Debug:
– Channel suspend and resume support
– Channel status reporting and event flags
• TrustZone support
– Support for secure and nonsecure DMA transfers, independently at a first channel
level, and independently at a source/destination and link sub-levels
– Secure and nonsecure interrupts reporting, resulting from any of the respectively
secure and nonsecure channels
– TrustZone-aware AHB slave port, protecting any DMA secure resource (register,
register field) from a nonsecure access
• Privileged/unprivileged support:
– Support for privileged and unprivileged DMA transfers, independently at
channel level
– Privileged-aware AHB slave port.
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Table 13.LPDMA1 channels implementation and usage

Hardware parameters
Channel
Features
x dma_fifo_ dma_
size[x] addressing[x]

– no FIFO. Only a single source transfer cell is
x = 0 to 3 0 0
internally registered.
– fixed/contiguously incremented addressing
Table 14. LPDMA1 autonomous mode and wake-up in low-power modes

Feature Low-power modes
Autonomous mode and wake-up LPDMA1 in Sleep, Stop 0, Stop 1 and Stop 2 modes
3.19 Neo-Chrom GPU (GPU2D)

The Neo-Chrom GPU is accelerating operations for graphic effects like rotation, scaling, and
perspective correct texture mapping (2.5D). It works together with an optimized software
stack designed for state of the art graphic rendering.
The GPU2D main features are:
• Multi-threaded fragment (pixel) processing core with a VLIW (very-long instruction
word) instruction set
• Fixed point functional units
• Command list based DMAs to minimize CPU overhead
• Two 32-bit AHB master interfaces for texture, command list and framebuffer access
• 32-bit AHB slave interface for register bank access
• Up to 4 general-purpose flags for system-level synchronization
• Texture decompression unit with TSC™4 and TSC™6/TSC™6a support
The GPU2D also features:
• 2D drawing
– Pixel/line drawing
– Filled rectangles
– Triangles, quadrilateral drawing
– Anti-aliasing 8xMSAA (multi-sample anti-aliasing)
• Image transformations
– 3D perspective correct projections
– Texture mapping with bilinear filtering or point sampling
• Blit support
– Rotation, mirroring, stretching (independently on x and y axis)
– Source and/or destination color keying
– Pixel format conversions
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• Text rendering support

– A1, A2, A4 and A8 bitmap anti-aliased
– Subsampled anti-aliased
• Color formats
– RGB, grayscale
– 32, 24, 16 and 8 bits with/without alpha
• Full alpha blending with hardware blender
– Programmable blending modes
– Source/destination color keying
3.20 Chrom-ART Accelerator controller (DMA2D)

The Chrom-ART Accelerator (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
• Filling a part or the whole of a destination image with a specific color
• Copying a part or the whole of a source image into a part or the whole of a destination
image
• Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
• Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format.
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with
indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color
look-up tables).
The main DMA2D features are:
• Single AHB master bus architecture
• AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT
accesses that are 32-bit)
• User programmable working area size
• User programmable offset for sources and destination areas expressed in pixels or
bytes expressed in pixels or bytes
• User programmable sources and destination addresses on the whole memory space
• Up to two sources with blending operation
• Alpha value can be modified (source value, fixed value or modulated value)
• User programmable source and destination color format
• Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
• Two internal memories for CLUT storage in indirect color mode
• Automatic CLUT loading or CLUT programming via the CPU
• User programmable CLUT size
• Internal timer to control AHB bandwidth
• Six operating modes: register-to-memory, memory-to-memory, memory-to-memory
with pixel format conversion, memory-to-memory with pixel format conversion and
blending, memory-to memory with pixel format conversion, blending and fixed color
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foreground, and memory-to memory with pixel format conversion, blending and fixed
color background
• Area filling with a fixed color
• Copy from an area to another
• Copy with pixel format conversion between source and destination images
• Copy from two sources with independent color format and blending
• Output buffer byte swapping to support refresh of displays through parallel interface
• Abort and suspend of DMA2D operations
• Watermark interrupt on a user programmable destination line
• Interrupt generation on bus error or access conflict
• Interrupt generation on process completion
3.21 Chrom-GRC (GFXMMU)

The GFXMMU is a graphical oriented memory management unit aimed to:
• Optimize memory usage according to the display shape
• Cache linear accesses to the frame buffer
• Prefetch data
The GFXMMU main features are:
• Fully programmable display shape to physically store only the visible pixel
• Up to 4 virtual buffers
• Each virtual buffer have 3072 or 4096 bytes per line and 1024 lines
• Each virtual buffer can be physically mapped to any system memory
• Optional cache for linear accesses
• Cache can be locked to a virtual buffer
• Cache prefetch mechanism for linear accesses anticipation
• Interrupt in case of buffer overflow (1 per buffer)
• Interrupt in case of memory transfer error
3.22 Interrupts and events
3.22.1 Nested vectored interrupt controller (NVIC)

The devices embed a NVIC that is able to manage 16 priority levels and to handle up to 138
maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.
The NVIC benefits are the following:
• closely coupled NVIC giving low-latency interrupt processing
• interrupt entry vector table address passed directly to the core
• early processing of interrupts
• processing of late arriving higher priority interrupts
• support for tail chaining
• processor state automatically saved
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• interrupt entry restored on interrupt exit with no instruction overhead

• TrustZone support: NVIC registers banked across secure and nonsecure states
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.22.2 Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wake-up through configurable event
inputs. It provides wake-up requests to the power control, and generates an interrupt
request to the CPU NVIC and events to the CPU event input. For the CPU an additional
event generation block (EVG) is needed to generate the CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can also be used in Run modes.
The EXTI also includes the EXTI multiplexer I/O port selection.
The EXTI main features are the following:
• All event inputs allowed to wake up the system
• Configurable events (signals from I/Os or peripherals able to generate a pulse)
– Selectable active trigger edge
– Interrupt pending status register bit independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wake-up, interrupt and event generation
– Software trigger possibility
• TrustZone secure events
– The access to control and configuration bits of secure input events can be made
secure
• EXTI I/O port selection
3.23 Cyclic redundancy check calculation unit (CRC)

The CRC is used to get a CRC code using a configurable generator with polynomial value
and size.
Among other applications, the CRC-based techniques are used to verify data transmission
or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify
the flash memory integrity.
The CRC calculation unit helps to compute a signature of the software during runtime, that
can be ulteriorly compared with a reference signature generated at link-time and that can be
stored at a given memory location.
3.24 CORDIC co-processor (CORDIC)

The CORDIC co-processor provides hardware acceleration of certain mathematical
functions, notably trigonometric, commonly used in motor control, metering, signal
processing and many other applications. It speeds up the calculation of these functions
compared to a software implementation, allowing a lower operating frequency, or freeing up
processor cycles in order to perform other tasks.
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The CORDIC main features are:

• 24-bit CORDIC rotation engine
• Circular and hyperbolic modes
• Rotation and vectoring modes
• Functions: sine, cosine, sinh, cosh, atan, atan2, atanh, modulus, square root,
natural logarithm
• Programmable precision
• Low-latency AHB slave interface
• Results can be read as soon as ready without polling or interrupt
• DMA read and write channels
• Multiple register read/write by DMA
3.25 Filter math accelerator (FMAC)

The FMAC performs arithmetic operations on vectors. It comprises a MAC
(multiplier/accumulator) unit, together with address generation logic that allows it to index
vector elements held in local memory.
The unit includes support for circular buffers on input and output, that allows digital filters to
be implemented. Both finite and infinite impulse response filters can be done.
The unit allows frequent or lengthy filtering operations to be offloaded from the CPU, freeing
up the processor for other tasks. In many cases it can accelerate such calculations
compared to a software implementation, resulting in a speed-up of time critical tasks.
The FMAC main features are:
• 16 x 16-bit multiplier
• 24 + 2-bit accumulator with addition and subtraction
• 16-bit input and output data
• 256 x 16-bit local memory
• Up to three areas can be defined in memory for data buffers (two input, one output),
defined by programmable base address pointers and associated size registers
• Input and output buffers can be circular
• Filter functions: FIR, IIR (direct form 1)
• Vector functions: dot product, convolution, correlation
• AHB slave interface
• DMA read and write data channels
3.26 Flexible static memory controller (FSMC)

The FSMC includes two memory controllers:
• NOR/PSRAM memory controller
• NAND/memory controller
The FSMC is also named flexible memory controller (FMC).
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The main features of the FSMC are the following:

• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR flash memory/OneNAND flash memory
– PSRAM (four memory banks)
– NAND flash memory with ECC hardware to check up to 8 Kbytes of data
– Ferroelectric RAM (FRAM)
• 8-,16- bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
3.26.1 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.
3.26.2 FSMC TrustZone security

When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Nonsecure area can be configured using the TZSC MPCWMx controller:
• FSMC NOR/PSRAM bank:
– Up to two nonsecure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
• FSMC NAND bank:
– Can be either configured as fully secure or fully nonsecure using the TZSC
MPCWM3 controller
The FSMC registers can be configured as secure through the TZSC controller.
3.27 Octo-SPI interface (OCTOSPI)

The devices embed two OCTOSPIs. The OCTOSPI supports most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAMs™ and
HyperFlash™ memories, with the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Status-polling mode: the external memory status register is periodically read and
an interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
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The OCTOSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus™ frame format
The OCTOSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Supports for single, dual, quad and octal communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad memories in parallel.
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
3.27.1 OCTOSPI TrustZone security

When the TrustZone security is enabled, the whole OCTOSPI bank is secure after reset.
Up to two nonsecure area can be configured thought the TZSC MPCWM1 and MPCWM5
controllers with a granularity of 64 Kbytes.
The OCTOSPI registers can be configured as secure through the TZSC controller.
3.28 OCTOSPI I/O manager (OCTOSPIM)

The OCTOSPI I/O manager is a low-level interface enabling:
• efficient OCTOSPI pin assignment with a full I/O matrix (before alternate function map)
• multiplex of Single-, Dual-, Quad-, Octal-SPI interfaces over the same bus and hence
support memories embedded in a multichip package
The OCTOSPIM main features are:
• Supports up to two Single-, Dual-, Quad-, Octal-SPI interfaces
• Supports up to two ports for pin assignment
• Fully programmable I/O matrix for pin assignment by function (data/control/clock)
3.29 Delay block (DLYB)

The delay block (DLYB) is used to generate an output clock that is dephased from the input
clock. The phase of the output clock must be programmed by the user application. The
output clock is then used to clock the data received by another peripheral such as
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a SDMMC or Octo-SPI interface. The delay is voltage and temperature dependent, that may
require the application to re-configure and recenter the output clock phase with the received
data.
The delay block main features are:
• Input clock frequency ranging from 25 to 160 MHz
• Up to 12 oversampling phases
3.30 Hexadeca-SPI interface (HSPI)

The HSPI supports most external serial memories such as serial PSRAMs, serial NAND and
serial NOR Flash memories, HyperRAMs and HyperFlash memories, with the following
functional modes:
• Indirect mode: all the operations are performed using the HSPI registers.
• Status polling mode: the external memory status register is periodically read and an
interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.
The HSPI supports the following protocols with associated frame formats:
• the standard frame format with the command, address, alternate byte, dummy cycles
and data phase
• the HyperBus frame format
The HSPI offers the following features:
• Three functional modes: Indirect, Status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• Support for single, dual, quad, octal and hexadeca communication
• Dual-quad mode, where eight bits can be sent/received simultaneously by accessing
two quad or two octal memories in parallel
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• Support wrapped-type access to memory in read direction
• HyperBus support
• Integrated FIFO for reception and transmission
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
• High-speed interface up to 160MHz
3.30.1 HSPI TrustZone security

When the TrustZone security is enabled, the whole HSPI bank is secure after reset.
Up to two nonsecure areas can be configured thought the TZSC MPCWM6 controller with a
granularity of 64 Kbytes.
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The HSPI registers can be configured as secure through the TZSC controller.
3.31 Analog-to-digital converters (ADC1, ADC2, and ADC4)

The devices embed three successive approximation analog-to-digital converters.
Table 15. ADC features

(1)
ADC modes/features ADC1 ADC2 ADC4
Resolution 14 bits 12 bits

Maximum sampling speed for maximum
2.5 Msps
resolution
Hardware offset calibration X
Hardware linearity calibration X -
Single-ended inputs X
Differential inputs X -
Injected channel conversion X -
Oversampling up to x1024 up to x256
Data register 32 bits 16 bits
DMA support X
Parallel data output to MDF X -
Dual mode X -
Autonomous mode - X
Offset compensation X -
Gain compensation X -
Number of analog watchdogs 3
Wake-up from Stop mode - X(2)
1. X = supported.
2. wake-up supported from Stop 0, Stop 1 and Stop 2 modes.
3.31.1 Analog-to-digital converters (ADC1/2)

The ADC1/2 are 14-bit ADC successive approximation analog-to-digital converters.
Each ADC has up to 20 multiplexed channels. A/D conversion of the various channels can
be performed in Single, Continuous, Scan or Discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 32-bit data register.
The ADC1/2 are mapped on the AHB bus to allow fast data handling. The analog watchdog
features allow the application to detect if the input voltage goes outside the user-defined
high or low thresholds.
A built-in hardware over sampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
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An efficient low-power mode is implemented to allow very low consumption at low

frequency.
The ADC1/2 main features are:
• High-performance features
– Dual mode operation
– 14-, 12-, 10- or 8-bit configurable resolution
– A/D conversion time independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Management of single-ended or differential inputs (programmable per channels)
– Fast data handling thanks to the AHB slave bus interface
– Self-calibration (both offset and linearity)
– Channel-wise programmable sampling time
– Flexible sampling time control
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Fast context switching thanks to the hardware assistant that prepares the context
of the injected channels
– Data alignment with in-built data coherency
– Data can be managed by GPDMA for regular channel conversions with FIFO
– Data can be routed to MDF for post processing
– Four dedicated data registers for the injected channels
• Oversampler
– 32-bit data register
– Oversampling ratio adjustable from 2 to 1024
– Programmable data right and left shift
• Data preconditioning
– Gain compensation
– Offset compensation
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Slow bus frequency application while keeping optimum ADC performance
– Automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)
• ADC features an external analog input channel:
– Up to 17 channels from dedicated GPIO pads
• Three additional internal dedicated channels:
– One channel for internal reference voltage (VREFINT)
– One channel for internal temperature sensor (VSENSE)
– One channel for VBAT monitoring channel (VBAT/4)
• Start-of-conversion can be initiated:
– by software for both regular and injected conversions
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– by hardware triggers with configurable polarity (internal timers events or GPIO

input events) for both regular and injected conversions
• Conversion modes
– Single mode: the ADC converts a single channel. The conversion is triggered by
a special event.
– Scan mode: the ADC scans and converts a sequence of channels.
– Continuous mode: the ADC converts continuously selected inputs.
– Discontinuous mode: the ADC converts a subset of the conversion sequence.
• Interrupt generation when the ADC is ready, at end of sampling, end of conversion
(regular or injected), end of sequence conversion (regular or injected), analog
watchdog 1, 2 or 3 or when an overrun event occurs
• Three analog watchdogs
– Filtering to ignore out-of-range data
• ADC input range: VSSA < VIN < VREF+
Note: The ADC1/2 analog block clock frequency must be between 5 MHz and 55 MHz.
3.31.2 Analog-to-digital converter 4 (ADC4)

The 12-bit ADC4 is a successive approximation analog-to-digital converter. It has up to
25 multiplexed channels allowing it to measure signals from 19 external and six internal
sources. A/D conversion of the various channels can be performed in Single, Continuous,
Scan or Discontinuous mode. The result of the ADC is stored in a left-aligned or
right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency. The ADC4 is autonomous in low-power modes down to Stop 2 mode.
A built-in hardware oversampler allows analog performances to be improved while
off-loading the related computational burden from the CPU.
The ADC4 main features are:
• High performance
– 12-, 10-, 8- or 6-bit configurable resolution
– A/D conversion time: 0.4 µs for 12-bit resolution (2.5 MHz), faster conversion
times obtained by lowering resolution
– Self-calibration
– Programmable sampling time
– Data alignment with built-in data coherency
– DMA support
• Low-power
– HCLK frequency reduced for low-power operation while still keeping optimum
ADC performance
– Wait mode: ADC overrun prevented in applications with low frequency HCLK
– Auto-off mode: ADC automatically powered off except during the active
conversion phase, dramatically reducing the ADC power consumption
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– Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is

automatically switched on when a trigger occurs to start conversion, and it is
automatically switched off after conversion. Data are transfered in SRAM
with DMA.
– ADC4 interrupts wake up the device from Stop 0, Stop 1 and Stop 2 modes.
• Analog input channels
– Up to 19 external analog inputs
– One channel for the internal temperature sensor (VSENSE)
– One channel for the internal reference voltage (VREFINT)
– One channel for the internal digital core voltage (VCORE)
– One channel for monitoring the external VBAT power supply pin
– Connection to two DAC internal channels
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events or GPIO input
events)
• Conversion modes
– Conversion of a single channel or scan of a sequence of channels
– Selected inputs converted once per trigger in Single mode
– Selected inputs converted continuously in Continuous mode
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events, with wake-up from Stop
capability
• Analog watchdog
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256
– Programmable data shift up to 8 bits
• ADC supply requirements: 1.62 to 3.6 V
• ADC input range: VSSA <VIN < VREF+
Note: The ADC4 analog block clock frequency must be between 140 kHz and 55 MHz.
3.31.3 Temperature sensor

The temperature sensor generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to ADC1, ADC2 and ADC4 input channel
that is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it must be calibrated to obtain a good accuracy of the
temperature measurement. As the offset of the temperature sensor varies from chip to chip
due to process variation, the uncalibrated internal temperature sensor is suitable for
applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by STMicroelectronics in the system memory area, accessible in read-only mode.
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Table 16. Temperature sensor calibration values

Calibration
Description Memory address
value name
Temperature sensor 14-bit raw data acquired by ADC1

TS_CAL1 0x0BFA 0710 - 0x0BFA 0711
at 30 °C (± 5 °C), VDDA = VREF+ = 3.0 V (± 10 mV)
Temperature sensor 14-bit raw data acquired by ADC1
TS_CAL2 0x0BFA 0742 - 0x0BFA 0743
3.31.4 Internal voltage reference (VREFINT)

The VREFINT provides a stable (bandgap) voltage output for the ADC and the comparators.
The VREFINT is internally connected to ADC1, ADC2 and ADC4 input channels.
The precise voltage of VREFINT is individually measured for each part by
STMicroelectronics during production test and stored in the system memory area. It is
accessible in read-only mode.
Table 17. Internal voltage reference calibration values

Calibration value name Description Memory address
14-bit raw data acquired by ADC1

VREFINT_CAL 0x0BFA 07A5 - 0x0BFA 07A6
3.31.5 VBAT battery voltage monitoring

This embedded hardware enables the application to measure the VBAT battery voltage using
ADC1, ADC2 or ADC4 input channel. As the VBAT voltage may be higher than the VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by four. As a consequence, the converted digital value is a quarter of the VBAT
voltage.
3.32 Digital to analog converter (DAC)

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller.
In 12-bit mode, the data may be left- or right-aligned.
The DAC features two output channels, each with its own converter. In dual DAC channel
mode, conversions can be done independently or simultaneously when both channels are
grouped together for synchronous update operations. An input reference pin, VREF+
(shared with others analog peripherals) is available for better resolution. An internal
reference can also be set on the same input.
The DAC_OUTx pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low-power mode, the sample and hold mode.
The digital interface supports the following features:
• One DAC interface, maximum two output channels
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• Left or right data alignment in 12-bit mode

• Synchronized update capability
• Noise-wave and triangular-wave generation
• Sawtooth wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• Double data DMA capability to reduce the bus activity
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DAC_OUTx output pin
• DAC output connection to on chip peripherals
• Sample and hold mode for low-power operation in Stop mode. The DAC voltage can
be changed autonomously with the DMA while the device is in Stop mode.
• Autonomous mode to reduce the power consumption for the system
• Voltage reference input
3.33 Voltage reference buffer (VREFBUF)

The devices embed a voltage reference buffer that can be used as voltage reference for
ADCs, DACs and also as voltage reference for external components through the
VREF+ pin.
Figure 6. VREFBUF block diagram
VREFINT +
VREF+
VSSA
MSv64430V2
The internal voltage reference buffer supports four voltages: 1.5 V, 1.8 V, 2.048 V and 2.5 V.
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
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3.34 Comparators (COMP)

The devices embed two rail-to-rail comparators with programmable reference voltage
(internal or external), hysteresis and speed (low speed for low power) and with selectable
output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4)
All comparators can wake up from Stop 0, Stop 1 and Stop 2 modes, generate interrupts and
breaks for the timers and can also be combined into a window comparator.
3.35 Operational amplifiers (OPAMP)

The devices embed two operational amplifiers with external or internal follower routing and
PGA capability.
The operational amplifier features:
• Low-input bias current
• Low-offset voltage
• Low-power mode
• Rail-to-rail input
3.36 Multi-function digital filter (MDF) and audio digital filter (ADF)
The table below lists the set of features implemented into the MDF and the ADF.
Table 18. MDF features

MDF modes/features(1) ADF1 MDF1
Number of filters (DFLTx) and serial interfaces (SITFx) 1 6
ADF_CKI0 / MDF_CKIy connected to pins - X
Sound activity detection (SAD) X -
RXFIFO depth (number of 24-bit words) 4 4
ADC connected to ADCITF1 - ADC1
ADC connected to ADCITF2 - ADC2
Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break) - X
Main path with CIC4, CIC5 X X
Main path with CIC1,2, 3 or FastSinc - X
RSFLT, HPF, SAT, SCALE, DLY, Discard functions X X
Autonomous in Stop mode X(2) X(3)
1. X = supported.
2. Stop 0, Stop 1 and Stop 2 modes only.
3. Stop 0 and Stop 1 modes only.
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3.36.1 Multi-function digital filter (MDF)

The MDF is a high-performance module dedicated to the connection of external sigma-delta
(Σ∆) modulators. It is mainly targeted for the following applications:
• audio capture signals
• motor control
• metering
The MDF features six digital serial interfaces (SITFx) and digital filters (DFLTx) with flexible
digital processing options to offer up to 24-bit final resolution.
The DFLTx of the MDF also include the filters of the ADF (audio digital filter).
The MDF can receive, via its serial interfaces, streams coming from various digital sensors.
The MDF supports the following standards allowing the connection of various Σ∆ modulator
sensors:
• SPI interface
• Manchester coded 1-wire interface
• PDM interface
A flexible BSMX (bitstream matrix) allows the connection of any incoming bitstream to any
filter.
The MDF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks.In addition it is
possible to insert a high-pass filter or DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio, integrator length. The
maximum output data resolution is up to 24 bits. There are two conversion modes: single
conversion and continuous modes. The data can be automatically stored in a system RAM
buffer through DMA, thus reducing the software overhead.
A flexible trigger interface can be used to control the conversion start. This timing control
can trigger simultaneous conversions or insert a programmable delay between conversions.
The MDF features an OLD (out-off limit detectors) function. There is one OLD for each
digital filter chain. Independent programmable thresholds are available for each OLD,
making it very suitable for over-current detection.
A SCD (short circuit detector) is also available for every selected bitstream. The SCD is able
to detect a short-circuit condition with a very short latency. Independent programmable
thresholds are offered in order to define the short circuit condition.
All the digital processing is performed using only the kernel clock. The MDF requests the
bus interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The MDF main features are:
• AHB interface
• Six serial digital inputs:
– configurable SPI interface to connect various digital sensors
– configurable Manchester coded interface support
– compatible with PDM interface to support digital microphones
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• Two common clock input/output for Σ∆ modulators

• Flexible BSMX for connection between filters and digital inputs
• Two inputs to connect the internal ADCs
• Six flexible digital filter paths, including:
– A configurable CIC filter:
- Can be split into two CIC filters: high-resolution filter and out-off limit detector
- Can be configured in Sinc4 filter
- Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset
– An offset error cancellation
– Gain control
– Saturation blocks
– An out-off limit detector
• Short-circuit detector
• Clock absence detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Break generation on out-of limit or short-circuit detector events
• Autonomous functionality in Stop modes
• DMA can be used to read the conversion data
• Interrupts services
3.36.2 Audio digital filter (ADF)

The ADF is a high-performance module dedicated to the connection of external Σ∆
modulators. It is mainly targeted for the following applications:
• audio capture signals
• metering
The ADF features one digital serial interface (SITF0) and one digital filter (DFLT0) with
flexible digital processing options to offer up to 24-bit final resolution.
The DLFT0 of the ADF is a subset of the digital filters included into the MDF.
The ADF serial interface supports several standards allowing the connection of various Σ∆
modulator sensors:
• SPI interface
• Manchester coded 1-wire interface
• PDM interface
A flexible BSMX allows the connection of any incoming bitstream to any filter.
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The ADF converts an input data stream into clean decimated digital data words. This
conversion is done thanks to low-pass digital filters and decimation blocks. In addition it is
possible to insert a high-pass filter or a DC offset correction block.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, decimation ratio. The maximum output data
resolution is up to 24 bits. There are two conversion modes: single conversion and
continuous modes. The data can be automatically stored in a system RAM buffer through
DMA, thus reducing the software overhead.
A SAD (sound activity detector) is available for the detection of “speech-like” signals. The
SAD is connected at the output of DFLT0. Several parameters can be programmed to adjust
properly the SAD to the sound environment. The SAD can strongly reduce the power
consumption by preventing the storage of samples into the system memory as long as the
observed signal does not match the programmed criteria.
A flexible trigger interface can be used to control the start of conversion of the ADF.
All the digital processing is performed using only the kernel clock. The ADF requests the bus
interface clock (AHB clock) only when data must be transfered or when a specific event
requests the attention of the system processor.
The ADF main features are:
• AHB interface
• One serial digital input:
– Configurable SPI interface to connect various digital sensors
– Configurable Manchester coded interface support
– Compatible with PDM interface to support digital microphones
• Two common clocks input/output for Σ∆ modulators
• Flexible BSMX for connection between filters and digital inputs
• One flexible digital filter path, including:
– A configurable CIC filter:
- Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high-pass filter to cancel the DC offset
– Gain control
– Saturation blocks
• Clock absence detector
• Sound activity detector
• 16- or 24-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Autonomous mode in Stop 0, Stop 1 and Stop 2 modes
• Wake-up from Stop with all interrupts
• DMA can be used to read the conversion data
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• Interrupts services
3.37 Digital camera interface (DCMI)

The DCMI is a synchronous parallel interface able to receive a high-speed data flow from
an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data formats:
YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black and white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing such as resizing is performed in the camera module.
The DCMI features are:
• 8-, 10-, 12- or 14-bit parallel interface
• Embedded/external line and frame synchronization
• Continuous or snapshot mode
• Crop feature
• Supports the following data formats:
– 8/10/12/14-bit progressive video: either monochrome or raw Bayer
– YCbCr 4:2:2 progressive video
– RGB 565 progressive video
– Compressed data: JPEG
3.38 Parallel synchronous slave interface (PSSI)

The PSSI and the DCMI use the same circuitry. As a result, these two peripherals cannot be
used at the same time: when using the PSSI, the DCMI registers cannot be accessed, and
vice versa. In addition, the PSSI and the DCMI share the same alternate functions and the
same interrupt vector.
The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It
enables the transmitter to send a data valid signal that indicates when the data is valid, and
the receiver to output a flow control signal that indicates when it is ready to sample the data.
The PSSI peripheral main features are the following:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 4-word (16-byte) FIFO
• Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate
function output
When selected, these inputs can either enable the transmitter to indicate when the data is
valid, or allow the receiver to indicate when it is ready to sample the data, or both.
3.39 LCD-TFT display controller (LTDC)

The LCD-TFT (liquid crystal display - thin film transistor) display controller provides a
parallel digital RGB (Red, Green, Blue) and signals for horizontal/vertical synchronization,
pixel clock and data enable as output to interface directly to a variety of LCD and TFT
panels.
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The LTDC main features are:

• 24-bit RGB parallel pixel output; 8 bits-per-pixel (RGB888)
• 2 display layers with dedicated FIFO (64x32-bit)
• Color look-up table (CLUT) up to 256 color (256x24-bit) per layer
• Programmable timings for different display panels
• Programmable background color
• Programmable polarity for HSYNC, VSYNC and data enable
• Up to 8 input color formats selectable per layer:
– ARGB8888
– RGB888
– RGB565
– ARGB1555
– ARGB4444
– L8 (8-bit luminance or CLUT)
– AL44 (4-bit alpha + 4-bit luminance)
– AL88 (8-bit alpha + 8-bit luminance)
• Pseudo-random dithering output for low bits per channel
– Dither width 2 bits for Red, Green, Blue
• Flexible blending between two layers using alpha value (per pixel or constant)
• Color keying (transparency color)
• Programmable window position and size
• Supports thin film transistor (TFT) color displays
• AHB master interface with burst of 16 words
• Up to 4 programmable interrupt events
3.40 DSI Host controller (DSI)

The display serial interface (DSI) is part of a group of communication protocols defined by
the MIPI Alliance. The MIPI DSI Host controller is a digital core that implements all protocol
functions defined in the MIPI DSI specification. It provides an interface between the system
(LTDC and APB interface) and the MIPI D-PHY, allowing the user to communicate with a
DSI-compliant display.
The DSI main features are:
• Compliant with MIPI Alliance standards
• Interface with internal MIPI D-PHY
• Supports all commands defined in the MIPI Alliance specification for DCS:
– Transmission of all command mode packets through the APB interface
– Transmission of commands in low-power and high-speed during video mode
• Support of up to 2 D-PHY data lanes
• Bidirectional communication and escape mode support through data lane 0
• Support of non-continuous clock in D-PHY clock lane for additional power saving
• Support of ultra low-power mode with PLL disabled
• ECC and checksum capabilities
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• Support for end of transmission packet (EoTp)

• Fault recovery schemes
• Configurable selection of system interfaces:
– AMBA® APB for control and optional support for generic and DCS commands
– Video mode interface through LTDC
– Adapted command mode interface through LTDC
– Independently programmable virtual channel ID in video mode, adapted command
mode and APB slave
• Video mode interfaces features:
– LTDC interface color coding mappings into 24-bit interface:
- 16-bit RGB, configurations 1, 2, and 3
- 18-bit RGB, configurations 1 and 2
- 24-bit RGB
– Programmable polarity of all LTDC interface signals
– Extended resolutions beyond the DPI standard maximum resolution of
800x480 pixels
– Maximum resolution is limited by available DSI physical link bandwidth:
- Number of lanes: 2
- Maximum speed per lane: 500 Mbit/s
• Adapted interface features:
– Support for sending large amounts of data through the memory_write_start (WMS)
and memory_write_continue (WMC) DCS commands
– LTDC interface color coding mappings into 24-bit interface:
- 16-bit RGB, configurations 1, 2, and 3
- 18-bit RGB, configurations 1 and 2
- 24-bit RGB
• Video mode pattern generator:
– Vertical and horizontal color bar generation without LTDC stimuli
– BER pattern without LTDC stimuli
3.41 Touch sensing controller (TSC)

The TSC provides a simple solution to add capacitive sensing functionality to any
application. A capacitive sensing technology is able to detect finger presence near
an electrode that is protected from direct touch by a dielectric (such as glass or plastic). The
capacitive variation introduced by the finger (or any conductive object) is measured using
a proven implementation based on a surface charge transfer acquisition principle.
The TSC is fully supported by the STMTouch touch sensing firmware library that is free to
use and allows touch sensing functionality to be implemented reliably in the end application.
The TSC main features are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 22 capacitive sensing channels
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• Up to eight capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.42 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and
an internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct
a non-deterministic random bit generator (NDRBG).
The true random generator:
• delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage
• can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG)
• produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise)
• embeds startup and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• can be disabled to reduce power consumption, or enabled with an automatic low-power
mode (default configuration)
• has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored)
3.43 Secure advanced encryption standard hardware accelerator

(SAES)
and encryption standard hardware accelerator (AES)
The devices embed two AES accelerators: SAES and AES. The SAES with hardware
unique key embeds protection against differential power analysis (DPA) and related side
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channel attacks. The SAES can share its current key register information with the faster
AES using a dedicated hardware bus.
The SAES and the AES can be used to both encrypt and decrypt data using the AES
algorithm. It is a fully compliant implementation of the advanced encryption standard (AES)
as defined by Federal Information Processing Standards Publication (FIPS PUB 197,
Nov 2001).
Multiple chaining modes are supported for key sizes of 128 or 256 bits. ECB and CBC
chaining is supported by both SAES and AES, while CTR, CCM, GCM and GMAC chaining
is only supported by the AES.
SAES and AES support DMA single transfers for incoming and outgoing data (two DMA
channels required).
The SAES supports the selection of all the following key sources, while the AES support
only the first:
• 256-bit software key, written by the application in the key registers (write only)
• 256-bit derived hardware unique key (DHUK), computed inside the SAES engine from
a non-volatile OTP based root hardware unique key (RHUK)
• 256-bit boot hardware key (BHK), stored in tamper-resistant secure backup registers,
written by a secure code during boot. Once written, this key cannot be read or write by
any application until the next product reset.
• XOR of DHUK (provisioned chip secret) and BHK (software secret)
DHUK, BHK and their XOR are not visible by any software (even secure).
Note: 128-bit key size can also be selected.
BHK key is cleared in case of tamper or RDP regression.
When the SAES is secure (respectively nonsecure), DHUK secure (respectively nonsecure)
is used.
The SAES peripheral is connected by hardware to the true random number generator RNG
(for side-channel resistance).
The SAES and AES peripherals support:
• Compliant implementation of standard NIST Special Publication 197, Advanced
Encryption Standard (AES) and Special Publication 800-38A, Recommendation for
Block Cipher Modes of Operation
• 128-bit data block processing
• Support for cipher keys length of 128-bit and 256-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
• Additional chaining modes supported by AES only:
– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• 528 or 743 clock cycle latency in ECB encryption mode for SAES processing one
128-bit block of data with, respectively, 128-bit or 256-bit key
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• 51 or 75 clock cycle latency in ECB encryption mode for AES processing one 128-bit
block of data with, respectively, 128-bit or 256-bit key
• Integrated round key scheduler to compute the last round key for AES ECB/CBC
decryption
• 256-bit register for storing the cryptographic key (four 32-bit registers), with key
atomicity enforcement
• 128-bit registers for storing initialization vectors (four 32-bit registers)
• One 32-bit input buffer and one 32-bit output buffer
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data swapping logic to support 1-, 8-, 16- or 32-bit data
• Possibility for software to suspend a message if the SAES/AES needs to process
another message with a higher priority (suspend/resume operation)
• SAES additional features:
– Security context enforcement for keys
– Hardware secret key encryption/ decryption (wrapped key mode) and sharing with
faster AES peripheral (Shared key mode)
– Protection against differential power analysis (DPA) and related side-channel
attacks
– Optional hardware loading of two hardware secret keys (BHK, DHUK) that can be
XORed together
On top of standard AES encryption and decryption with a key loaded by software, SAES
peripheral allows the following advanced use cases:
• Allow or deny the sharing of a key between a secure and a nonsecure application,
enforced by hardware
• Encrypt once a key using side-channel resistant AES, then share it to a faster AES
engine by decrypting it (Shared key mode)
• On-chip encrypted storage using chip-unique secret DHUK
• Transport key generation by encrypting the device public unique ID with the application
secret BHK
• Binding of device secure storage keys, using the silicon unique secret key (DHUK)
XORed with the boot secret key (BHK). If BHK is lost, the whole device secure storage
is lost.
Note: Encrypted storage or derived keys that are using DHUK or BHK, cannot be used anymore
when a security breach is detected.
Table 19. AES/SAES features

AES/SAES modes/features(1) AES SAES
ECB, CBC chaining X X

CTR, CCM, GCM chaining X -
AES 128-bit ECB encryption in cycles 51 528
DHUK and BHK key selection - X
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Table 19. AES/SAES features (continued)

AES/SAES modes/features(1) AES SAES
Side-channel attacks resistance - X

Shared key between SAES and AES X
1. X = supported.
3.44 HASH hardware accelerator (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for
applications requiring message authentication.
The HASH computes FIPS (Federal information processing standards) approved digests of
length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes 128 bits
digests for the MD5 algorithm.
The HASH main features are:
• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256, and MD5
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
– 66 clock cycles for processing one 512-bit block of data using MD5 algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message:
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO of sixteen 32-bit words,
corresponding to one block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
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• Automatic data flow control with support of direct memory access (DMA) using one
channel. Single or fixed burst of 4 supported.
• Interruptible message digest computation, on a per-32-bit word basis
– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including using DMA
3.45 On-the-fly decryption engine (OTFDEC)

The OTFDEC allows the decryption of the on-the-fly AHB traffic based on the read request
address information, for example execute-in-place of a code stored encrypted. Four
independent and non-overlapping encrypted regions can be defined in OTFDEC.
OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency.
As consequence, each time the content of one encrypted region is changed the entire
region must be re-encrypted with a different cryptographic context (key or initialization
vector). This constraint makes OTFDEC suitable to decrypt read-only data or code, stored in
external NOR Flash.
Note: When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the flash
memory using the Memory-mapped mode of the flash memory controller.
When security is enabled in the product, OTFDEC can be programmed only by
a secure host.
The OTFDEC main features are the following:
• On-the-fly 128-bit decryption during OCTOSPI memory-mapped read operations
(single or multiple)
– Use of AES in counter (CTR) mode, with two 128-bit keystream buffers
– Support for any read size
– Physical address of the reads is used for the encryption/decryption
• Up to 4 independent encrypted regions
– Granularity of the region definition: 4096 bytes
– Region configuration write locking mechanism
– Each region has its own 128-bit key, two bytes firmware version, and eight bytes
application-defined nonce. At least one of those must be changed each time
an encryption is performed by the application.
• Encryption keys confidentiality and integrity protection
– Write-only registers, with software locking mechanism
– Availability of 8-bit CRC as public key information
• Support for OCTOSPI prefetching mechanism
• Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher (execute only)
• AMBA® AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)
• Secure only programming if TrustZone security is enabled
• Encryption mode
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3.46 Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically
those related to RSA, Diffie-Hellmann or ECC (elliptic curve cryptography) over GF(p)
(Galois fields). To achieve high performance at a reasonable cost, these operations are
executed in the Montgomery domain.
All needed computations are performed within the accelerator, so no further
hardware/software elaboration is needed to process the inputs or the outputs.
The PKA main features are:
• Acceleration of RSA, DH and ECC over GF(p) operations, based on the Montgomery
method for fast modular multiplications. More specifically:
– RSA modular exponentiation, RSA Chinese remainder theorem (CRT)
exponentiation
– ECC scalar multiplication, point on curve check, complete addition, double base
ladder, projective to affine
– ECDSA signature generation and verification
• Capability to handle operands up to 4160 bits for RSA/DH and 640 bits for ECC
• Arithmetic and modular operations such as addition, subtraction, multiplication,
modular reduction, modular inversion, comparison, and Montgomery multiplication
• Built-in Montgomery domain inward and outward transformations
• Protection against differential power analysis (DPA) and related side-channel attacks.
3.47 Timers and watchdogs

The devices include two advanced control timers, up to seven general-purpose timers, two
basic timers, four low-power timers, two watchdog timers and two SysTick timers.
The table below compares the features of the advanced control, general-purpose and basic
timers.
Table 20. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
Advanced Up, down,
TIM1, TIM8 16 bits between 1 and Yes 4 3
control Up/down
65536
Any integer
General- TIM2, TIM3, Up, down,
32 bits between 1 and Yes 4 No
purpose TIM4, TIM5 Up/down
65536
Any integer
General-
TIM15 16 bits Up between 1 and Yes 2 1
purpose
65536
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Table 20. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
General- TIM16,
16 bits Up between 1 and Yes 1 1
purpose TIM17
65536
Any integer
Basic TIM6, TIM7 16 bits Up between 1 and Yes 0 No
65536
3.47.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers can each be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers.
The four independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability
(0 - 100 %)
• One-pulse mode output
In Debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled in order to turn off any power switches driven by these outputs.
Many features are shared with the general-purpose TIMx timers (described in the next
section) using the same architecture, so the advanced-control timers can work together with
the TIMx timers via the Timer Link feature for synchronization or event chaining.
3.47.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15,

TIM16,TIM17)
There are up to seven synchronizable general-purpose timers embedded in the
STM32U5Axxx devices (see Table 20 for differences). Each general-purpose timer can be
used to generate PWM outputs, or act as a simple time base.
• TIM2, TIM3, TIM4 and TIM5
They are full-featured general-purpose timers with 32-bit auto-reload up/downcounter
and 16-bit prescaler.
These timers feature four independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other
general-purpose timers via the Timer Link feature for synchronization or event
chaining.
The counters can be frozen in Debug mode.
All have independent DMA request generation and support quadrature encoders.
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• TIM15, 16 and 17
They are general-purpose timers with mid-range features.
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has two channels and one complementary channel
– TIM16 and TIM17 have one channel and one complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in Debug mode.
3.47.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebase.
3.47.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4)

The devices embed four low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by HSI16, MSI, LSE, LSI or an external clock. They
are able to wake up the system from Stop mode.
LPTIM1, LPTIM3, and LPTIM4 are active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
The low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 3-bit prescaler with eight possible dividing factors (1, 2, 4, 8, 16, 32, 64, 128)
• Selectable clock
– Internal clock sources: LSE, LSI, HSI16, MSIK (LPTIM1, LPTIM3, LPTIM4 only) or
APB clock (LPTIM2 only)
– External clock source over LPTIM input (working with no LP oscillator running,
used by Pulse Counter application)
• 16-bit ARR autoreload register
• 16-bit capture/compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable digital glitch filter
• Configurable output: pulse, PWM
• Configurable I/O polarity
• Encoder mode
• Repetition counter
• Up to 2 independent channels for:
– Input capture
– PWM generation (edge-aligned mode)
– One-pulse mode output
• Interrupt generation on 10 events
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• DMA request generation on the following events:

– Update event
– Input capture
3.47.5 Infrared interface (IRTIM)

An infrared interface (IRTIM) for remote control is available on the device. It can be used
with an infrared LED to perform remote control functions. It uses internal connections with
TIM16 and TIM17.
3.47.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and a 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and, as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as
a watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in Debug mode.
3.47.7 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen
in Debug mode.
3.47.8 SysTick timer

The Cortex-M33 with TrustZone embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance
• SysTick, nonsecure instance
When TrustZone is disabled, only one SysTick timer is available. This timer (secure or
non-secure) is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
3.48 Real-time clock (RTC), tamper and backup registers
3.48.1 Real-time clock (RTC)

The RTC supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), weekday, date,
month, year, in BCD (binary-coded decimal) format
• Binary mode with 32-bit free-running counter
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• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature that can be used to save the calendar content. This function can be
triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period
– RTC fully securable
– Alarm A, alarm B, wake-up timer and timestamp individual secure or nonsecure
configuration
– Alarm A, alarm B, wake-up timer and timestamp individual privileged protection
The RTC is supplied through a switch that takes power either from the VDD supply when
present or from the VBAT pin.
The RTC clock sources can be one of the following:
• 32.768 kHz external crystal (LSE)
• external resonator or oscillator (LSE)
• internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• high-speed external clock (HSE), divided by a prescaler in the RCC.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, timestamp) can generate an interrupt and wake up
the device from the low-power modes.
3.48.2 Tamper and backup registers (TAMP)

The anti-tamper detection circuit is used to protect sensitive data from external attacks. 32
32-bit backup registers are retained in all low-power modes and also in VBAT mode. The
backup registers, as well as other secrets in the device, are protected by this anti-tamper
detection circuit with eight tamper pins and eleven internal tampers. The external tamper
pins can be configured for edge detection, or level detection with or without filtering, or
active tamper that increases the security level by auto checking that the tamper pins are not
externally opened or shorted.
TAMP main features:
• A tamper detection can erase the backup registers, backup SRAM, SRAM2, caches,
and cryptographic peripherals.
• 32 32-bit backup registers:
– The backup registers (TAMP_BKPxR) are implemented in the Backup domain that
remains powered-on by VBAT when the VDD power is switched off.
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• Up to 8 tamper pins for 8 external tamper detection events:

– Active tamper mode: continuous comparison between tamper output and input to
protect from physical open-short attacks
– Flexible active tamper I/O management: from 4 meshes (each input associated to
its own exclusive output) to 7 meshes (single output shared for up to 7 tamper
inputs)
– Passive tampers: ultra-low power edge or level detection with internal pull-up
hardware management
– Configurable digital filter
• 11 internal tamper events to protect against transient or environmental perturbation
attacks:
– Backup domain voltage monitoring
– Temperature monitoring
– LSE monitoring
– RTC calendar overflow
– JTAG/SWD access if RDP different from 0
– Monotonic counter overflow
– Cryptographic peripherals fault (RNG, SAES, AES, PKA)
– Independent watchdog reset when tamper flag is already set
– 3 ADC4 watchdogs
• Each tamper can be configured in two modes:
– Hardware mode: immediate erase of secrets on tamper detection, including
backup registers erase
– Software mode: erase of secrets following a tamper detection launched by
software
• Any tamper detection can generate a RTC time stamp event.
– Tamper secure or nonsecure configuration
– Backup registers configuration in 3 configurable-size areas:
- 1 read/write secure area
- 1 write secure/read nonsecure area
- 1 read/write nonsecure area
– Boot secret key (BHK) only usable by secure AES peripheral, stored in backup
registers, protected against read and write access
• Tamper configuration and backup registers privilege protection
• Monotonic counter
3.49 Inter-integrated circuit interface (I2C)

The device embeds six I2C. Refer to Table 21 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
88/390 DS13543 Rev 2

The I2C peripheral supports:

• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bit rate up to 100 Kbit/s
– Fast-mode (Fm), with a bit rate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with
ACK control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.3 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Autonomous functionality in Stop modes with wake-up from Stop capability
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 21. I2C implementation

I2C features(1) I2C1 I2C2 I2C3 I2C4 I2C5 I2C6
Standard-mode (up to 100 Kbit/s) X X X X X X

Fast-mode (up to 400 Kbit/s) X X X X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X X X X
Programmable analog and digital noise filters X X X X X X
SMBus/PMBus hardware support X X X X X X
Independent clock X X X X X X
Autonomous in Stop 0, Stop 1 mode with wake-up capability X X X X X X
Autonomous in Stop 2 mode with wake-up capability - - X - - -
1. X: supported
3.50 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
and low-power universal asynchronous receiver transmitter
(LPUART)
The devices embed four universal synchronous receiver transmitters (USART1, USART2,
USART3 and USART6), two universal asynchronous receiver transmitters (UART4, UART5)
and one low-power universal asynchronous receiver transmitter (LPUART1).
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Table 22. USART, UART and LPUART features

USART modes/features(1) USART1/2/3/6 UART4/5 LPUART1
Hardware flow control for modem X X X

Continuous communication using DMA X X X
Multiprocessor communication X X X
Synchronous mode (master/slave) X - -
Smartcard mode X - -
Single-wire half-duplex communication X X X
IrDA SIR ENDEC block X X -
LIN mode X X -
(2)
Dual-clock domain and wake-up from Stop mode X X(2) X(3)
Receiver timeout interrupt X X -
Modbus communication X X -
Auto-baud rate detection X X -
Driver enable X X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X X
Tx/Rx FIFO size 8 bytes
Autonomous mode X X X
1. X = supported.
2. Wake-up supported from Stop 0 and Stop 1 modes.
3. Wake-up supported from Stop 0, Stop 1 and Stop 2 modes.
3.50.1 Universal synchronous/asynchronous receiver transmitter

(USART/UART)
The USART offers a flexible means to perform full-duplex data exchange with external
equipments requiring an industry standard NRZ asynchronous serial data format. A very
wide range of baud rates can be achieved through a fractional baud rate generator.
The USART supports both synchronous one-way and half-duplex single-wire
communications, as well as LIN (local interconnection network), Smartcard protocol, IrDA
(infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS).
Multiprocessor communications are also supported.
High-speed data communications up to 20 Mbauds are possible by using the DMA (direct
memory access) for multibuffer configuration.
The USART main features are:
• Full-duplex asynchronous communication
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to achieve the best compromise
between speed and clock tolerance
• Baud rate generator systems
90/390 DS13543 Rev 2

• Two internal FIFOs for transmit and receive data

Each FIFO can be enabled/disabled by software and come with a status flag.
• A common programmable transmit and receive baud rate
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous Master/Slave mode and clock output/input for synchronous
communications
• SPI slave transmission underrun error flag
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Communication control/error detection flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from stop capability
• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16-bit duration for Normal mode
• Smartcard mode
– Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for Smartcard operation
• Support for Modbus communication
– Timeout feature
– CR/LF character recognition
3.50.2 Low-power universal asynchronous receiver transmitter (LPUART)

The LPUART supports bidirectional asynchronous serial communication with minimum
power consumption. It also supports half-duplex single-wire communication and modem
operations (CTS/RTS). It allows multiprocessor communication.
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Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to

9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher-speed clock can be used to
reach higher baudrates.
The LPUART interface can be served by the DMA controller.
The LPUART main features are:
• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate
• From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• Higher baud rates can be achieved by using a higher frequency clock source
• Two internal FIFOs to transmit and receive data
Each FIFO can be enabled/disabled by software and come with status flags for
FIFO states.
• Dual-clock domain with dedicated kernel clock for peripherals independent from PCLK
• Programmable data word length (7 or 8 or 9 bits)
• Configurable stop bits (1 or 2 stop bits)
• Single-wire half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Interrupt sources with flags
• Multiprocessor communications: wake-up from Mute mode by idle line detection or
address mark detection
• Autonomous functionality in Stop mode with wake-up from Stop capability
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3.51 Serial peripheral interfaces (SPI)

The devices embed three serial peripheral interfaces (SPI) that can be used to
communicate with external devices while using the specific synchronous protocol. The SPI
protocol supports half-duplex, full-duplex and simplex synchronous, serial communication
with external devices.
The interface can be configured as master or slave and can operate in multi-slave or
multi-master configurations. The device configured as master provides communication
clock (SCK) to the slave device. The slave select (SS) and ready (RDY) signals can be
applied optionally just to setup communication with concrete slave and to assure it handles
the data flow properly. The Motorola® data format is used by default, but some other specific
modes are supported as well.
The SPI main features are:
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 4-bit to 32-bit data size selection or fixed to 8-bit and 16-bit only
• Multi master or multi slave mode capability
• Dual-clock domain, separated clock for the peripheral kernel that can be independent
of PCLK
• Baud rate prescaler up to kernel frequency/2 or bypass from RCC in Master mode
• Protection of configuration and setting
• Hardware or software management of SS for both master and slave
• Adjustable minimum delays between data and between SS and data flow
• Configurable SS signal polarity and timing, MISO x MOSI swap capability
• Programmable clock polarity and phase
• Programmable number of data within a transaction to control SS and CRC
• Dedicated transmission and reception flags with interrupt capability
• SPI Motorola® and Texas Instruments® formats support
• Hardware CRC feature can secure communication at the end of transaction by:
– Adding CRC value in Tx mode
– Automatic CRC error checking for Rx mode
• Error detection with interrupt capability in case of data overrun, CRC error, data
underrun at slave, mode fault at master
• Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
• Programmable number of data in transaction
• Configurable FIFO thresholds (data packing)
• Configurable behavior at slave underrun condition (support of cascaded circular
buffers)
• Autonomous functionality in Stop modes (handling of the transaction flow and required
clock distribution) with wake-up from stop capability
• Optional status pin RDY signalizing the slave device ready to handle the data flow.
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Table 23. SPI features

SPI1, SPI2 SPI3
SPI feature
(full feature set instances) (limited feature set instance)
Data size Configurable from 4 to 32-bit 8/16-bit

CRC polynomial length CRC polynomial length
CRC computation
configurable from 5 to 33-bit configurable from 9 to 17-bit
Size of FIFOs 16x 8-bit 8x 8-bit
Number of transfered data Unlimited, expandable Up to 1024, no data counter
Autonomous in Stop 0, Stop 1 mode
Yes Yes
with wake-up capability
Autonomous in Stop 2 mode with
No Yes
wake-up capability
3.52 Serial audio interfaces (SAI)

The devices embed two SAI. Refer to Table 24: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks that can be transmitters or receivers with their
respective FIFO
• 8-word integrated FIFOs for each audio sub-block
• Synchronous or Asynchronous mode between the audio sub-blocks
• Master or slave configuration independent for both audio sub-blocks
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and
SPDIF out
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame
• Number of bits by frame may be configurable
• Frame synchronization active level configurable (offset, bit length, level)
• First active bit position in the slot is configurable
• LSB first or MSB first for data transfer
• Mute mode
• Stereo/mono audio frame capability
• Communication clock strobing edge configurable (SCK)
• Error flags with associated interrupts if enabled respectively
– Overrun and underrun detection
– Anticipated frame synchronization signal detection in Slave mode
– Late frame synchronization signal detection in Slave mode
94/390 DS13543 Rev 2

– Codec not ready for the AC’97 mode in reception

• Interruption sources when enabled:
– Errors
– FIFO requests
• DMA interface with two dedicated channels to handle access to the dedicated
integrated FIFO of each SAI audio sub-block.
Table 24. SAI implementation

SAI features(1) SAI1 SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X X

Mute mode X X
Stereo/mono audio frame capability. X X
16 slots X X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X X
FIFO size X (8 words) X (8 words)
SPDIF X X
PDM X -
1. X: supported
3.53 Secure digital input/output and MultiMediaCards interface

(SDMMC)
The SDMMC (SD/SDIO embedded MultiMediaCard e•MMC™ host interface) provides
an interface between the AHB bus and SD memory cards, SDIO cards and e•MMC devices.
The MultiMediaCard system specifications are available through the MultiMediaCard
association website at www.mmca.org, published by the MMCA technical committee.
SD memory card and SD I/O card system specifications are available through the SD card
Association website at www.sdcard.org.
The SDMMC features include the following:
• Compliance with Embedded MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit
(HS200 SDMMC_CK speed limited to maximum allowed I/O speed) (HS400 is not
supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility).
• Full compliance with SD memory card specifications version 6.0
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit
(SDR104 SDMMC_CK speed limited to maximum allowed I/O speed, SPI mode and
UHS-II mode not supported).
DS13543 Rev 2 95/390

99
• Data transfer up to 208 Mbyte/s for the 8-bit mode

(Depending maximum allowed I/O speed).
• Data and command output enable signals to control external bidirectional drivers
• IDMA linked list support
The MultiMediaCard/SD bus connects cards to the host.
The current version of the SDMMC supports only one SD/SDIO/e•MMC card at any one
time and a stack of e•MMC.
Table 25. SDMMC features

SDMMC modes/features(1) SDMMC1 SDMMC2
Variable delay (SDR104, HS200) X X

SDMMC_CKIN X -
SDMMC_CDIR, SDMMC_D0DIR X -
SDMMC_D123DIR X -
1. X = supported.
When SDMMC peripherals are used simultaneously:

• Only one can be used in e•MMC with 8-bit bus width.
• The SDMMC1 SDIO voltage switch use is mutually exclusive with SDMMC2 interfacing
e•MMC with 8-bit bus width, as follows:
– If SDMMC1 has to support SDIO UHS-I modes (SDR12, SDR25, SDR50,
SDR104 or DDR50), SDMMC2 cannot support e•MMC with 8-bit bus width.
– if SDMMC2 has to support e•MMC with 8-bit bus width, SDMMC1 supports only
SDIO default mode and high-speed mode.
3.54 Controller area network (FDCAN)

The controller area network (CAN) subsystem consists of one CAN module, a shared
message RAM memory and a configuration block.
The modules (FDCAN) are compliant with ISO 11898-1: 2015 (CAN protocol specification
version 2.0 part A, B) and CAN FD protocol specification version 1.0.
A 0.8-Kbyte message RAM implements filters, receives FIFOs, transmits event FIFOs and
transmits FIFOs.
The FDCAN main features are:
• Conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015, -4
• CAN FD with maximum 64 data bytes supported
• CAN error logging
• AUTOSAR and J1939 support
• Improved acceptance filtering
• 2 receive FIFOs of three payloads each (up to 64 bytes per payload)
• Separate signaling on reception of high priority messages
• Configurable transmit FIFO / queue of three payload (up to 64 bytes per payload)
96/390 DS13543 Rev 2

• Configurable transmit Event FIFO

• Programmable loop-back test mode
• Maskable module interrupts
• Two clock domains: APB bus interface and CAN core kernel clock
• Power-down support
3.55 USB on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed device/host/OTG peripheral with integrated
transceivers. The OTG_HS peripheral is compliant with the USB 2.0 specification and with
the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume.
This interface requires a precise 60 MHz clock that is generated from the internal
USB PHY PLL (the clock source must use a HSE crystal oscillator).
The OTG_HS features are:
• USB-IF certified to the Universal Serial Bus Specification Rev 2.0
• On-chip high-speed PHY
• Full support (PHY) for the optional OTG (on-the-go) protocol detailed in the OTG
Supplement Rev 2.0 specification
– Integrated support for A-B device identification (ID line)
– Supports OTG monitoring of VBUS levels with internal comparators
– Supports dynamic host-peripheral switch of role
• Software-configurable to operate as USB on-the-go high-speed dual role device
• Supports HS/FS SOF and LS keep-alives with
– SOF pulse PAD connectivity
– SOF pulse internal connection to timer (TIMx)
– Configurable framing period
– Configurable end of frame interrupt
• USB 2.0 link power management (LPM) support
• Internal DMA with thresholding support and software selectable AHB burst type in DMA
mode
• Power saving features such as system stop during USB suspend, switch-off of clock
domains internal to the digital core, PHY and DFIFO power management
• Dedicated RAM of 4 Kbytes with advanced FIFO control:
– Configurable partitioning of RAM space into different FIFOs for flexible and
efficient use of RAM
– Each FIFO able to hold multiple packets
– Dynamic memory allocation
– Configurable FIFO sizes that are not powers of two to allow the use of contiguous
memory locations
• Max guaranteed USB bandwidth for up to one frame (1 ms) without system intervention
• Support of charging port detection as described in Battery Charging Specification
revision 1.2
DS13543 Rev 2 97/390

99
Host-mode features:
• External charge pump for VBUS voltage generation
• Up to 16 host channels (pipes): each channel is dynamically reconfigurable to allocate
any type of USB transfer
• Built-in hardware scheduler holding:
– Up to 16 interrupt plus isochronous transfer requests in the periodic hardware
queue
– Up to 16 control plus bulk transfer requests in the non-periodic hardware queue
• Management of a shared Rx FIFO, a periodic Tx FIFO and a non periodic Tx FIFO for
efficient usage of the USB data RAM
Peripheral-mode features:
• 1 bidirectional control endpoint0
• 8 IN endpoints (EPs) configurable to support bulk, interrupt or isochronous transfers
• 8 OUT endpoints configurable to support bulk, interrupt or isochronous transfers
• Management of a shared Rx FIFO and a Tx-OUT FIFO for efficient usage of the USB
data RAM
• Management of up to 9 dedicated Tx-IN FIFOs (one for each active IN EP) to put less
load on the application
• Support for the soft disconnect feature
3.56 USB Type-C /USB Power Delivery controller (UCPD)

The device embeds one controller (UCPD) compliant with USB Type-C Cable and
Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications.
The controller uses specific I/Os supporting the USB Type-C and USB power delivery
requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• “Dead battery” support
• USB power delivery message transmission and reception
• FRS (fast role swap) support
The digital controller handles notably:
• USB Type-C level detection with debounce, generating interrupts
• FRS detection, generating an interrupt
• Byte-level interface for USB power delivery payload, generating interrupts
(DMA compatible)
• USB power delivery timing dividers (including a clock prescaler)
• CRC generation/checking
• 4b5b encode/decode
• Ordered sets (with a programmable ordered set mask at receive)
• Frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the
capacity to detect incoming USB power delivery messages and FRS signaling.
98/390 DS13543 Rev 2

3.57 Development support
3.57.1 Serial-wire/JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded and is a combined JTAG and serial-wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using two pins only instead of five required by the JTAG (JTAG pins can
be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.57.2 Embedded Trace Macrocell

The Arm Embedded Trace Macrocell (ETM) provides a greater visibility of the instruction
and data flow inside the CPU core by streaming compressed data at a very high rate from
the devices through a small number of ETM pins to an external hardware trace port analyzer
(TPA) device.
Real-time instruction and data flow activity be recorded and then formatted for display on
the host computer that runs the debugger software. TPA hardware is commercially available
from common development tool vendors.
The ETM operates with third party debugger software tools.
DS13543 Rev 2 99/390

99
Pinout, pin description and alternate functions STM32U5Axxx
4 Pinout, pin description and alternate functions
4.1 Pinout/ballout schematics

Figure 7. LQFP64_SMPS pinout
PH3-BOOT0
VDD11
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PB0
PB1
PB2
VLXSMPS
PB10
VDDSMPS
VSSSMPS
VSS
PA3
PA4
PA5
PA6
PA7
VDD11
MSv62929V1
1. The above figure shows the package top view.
100/390 DS13543 Rev 2

STM32U5Axxx Pinout, pin description and alternate functions
Figure 8. LQFP64 pinout
PH3-BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7
MSv62923V1
DS13543 Rev 2 101/390

180
PH3-BOOT0
VDD11
PC10
PC12
PC11
PA14
PA15
VDD
VSS
PD0
PD1
PD3
PD2
PD4
PD6
PD5
PD7
PB4
PB3
PB6
PB5
PB7
PB9
PB8
PE0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 VDD
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSSSMPS
VDDSMPS
VLXSMPS
PB10
PE14
PE15
PE13
PE12
PE10
PE8
PE9
PE7
PB2
PB1
PB0
VDD
VSS
VDD11
PB11
PE11
PA7
PA6
PA5
PA4
MSv62930V1
102/390 DS13543 Rev 2

PH3-BOOT0
PC10
PC12
PC11
PA14
PA15
VDD
VSS
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
VSS
VCAP
PB10
PE15
PE14
PE13
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PB0
PC5
PC4
VDD
VSS
PE11
PA7
PA6
PA5
PA4
PA3
MSv62924V1
DS13543 Rev 2 103/390

180
Figure 11. UFBGA132_SMPS ballout
1 2 3 4 5 6 7 8 9 10 11 12
A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB
PH3-
B VBAT PE4 PE2 VDD11
BOOT0
PB4 PG9 PD4 PD1 PC12 PC10 PA12
PC14-
C OSC32 PE6 PC13 PE0 PB8 PB3 PG10 PD3 PD0 PA13 PA14 PA11
_IN
PC15-
D OSC32_ PF0 PF3 VDD PB7 PB5 PD7 VDDIO2 VDD PA9 PA10 PA8
OUT
E PF2 PF1 PF4 VSS VSS PC7 PC9 PC8
PH0-
F OSC_IN
PF5 PC2 PC3 VSS VDD PG6 PG7 PC6 PG8
PH1-OSC
G _OUT
NRST PC1 PA1 VDD VSS PG4 PG2 PG3 PG5
OPAMP1
H VSSA PC0
_VINM
VSS VSS PD14 PD13 PD15
J VREF+ PA0 PC5 VDD PF14 PE8 PE10 PE12 VDD PD9 PD11 PD12
K VDDA PA2 PA7 PB2 PF11 PG1 PE7 PE14 PB10 PB13 PB14 PB15
VSS
L PA3 PA6 PA4 PB1 PF12 PF15 PE11 PE15 PB11
SMPS
PB12 PD8
OPAMP2 VDD VLX

M PA5
_VINM
PC4 PB0 PF13 PG0 PE9 PE13
SMPS SMPS
VDD11 PD10
MSv62931V2
104/390 DS13543 Rev 2

Figure 12. UFBGA132 ballout
1 2 3 4 5 6 7 8 9 10 11 12
A PE5 PE3 PE1 PB9 PB6 PG12 PD6 PD5 PD2 PC11 PA15 VDDUSB
PH3-
B VBAT PE4 PE2 PG15
BOOT0
PB4 PG9 PD4 PD1 PC12 PC10 PA12
PC14-
C OSC32 PE6 PC13 PE0 PB8 PB3 PG10 PD3 PD0 PA13 PA14 PA11
_IN
PC15-
D OSC32_ PF0 PF3 VDD PB7 PB5 PD7 VDDIO2 VDD PA9 PA10 PA8
OUT
E PF2 PF1 PF4 VSS VSS PC7 PC9 PC8
PH0-
F OSC_IN
PF5 PC2 PC3 VSS VDD PG6 PG7 PC6 PG8
PH1-
G OSC_ NRST PC1 PA1 VDD VSS PG4 PG2 PG3 PG5
OUT
OPAMP1
H VSSA PC0
_VINM
VSS VSS PD14 PD13 PD15
J VREF+ PA0 PC5 VDD PF14 PE8 PE10 PE12 VDD PD9 PD11 PD12
K VDDA PA2 PA7 PB2 PF11 PG1 PE7 PE14 PB10 PB13 PB14 PB15
L PA3 PA6 PA4 PB1 PF12 PF15 PE11 PE15 PB11 VCAP PB12 PD8
OPAMP2
M PA5
_VINM
PC4 PB0 PF13 PG0 PE9 PE13 PG14 PG13 PG11 PD10
MSv62925V2
DS13543 Rev 2 105/390

180
PH3-BOOT0
VDDIO2
VDD11
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PC11
PA15
PA14
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF+ 31 78 PD9
VDDA 32 77 PD8
PA0 33 76 PB15
PA1 34 75 PB14
PA2 35 74 PB13
PA3 36 73 VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VSS
VDD
PB0
PB1
PB2
PF12
PF13
PE8
VSS
VDD
PF14
PF15
PG0
PG1
PE7
PE9
VLXSMPS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VDDSMPS
VSSSMPS
VSS
PA4
PA5
PA6
PA7
PF11
PE11
PB11
VDD11
MSv62932V1
106/390 DS13543 Rev 2

PH3-BOOT0
VDDIO2
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VDDUSB
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDIO2
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VSSA 30 79 PD10
VREF- 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
PG0
PG1
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PE7
PE8
PE9
VSS
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PA3
PA4
PA5
PA6
PA7
PF11
PE11
MSv62926V1
DS13543 Rev 2 107/390

180
Figure 15. WLCSP150_SMPS ballout
1 2 3 4 5 6 7 8 9 10 11 12 13
A VDDUSB VDD PD3 PG12 PB5 VDD11 PE2
B VDD11 PC11 VDD VDDIO2 PB9 VDD
C PA12 VSS PD2 PG11 PB7 VSS VBAT
D PA13 PC10 VSS VSS PE3 PC13
PC14-
E PA11 PA10 PD1 PG10 PB6 PE6
OSC32_IN
F PA9 PA15 PD5 PG14 PE4 VSS
PC15-
PH3-
G PC8 PA8 PD0 PG13
BOOT0
PF0 OSC32
_OUT
H PC9 PA14 PD4 PG15 PE5 PF1
J VDDIO2 PC6 PC12 PG9 PB8 PF4 PF2
K VSS PG8 PD6 PB3 PE1 PF3
L PG7 PG5 PC7 PD7 PB4 PF5 VDD
M PG4 PG3 PG6 PC1 PE0 VSS
N PG2 PD14 PB15 PC5 PC0 PF6 PF7
P PD15 PD11 PF13 PA4 PF8 PF9
PH0-
R VDD PD12 PB13 PF11 PA2 PF10
OSC_IN
T VSS PB14 PG0 PB0 PA0 NRST
PH1-
U PD13 PD10 PE9 PF14 PA6 PC3
OSC_OUT
V PD9 PE12 PE8 PF12 PA3 PC2
W PD8 PB10 PE11 PG1 PB1 PA1 VSSA
Y PB12 PE13 PE10 PF15 PA7 VREF+
AA VSS PB11 PE15 VSS VSS PA5 VDDA
AB VDD11 VDDSMPS PE14 PE7 PB2 VDD
AC VDD VSSSMPS VLXSMPS VDD VDD PC4 VSS
MSv71166V1
108/390 DS13543 Rev 2

Figure 16. WLCSP150_DSI_SMPS ballout
1 2 3 4 5 6 7 8 9 10 11 12 13
PC14-
A VDDUSB VDD PC12 VDD PB5 VDD
OSC32_IN
PC15-
B VDD11 PA15 PD4 PB3 VDD11 OSC32_O
UT
C PA12 VSS PD0 VSS PB8 VSS VBAT
D VSS PC10 PD5 PB6 PE2 PE6
E PA11 PA13 PD1 PB4 PE1 PC13 DSI_D0P
F PA9 PA14 PD6 PB9 PE5 PF2
G VDDIO2 PA10 PD2 PB7 PE3 PF0 DSI_D0N
H VSS PA8 PD7 PE0 PF1 VDDDSI
PH3-
J PG7 PC7 PC11
BOOT0
PE4 PF6 DSI_CKP
K PG8 PC8 PD3 PF10 PF7 VSSDSI
L PG3 PG5 PC9 PC1 PF9 PF3 DSI_CKN
M PG4 PG6 PB2 PA4 PF8 VDD11DSI
N PG2 PD13 PC6 PC5 PA3 PF4 DSI_D1P
P PD14 PE14 PG0 PA7 PC0 VSSDSI
R PD15 PD11 PE10 PF11 PA2 PF5 DSI_D1N
T PD12 PE15 PE7 PC4 PC3 VSS
U VDD PD9 PE11 PF15 PA6 NRST VDD
PH1-
V VSS PB14 PE9 PF12 PA1
OSC_OUT
PH0-
W PD10 PD8 PB10 PG1 PB1 PA0
OSC_IN
Y PB15 PB13 PE12 PF14 PB0 PC2
AA VSS PB12 PB11 PE8 PF13 PA5 VSSA
AB VDD11 VDDSMPS PE13 VSS VSS VREF+
AC VDD VSSSMPS VLXSMPS VDD VDD VDD VDDA
MSv71167V1
DS13543 Rev 2 109/390

180
Figure 17. TFBGA169_SMPS ballout

1 2 3 4 5 6 7 8 9 10 11 12 13
A PE2 PI6 VDD VDD11 PG15 VDDIO2 PG9 VDD PC11 PA15 VDD PI1 PH15
B VDD VSS PI5 VSS PB6 PB4 PD6 VSS PD0 PI4 VSS PI0 PH12
PH3-
C VBAT PE4 PI7 PE1
BOOT0
PB5 PG10 PD4 PC10 PA14 PH14 PH13 PH10
PC14-
D OSC32 PE5 PE3 PE0 PB9 PB3 PD7 PD3 PH11 PI3 PI2 PH8 VDD
_IN
PC15-
E OSC32_ PF0 PC13 PE6 PB8 PG12 PD5 PC12 PH9 PH4 PH6 VSS VDDUSB
OUT
F PF8 VSS PF1 PF2 PB7 PD1 PD2 PH7 PH5 PH2 PA10 PA13 PA12
G VDD PF7 PF9 PF5 PF3 PF4 PA8 PG7 PC9 PC8 PA9 PC7 PA11
PH0- OPAMP2
H OSC_IN
VSS NRST PF10
_VINM
PF6 PG1 PE10 PG8 PG6 PG4 VDDIO2 PC6
PH1-
J OSC_ PC0 PC1 PC2 PA7 PG0 PE9 PG3 PG5 PD14 PD15 VSS VDD
OUT
K PC3 VSSA PA0 PA5 PB0 PF12 PE8 PE14 PB10 PD12 PD10 PD13 PG2
L VREF+ VDDA PA1 PC4 PB2 PF14 PE7 PE13 PB11 PB12 PB15 PD8 PD9
OPAMP1 VSS
M _VINM
PA2 VSS PC5 PF11 PF13 VSS PE11 PE15
SMPS
VSS PB14 PD11
VLX VDD
N PA4 PA3 VDD PA6 PB1 PF15 VDD PE12
SMPS SMPS
VDD11 VDD PB13
MSv62933V3
110/390 DS13543 Rev 2

Figure 18. TFBGA169 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13
A PE2 PI6 VDD VCAP PG15 VDDIO2 PG9 VDD PC11 PA15 VDD PI1 PH15
B VDD VSS PI5 VSS PB6 PB4 PD6 VSS PD0 PI4 VSS PI0 PH12
PH3-
C VBAT PE4 PI7 PE1
BOOT0
PB5 PG10 PD4 PC10 PA14 PH14 PH13 PH10
PC14-
D OSC32_ PE5 PE3 PE0 PB9 PB3 PD7 PD3 PH11 PI3 PI2 PH8 VDD
IN
PC15-
E OSC32_ PF0 PC13 PE6 PB8 PG12 PD5 PC12 PH9 PH4 PH6 VSS VDDUSB
OUT
F PF8 VSS PF1 PF2 PB7 PD1 PD2 PH7 PH5 PH2 PA10 PA13 PA12
G VDD PF7 PF9 PF5 PF3 PF4 PA8 PG7 PC9 PC8 PA9 PC7 PA11
PH0- OPAMP2
H OSC_IN
VSS NRST PF10
_VINM
PF6 PG1 PE10 PG8 PG6 PG4 VDDIO2 PC6
PH1-
J OSC_ PC0 PC1 PC2 PA7 PG0 PE9 PG3 PG5 PD14 PD15 VSS VDD
OUT
K PC3 VSSA PA0 PA5 PB0 PF12 PE8 PE14 PB10 PD12 PD10 PD13 PG2
L VREF+ VDDA PA1 PC4 PB2 PF14 PE7 PE13 PB11 PB12 PB15 PD8 PD9
OPAMP1
M _VINM
PA2 VSS PC5 PF11 PF13 VSS PE11 PE15 PG11 VSS PB14 PD11
N PA4 PA3 VDD PA6 PB1 PF15 VDD PE12 PG14 PG13 VCAP VDD PB13
MSv62927V3
DS13543 Rev 2 111/390

180
Figure 19. WLCSP208_DSI_SMPS ballout

2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A VDDUSB VDD11 VDD PA15 PD1 VDD PG13 VDDIO2 PB6 PE0 VDD11 VDD VDD
B PA12 PA13 VSS PH2 PC10 VSS PG9 VSS PB3 PB8 PE1 VSS VBAT
PC14-
C PA11 PA10 PA9 PA8 PC11 PD3 PD7 PG14 PB5 PB9 PI5 PE6
OSC32_IN
PC15-
VDD11
D USB
PC7 PC6 PC8 PC9 PA14 PD2 PD4 PG12 PB7 PI6 PC13 OSC32
_OUT
PH3-
E VDDIO2 VSS PJ0 PI15 PH4 PH7 PC12 PD5 PG11
BOOT0
PE3 VSSDSI DSI_D0P
F VDD VSS PI14 PI13 PG2 PG8 PH5 PD0 PD6 PG10 PE4 VSSDSI DSI_D0N
G VDD VSS PI11 PI12 PG6 PG5 PG7 PH8 PB4 PE2 PE5 VDDDSI DSI_CKP
H VDD VSS PI9 PI10 PG3 PG0 PB0 PH6 PG15 PF0 PF1 VSSDSI DSI_CKN
J PI4 VSS PI2 PI8 PG4 PG1 PF7 PF6 PI7 PF2 PF4 VDD11DSI DSI_D1P
K PI3 VSS PI1 PI0 PD15 PD13 PF14 PC1 PC0 PF8 PF5 PF3 DSI_D1N
L VDD VSS PH14 PH15 PD12 PE7 PB1 PA1 PC2 PF9 PF10 VSS VDD
PH0- PH1-
M VDD VSS PH12 PH13 PH9 PD11 PE10 PB2 PA2 PC3 NRST
OSC_IN OSC_OUT
N VDD VSS PH10 PH11 PD14 PE13 PE8 PF11 PA6 PA4 PA0 VREF- VSSA
P VDD VSS PD10 PD9 PD8 PB15 PE14 PE11 PF13 PC5 PA5 PA3 VREF+
R VDD VSS PB14 VSSSMPS PB11 PE15 PE12 VSS PF15 VSS PA7 VSS VDDA
T VDD VDD11 PB12 PB13 VDDSMPS VLXSMPS PB10 VDD PE9 VDD PF12 PC4 VDD
MSv66061V1
112/390 DS13543 Rev 2

Figure 20. TFBGA216_DSI_SMPS pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PE0 PB7 PB6 PG15 PG12 PG9 PD4 PD3 PC10 PA15 PA14 PA8 PC8 VSS
PC14-
PH3-
B OSC32 PE4 PE1
BOOT0
PB5 PG13 PG10 PD5 PD2 PC11 PH7 PH5 PA12 PA11 PC7
_IN
PC15-
C OSC32 VBAT PE3 PI5 PB9 PB8 PG11 PD6 PD1 PC12 PH6 PH4 PA13 PC9 PC6
_OUT
D PJ3 PJ2 PE5 PI7 PI6 PB4 PG14 PD7 PD0 PH8 PH2 PA10 PG7 PG6 PG3
E PJ7 PJ6 PJ4 PE6 PE2 VDD11 PB3 VDDIO2 VDDUSB VSS VDD11 PA9 PG8 PG5 PJ0
VDD11
F PJ10 PJ8 PJ5 PC13 VDD VSS VSS VDD VSS VSS
USB
PG4 PI15 PI14 PI13
G DSI_D0P DSI_D0N PJ11 PJ1 VDDDSI VSSDSI VSS VDDIO2 PG2 PI12 PI11 PI10
VDD11
H DSI_CKP VSSDSI PF0 PJ9
DSI
VSSDSI VSS VDD PI9 PI8 PI4 VSS
J DSI_CKN VSSDSI PF2 PF1 VDD VSS VSS VDD PI1 PI2 PI3 VSS
K DSI_D1N DSI_D1P PF4 PF3 VREF- VSSA VSS VSS VSS VSS VDD PD15 PH14 PH15 PI0
L PF10 PF5 PF7 PF9 VREF+ VDDA VDD VDD VDD VSS VDD PD11 PH10 PH11 PH13
M PC1 PF6 PF8 PA2 PA4 PB1 PF13 PE8 PE13 PB11 PB12 PB13 PD12 PH9 PH12
PH0- PH1-OSC OPAMP2_

N OSC_IN _OUT
PC3 PA0
VINM
PB0 PF12 PG1 PE7 PE15 PE12 PB10 PD8 PD13 PD14
VSS
P PC2 PC0 PA1 PA3 PA6 PC5 PF11 PF15 PE9 PE10 PE11
SMPS
PB14 PD10 PD9
OPAMP1_ VDD
R VSS NRST
VINM
PA5 PA7 PC4 PB2 PF14 PG0 PE14 VLXSMPS
SMPS
VDD11 PB15 VSS
MSv66080V1
DS13543 Rev 2 113/390

180
4.2 Pin description

Table 26. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function
Pin name
during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/output pin
FT 5V-tolerant I/O
TT 3.6V-tolerant I/O
DSI 1.2 V I/O for DSI interface
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os(1)
_a I/O, with analog switch function supplied by VDDA
_c I/O with USB Type-C power delivery function
_d I/O with USB Type-C power delivery dead battery function
I/O structure
_f I/O, Fm+ capable
_h I/O with high-speed low-voltage mode
_o I/O with OSC32_IN/OSC32_OUT capability
_p I/O with differential clock capability CLKP/CLKN
_s I/O supplied only by VDDIO2
_t I/O with a function supplied by VSW
_u I/O, with USB function supplied by VDDUSB
_v I/O very high-speed capable
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.
114/390 DS13543 Rev 2

STM32U5Axxx
Table 27. STM32U5Axxx pin/ball definitions(1)
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP64 SMPS
Pin name
Pin type
UFBGA132
Additional
Notes
TFBGA169
LQFP100
LQFP144
(function Alternate functions
LQFP64
functions
after reset)
TRACECLK,
TIM3_ETR, SAI1_CK1,
USART6_CK, LCD_R0,
TSC_G7_IO1,
- 1 B3 1 A13 D10 A1 G20 E5 - 1 B3 1 A1 PE2 I/O FT_ha - -
LPGPIO1_P14,
DS13543 Rev 2
FMC_A23,
SAI1_MCLK_A,
EVENTOUT
TRACED0, TIM3_CH1,
Pinout, pin description and alternate functions

OCTOSPIM_P1_DQS,
USART6_CTS,
LCD_R1,
TAMP_IN6/
- 2 A2 2 D10 G9 D3 E22 C3 - 2 A2 2 D3 PE3 I/O FT_hat - TSC_G7_IO2,
TAMP_OUT3
LPGPIO1_P15,
FMC_A19,
SAI1_SD_B,
EVENTOUT
TRACED1, TIM3_CH2,
SAI1_D2, MDF1_SDI3,
USART6_RTS_DE,
WKUP1,
LCD_B0,
- 3 B2 3 F10 J9 C2 F21 B2 - 3 B2 3 C2 PE4 I/O FT_hat - TAMP_IN7/
TSC_G7_IO3,
TAMP_OUT8
DCMI_D4/PSSI_D4,
FMC_A20, SAI1_FS_A,
EVENTOUT
115/390
Table 27. STM32U5Axxx pin/ball definitions(1) (continued)
116/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
LQFP64 SMPS Pin name
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TRACED2, TIM3_CH3,
SAI1_CK2,
MDF1_CKI3, LCD_G0,
WKUP2,
TSC_G7_IO4,
- 4 A1 4 H10 F10 D2 G22 D3 - 4 A1 4 D2 PE5 I/O FT_hat - TAMP_IN8/
DCMI_D6/PSSI_D6,
TAMP_OUT7
FMC_A21,
DS13543 Rev 2
SAI1_SCK_A,
EVENTOUT
TRACED3, TIM3_CH4,
SAI1_D1, LCD_G1,
WKUP3,
DCMI_D7/PSSI_D7,
- 5 C2 5 E11 D12 E4 C24 E4 - 5 C2 5 E4 PE6 I/O FT_ht - TAMP_IN3/
FMC_A22,
TAMP_OUT6
SAI1_SD_A,
EVENTOUT
1 6 B1 6 C13 C13 C1 B25 C2 1 6 B1 6 C1 VBAT S - - - -
- - - - - - F2 B11 A1 - - - - F2 VSS S - - - -
WKUP2,
(2) RTC_TS/
2 7 C3 7 D12 E11 E3 D23 F4 2 7 C3 7 E3 PC13 I/O FT (3) EVENTOUT RTC_OUT1,
TAMP_IN1/T
AMP_OUT2
STM32U5Axxx
PC14- (2)
3 8 C1 8 E13 A13 D1 C26 B1 3 8 C1 8 D1 OSC32_IN I/O FT_o (3) EVENTOUT OSC32_IN
(PC14)
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
PC15-
OSC32_ (2)
4 9 D1 9 G13 B12 E1 D25 C1 4 9 D1 9 E1 I/O FT_o (3) EVENTOUT OSC32_OUT
OUT
(PC15)
I2C6_SDA, I2C2_SDA,
OCTOSPIM_P2_IO0,
DS13543 Rev 2
- - D2 10 G11 G11 E2 H19 H3 - - D2 10 E2 PF0 I/O FT_fh - -

USART6_TX, FMC_A0,
EVENTOUT
I2C6_SCL, I2C2_SCL,

OCTOSPIM_P2_IO1,
- - E2 11 H12 H10 F3 H21 J4 - - E2 11 F3 PF1 I/O FT_fh - -
USART6_RX,
FMC_A1, EVENTOUT
LPTIM3_CH2,
I2C2_SMBA,
- - E1 12 J13 F12 F4 J20 J3 - - E1 12 F4 PF2 I/O FT_h - OCTOSPIM_P2_IO2, WKUP8
USART6_CK,
FMC_A2, EVENTOUT
LPTIM3_IN1,
ADF1_CCK0,
OCTOSPIM_P2_IO3,
- - D3 13 K12 L11 G5 K23 K4 - - D3 13 G5 PF3 I/O FT_h - MDF1_CCK0, -
USART6_CTS,
UART5_TX, FMC_A3,
EVENTOUT
117/390
118/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM3_ETR,
ADF1_SDI0,
OCTOSPIM_P2_CLK,
- - E3 14 J11 N11 G6 J22 K3 - - E3 14 G6 PF4 I/O FT_hvp - MDF1_SDI0, -
USART6_RTS_DE,
UART5_RX, FMC_A4,
DS13543 Rev 2
EVENTOUT
LPTIM3_CH1,
OCTOSPIM_P2_NCLK
- - F2 15 L11 R11 G4 K21 L2 - - F2 15 G4 PF5 I/O FT_hvp - -
, MDF1_CKI0,
FMC_A5, EVENTOUT
- 10 F6 16 F12 - H2 B15 A15 - 10 F6 16 H2 VSS S - - - -
- 11 F7 17 L13 A11 G1 L26 F5 - 11 F7 17 G1 VDD S - - - -
TIM5_ETR, TIM5_CH1,
DCMI_D12/PSSI_D12,
OCTOSPIM_P2_NCS,
- - - 18 N11 J11 H6 J16 M2 - - - 18 H6 PF6 I/O FT_h - -
OCTOSPIM_P1_IO3,
SAI1_SD_B,
EVENTOUT
TIM5_CH2,
FDCAN1_RX,
STM32U5Axxx
- - - 19 N13 K10 G2 J14 L3 - - - 19 G2 PF7 I/O FT_h - OCTOSPIM_P1_IO2, -
SAI1_MCLK_B,
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM5_CH3, PSSI_D14,
FDCAN1_TX,
- - - 20 P10 M10 F1 K19 M3 - - - 20 F1 PF8 I/O FT_h - OCTOSPIM_P1_IO0, -
SAI1_SCK_B,
EVENTOUT
TIM5_CH4, PSSI_D15,
DS13543 Rev 2
OCTOSPIM_P1_IO1,
- - - 21 P12 L9 G3 L20 L4 - - - 21 G3 PF9 I/O FT_h - SAI1_FS_B, -
TIM15_CH1,
EVENTOUT

OCTOSPIM_P1_CLK,
PSSI_D15,
MDF1_CCK1,
- - - 22 R11 K8 H4 L22 L1 - - - 22 H4 PF10 I/O FT_hv - DCMI_D11/PSSI_D11, -
DSI_TE, SAI1_D3,
TIM15_CH2,
EVENTOUT
PH0-
5 12 F1 23 R13 W13 H1 M23 N1 5 12 F1 23 H1 OSC_IN I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-
6 13 G1 24 U13 V12 J1 M25 N2 6 13 G1 24 J1 OSC_OUT I/O FT - EVENTOUT OSC_OUT
(PH1)
7 14 G2 25 T12 U11 H3 M21 R2 7 14 G2 25 H3 NRST I-O RST - - -
119/390
120/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_IN1,
OCTOSPIM_P1_IO7,
I2C3_SCL(boot),
SPI2_RDY,
MDF1_SDI4, ADC1_IN1,
8 15 H2 26 N9 P10 J2 K17 P2 8 15 H2 26 J2 PC0 I/O FT_fha - USART6_CTS, ADC2_IN1,
DS13543 Rev 2
LPUART1_RX, ADC4_IN1
SDMMC1_D5,
SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
TRACED0,
LPTIM1_CH1,
SPI2_MOSI,
I2C3_SDA(boot),
MDF1_CKI4, ADC1_IN2,
9 16 G3 27 M8 L7 J3 K15 M1 9 16 G3 27 J3 PC1 I/O FT_fhav - USART6_CK, ADC2_IN2,
LPUART1_TX, ADC4_IN2
OCTOSPIM_P1_IO4,
SDMMC2_CK,
SAI1_SD_A,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_IN2,
SPI2_MISO,
MDF1_CCK1, ADC1_IN3,
10 17 F3 28 V12 Y12 J4 L18 P1 10 17 F3 28 J4 PC2 I/O FT_ha - USART6_RX, ADC2_IN3,
OCTOSPIM_P1_IO5, ADC4_IN3
LPGPIO1_P5,
DS13543 Rev 2
EVENTOUT
LPTIM1_ETR,
LPTIM3_CH1,
SAI1_D1, SPI2_MOSI,

ADC1_IN4,
USART6_TX,
11 18 F4 29 U11 T10 K1 M19 N3 11 18 F4 29 K1 PC3 I/O FT_ha - ADC2_IN4,
OCTOSPIM_P1_IO6,
ADC4_IN4
SAI1_SD_A,
LPTIM2_ETR,
EVENTOUT
12 19 H1 30 W13 AA13 K2 N26 K6 12 19 H1 30 K2 VSSA S - - - -
- - - - - - - N24 K5 - 20 - 31 - VREF- S - - - -
VREFBUF
- 20 J1 31 Y12 AB12 L1 P25 L5 - 21 J1 32 L1 VREF+ S - - -
_OUT
13 21 K1 32 AA13 AC13 L2 R26 L6 13 22 K1 33 L2 VDDA S - - - -
121/390
122/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM2_CH1, TIM5_CH1,
TIM8_ETR, SPI3_RDY, OPAMP1
USART2_CTS, _VINP,
UART4_TX, ADC1_IN5,
14 22 J2 33 T10 W11 K3 N22 N4 14 23 J2 34 K3 PA0 I/O FT_hat - OCTOSPIM_P2_NCS, ADC2_IN5,
SDMMC2_CMD, WKUP1,
DS13543 Rev 2
AUDIOCLK, TAMP_IN2/T
TIM2_ETR, AMP_OUT1
EVENTOUT
OPAMP1_V
- - H3 - - - M1 - R3 - - H3 - M1 I TT - - -
INM
LPTIM1_CH2,
TIM2_CH2, TIM5_CH2,
OPAMP1
I2C1_SMBA,
_VINM,
SPI1_SCK,
ADC1_IN6,
USART2_RTS_DE,
15 23 G4 34 W11 V10 L3 L16 P3 15 24 G4 35 L3 PA1 I/O FT_hat - ADC2_IN6,
UART4_RX,
WKUP3,
OCTOSPIM_P1_DQS,
TAMP_IN5/
LPGPIO1_P0,
TAMP_OUT4
TIM15_CH1N,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM2_CH3, TIM5_CH3,
SPI1_RDY, COMP1
USART2_TX(boot), _INP3,
LPUART1_TX, ADC1_IN7,
16 24 K2 35 R9 R9 M2 M17 M4 16 25 K2 36 M2 PA2 I/O FT_ha -
OCTOSPIM_P1_NCS, ADC2_IN7,
UCPD1_FRSTX1, WKUP4/
DS13543 Rev 2
TIM15_CH1, LSCO
EVENTOUT
TIM2_CH4, TIM5_CH4,
SAI1_CK1,

USART2_RX(boot), OPAMP1
LPUART1_RX, _VOUT,
17 25 L1 36 V10 N9 N2 P23 P4 17 26 L1 37 N2 PA3 I/O TT_hav - OCTOSPIM_P1_CLK, ADC1_IN8,
LPGPIO1_P1, ADC2_IN8,
SAI1_MCLK_A, WKUP5
TIM15_CH2,
EVENTOUT
18 26 G7 37 AC13 AB10 M3 B23 E10 18 27 G7 38 M3 VSS S - - - -
19 27 G6 38 AB12 A3 N3 T25 F8 19 28 G6 39 N3 VDD S - - - -
OCTOSPIM_P1_NCS,
SPI1_NSS(boot),
ADC1_IN9,
SPI3_NSS,
ADC2_IN9,
USART2_CK,
20 28 L3 39 P8 M8 N1 N20 M5 20 29 L3 40 N1 PA4 I/O TT_ha - ADC4_IN9,
DCMI_HSYNC/PSSI_D
DAC1_OUT1
E, SAI1_FS_B,
, WKUP2
123/390
LPTIM2_CH1,
EVENTOUT
124/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
CSLEEP, TIM2_CH1,
TIM2_ETR,
ADC1_IN10,
TIM8_CH1N,
ADC2_IN10,
PSSI_D14,
21 29 M1 40 AA11 AA11 K4 P21 R4 21 30 M1 41 K4 PA5 I/O TT_a - ADC4_IN10,
SPI1_SCK(boot),
DAC1_OUT2
USART3_RX,
, WKUP6
DS13543 Rev 2
LPTIM2_ETR,
EVENTOUT
CDSTOP, TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
DCMI_PIXCLK/PSSI_P OPAMP2
DCK, _VINP,
SPI1_MISO(boot), ADC1_IN11,
22 30 L2 41 U9 U9 N4 N18 P5 22 31 L2 42 N4 PA6 I/O FT_ha -
USART3_CTS, ADC2_IN11,
LPUART1_CTS, ADC4_IN11,
OCTOSPIM_P1_IO3, WKUP7
LPGPIO1_P2,
TIM16_CH1,
EVENTOUT
OPAMP2
- - M2 - - - H5 - N5 - - M2 - H5 I TT - - -
_VINM
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
SRDSTOP,
TIM1_CH1N,
TIM3_CH2,
OPAMP2
TIM8_CH1N,
_VINM,
I2C3_SCL,
ADC1_IN12,
23 31 K3 42 Y10 P8 J5 R22 R5 23 32 K3 43 J5 PA7 I/O FT_fha - SPI1_MOSI(boot),
ADC2_IN12,
DS13543 Rev 2
USART3_TX,
ADC4_IN20,
OCTOSPIM_P1_IO2,
WKUP8
LPTIM2_CH2,
TIM17_CH1,

EVENTOUT
COMP1
I2C6_SMBA,
_INM2,
USART3_TX,
- - M3 - AC11 T8 L4 T23 R6 24 33 M3 44 L4 PC4 I/O FT_ha - ADC1_IN13,
OCTOSPIM_P1_IO7,
ADC2_IN13,
EVENTOUT
ADC4_IN22
COMP1
_INP1,
TIM1_CH4N, SAI1_D3, ADC1_IN14,
PSSI_D15, ADC2_IN14,
- - J3 - N7 N7 M4 P19 P6 25 34 J3 45 M4 PC5 I/O FT_at -
USART3_RX, ADC4_IN23,
EVENTOUT WKUP5,
TAMP_IN4/T
AMP_OUT5
125/390
126/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
LPTIM3_CH1, OPAMP2
SPI1_NSS, _VOUT,
24 32 M4 43 T8 Y10 K5 H13 N6 26 35 M4 46 K5 PB0 I/O TT_ha - USART3_CK, ADC1_IN15,
DS13543 Rev 2
OCTOSPIM_P1_IO1, ADC2_IN15,
LPGPIO1_P9, ADC4_IN18
COMP1_OUT,
AUDIOCLK,
EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
COMP1
LPTIM3_CH2,
_INM1,
MDF1_SDI0,
ADC1_IN16,
25 33 L4 44 W9 W9 N5 L14 M6 27 36 L4 47 N5 PB1 I/O FT_ha - USART3_RTS_DE,
ADC2_IN16,
LPUART1_RTS_DE,
ADC4_IN19,
OCTOSPIM_P1_IO0,
WKUP4
LPGPIO1_P3,
LPTIM2_IN1,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_CH1,
TIM8_CH4N, COMP1
I2C3_SMBA, _INP2,
SPI1_RDY, ADC1_IN17,
26 34 K4 45 AB10 M6 L5 M15 R7 28 37 K4 48 L5 PB2 I/O FT_hat -
MDF1_CKI0, LCD_B1, ADC2_IN17,
OCTOSPIM_P1_DQS, WKUP1,
DS13543 Rev 2
UCPD1_FRSTX1, RTC_OUT2
EVENTOUT
OCTOSPIM_P1_NCLK
, LCD_DE,

- - K5 46 R7 R7 M5 N16 P7 - - K5 49 M5 PF11 I/O FT_hv - DCMI_D12/PSSI_D12, -
DSI_TE, LPTIM4_IN1,
EVENTOUT
OCTOSPIM_P2_DQS,
LCD_B0, FMC_A6,
- - L5 47 V8 V8 K6 T21 N7 - - L5 50 K6 PF12 I/O FT_h - -
LPTIM4_ETR,
EVENTOUT
- - - 48 AA9 AB8 M7 B5 F10 - - - 51 M7 VSS S - - - -
- - - 49 AC9 A7 N7 T19 J5 - - - 52 N7 VDD S - - - -
I2C4_SMBA, LCD_B1,
UCPD1_FRSTX2,
- - M5 50 P6 AA9 M6 P17 M7 - - M5 53 M6 PF13 I/O FT_h - FMC_A7, -
LPTIM4_OUT,
EVENTOUT
127/390
128/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
I2C4_SCL, LCD_G0,
- - J5 51 U7 Y8 L6 K13 R8 - - J5 54 L6 PF14 I/O FT_fha - TSC_G8_IO1, ADC4_IN5
FMC_A8, EVENTOUT
I2C4_SDA, LCD_G1,
- - L6 52 Y8 U7 N6 R18 P8 - - L6 55 N6 PF15 I/O FT_fha - TSC_G8_IO2, ADC4_IN6
FMC_A9, EVENTOUT
DS13543 Rev 2
OCTOSPIM_P2_IO4,
- - M6 53 T6 P6 J6 H11 R9 - - M6 56 J6 PG0 I/O FT_ha - TSC_G8_IO3, ADC4_IN7
FMC_A10, EVENTOUT
OCTOSPIM_P2_IO5,
- - K6 54 W7 W7 H7 J12 N8 - - K6 57 H7 PG1 I/O FT_ha - TSC_G8_IO4, ADC4_IN8
FMC_A11, EVENTOUT
TIM1_ETR,
MDF1_SDI2, LCD_B6,
- 35 K7 55 AB8 T6 L7 L12 N9 - 38 K7 58 L7 PE7 I/O FT_h - WKUP6
FMC_D4, SAI1_SD_B,
EVENTOUT
TIM1_CH1N,
MDF1_CKI2, LCD_B7,
- 36 J6 56 V6 AA7 K7 N14 M8 - 39 J6 59 K7 PE8 I/O FT_h - FMC_D5, WKUP7
SAI1_SCK_B,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM1_CH1,
ADF1_CCK0,
MDF1_CCK0,
LCD_G2,
- 37 M7 57 U5 V6 J7 T17 P9 - 40 M7 60 J7 PE9 I/O FT_hv - -
OCTOSPIM_P1_NCLK
, FMC_D6,
DS13543 Rev 2
SAI1_FS_B,
EVENTOUT
- - - 58 AA7 C11 - E4 F6 - - - 61 - VSS S - - - -

- - J4 59 AC7 AC1 - T15 L7 - - J4 62 - VDD S - - - -
TIM1_CH2N,
ADF1_SDI0,
MDF1_SDI4, LCD_G3,
TSC_G5_IO1,
- 38 J7 60 Y6 R5 H8 M13 P10 - 41 J7 63 H8 PE10 I/O FT_hav - -
OCTOSPIM_P1_CLK,
FMC_D7,
SAI1_MCLK_B,
EVENTOUT
TIM1_CH2, SPI1_RDY,
MDF1_CKI4, LCD_G4,
- 39 L7 61 W5 U5 M8 P15 P11 - 42 L7 64 M8 PE11 I/O FT_ha - TSC_G5_IO2, -
OCTOSPIM_P1_NCS,
FMC_D8, EVENTOUT
129/390
130/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM1_CH3N,
SPI1_NSS,
MDF1_SDI5, LCD_G5,
- 40 J8 62 V4 Y6 N8 R14 N11 - 43 J8 65 N8 PE12 I/O FT_ha - -
TSC_G5_IO3,
OCTOSPIM_P1_IO0,
FMC_D9, EVENTOUT
DS13543 Rev 2
TIM1_CH3, SPI1_SCK,
MDF1_CKI5, LCD_G6,
- 41 M8 63 Y4 AB6 L8 N12 M9 - 44 M8 66 L8 PE13 I/O FT_ha - TSC_G5_IO4, -
OCTOSPIM_P1_IO1,
FMC_D10, EVENTOUT
TIM1_CH4,
TIM1_BKIN2,
- 42 K8 64 AB6 P4 K8 P13 R10 - 45 K8 67 K8 PE14 I/O FT_h - SPI1_MISO, LCD_G7, -
OCTOSPIM_P1_IO2,
FMC_D11, EVENTOUT
TIM1_BKIN,
TIM1_CH4N,
- 43 L8 65 AA5 T4 M9 R12 N10 - 46 L8 68 M9 PE15 I/O FT_h - SPI1_MOSI, LCD_R2, -
OCTOSPIM_P1_IO3,
FMC_D12, EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM2_CH3,
LPTIM3_CH1,
I2C4_SCL,
I2C2_SCL(boot),
SPI2_SCK,
USART3_TX,
DS13543 Rev 2
27 44 K9 66 W3 W5 K9 T13 N12 29 47 K9 69 K9 PB10 I/O FT_fhv - LPUART1_RX, WKUP8

TSC_SYNC,
OCTOSPIM_P1_CLK,
LPGPIO1_P4,

COMP1_OUT,
SAI1_SCK_A,
EVENTOUT
TIM2_CH4, I2C4_SDA,
I2C2_SDA(boot),
SPI2_RDY,
USART3_RX,
- 45 L9 67 AA3 AA5 L9 R10 M10 - - L9 - L9 PB11 I/O FT_fh - -
LPUART1_TX,
OCTOSPIM_P1_NCS,
COMP2_OUT,
EVENTOUT
28 46 M10 68 AC5 AC5 N9 T11 R11 - - - - - VLXSMPS S - - - -
29 47 M9 69 AB4 AB4 N10 T9 R12 - - - - - VDDSMPS S - - - -
30 48 L10 70 AC3 AC3 M10 R8 P12 - - - - - VSSSMPS S - - - -
131/390
- - - - - - - - - 30 48 L10 70 N11 VCAP S - - - -

31 49 M11 71 AB2 AB2 N11 T3 R13 - - - - - VDD11 S - - - -
132/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
32 50 E9 72 AA1 C3 M11 F3 F7 31 49 E9 71 M11 VSS S - - - -

33 51 D4 73 AC1 AC11 N12 P1 L8 32 50 D4 72 N12 VDD S - - - -
- - - - - - - T1 - - - - - - VDD S - - - -
TIM1_BKIN,
I2C6_SMBA,
DS13543 Rev 2
I2C2_SMBA,
SPI2_NSS(boot),
MDF1_SDI1,
USART3_CK,
- - L11 - Y2 AA3 L10 T5 M11 33 51 L11 73 L10 PB12 I/O FT_hav - -
LPUART1_RTS_DE,
TSC_G1_IO1,
OCTOSPIM_P1_NCLK
, SAI2_FS_A,
TIM15_BKIN,
EVENTOUT
TIM1_CH1N,
LPTIM3_IN1,
I2C2_SCL,
SPI2_SCK(boot),
MDF1_CKI1,
34 52 K10 74 R5 Y4 N13 T7 M12 34 52 K10 74 N13 PB13 I/O FT_fa - USART3_CTS, -
LPUART1_CTS,
STM32U5Axxx
TSC_G1_IO2,
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM1_CH2N,
LPTIM3_ETR,
TIM8_CH2N,
I2C2_SDA,
SPI2_MISO(boot),
MDF1_SDI2, UCPD1_
35 53 K11 75 T4 V4 M12 R6 P13 35 53 K11 75 M12 PB14 I/O FT_fda -
DS13543 Rev 2
USART3_RTS_DE, DBCC2
TSC_G1_IO3,
SDMMC2_D0,
SAI2_MCLK_A,

TIM15_CH1,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
LPTIM2_IN2,
TIM8_CH3N,
SPI2_MOSI(boot),
(4) UCPD1_CC2
36 54 K12 76 N5 Y2 L11 P11 R14 36 54 K12 76 L11 PB15 I/O FT_c MDF1_CKI2,
, WKUP7
FMC_NBL1,
SDMMC2_D1,
SAI2_SD_A,
TIM15_CH2,
EVENTOUT
- - - - - H12 - G24 G5 - - - - - VDDDSI S - - - -
- - - - - M12 - J24 H5 - - - - - VDD11DSI S - - - -
133/390
- - - - - E13 - E26 G1 - - - - - DSI_D0P I/O DSI - - -

134/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
- - - - - G13 - F25 G2 - - - - - DSI_D0N I/O DSI - - -

- - - - - K12 - E24 G6 - - - - - VSSDSI S - - - -
- - - - - - - H23 H6 - - - - - VSSDSI S - - - -
- - - - - J13 - G26 H1 - - - - - DSI_CKP I/O DSI - - -
DS13543 Rev 2
- - - - - L13 - H25 J1 - - - - - DSI_CKN I/O DSI - - -

- - - - - N13 - J26 K2 - - - - - DSI_D1P I/O DSI - - -
- - - - - R13 - K25 K1 - - - - - DSI_D1N I/O DSI - - -
- - - - - P12 - F23 H2 - - - - - VSSDSI S - - - -
- - - - - - - - J2 - - - - - VSSDSI S - - - -
USART3_TX, LCD_R3,
DCMI_HSYNC/PSSI_D
- 55 L12 77 W1 W3 L12 P9 N13 - 55 L12 77 L12 PD8 I/O FT_h - -
E, FMC_D13,
EVENTOUT
LPTIM2_IN2,
USART3_RX, LCD_R4,
DCMI_PIXCLK/PSSI_P
- 56 J10 78 V2 U3 L13 P7 P15 - 56 J10 78 L13 PD9 I/O FT_h - DCK, FMC_D14, -
SAI2_MCLK_A,
STM32U5Axxx
LPTIM3_IN1,
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM2_CH2,
I2C5_SMBA,
USART3_CK, LCD_R5,
TSC_G6_IO1,
- 57 M12 79 U3 W1 K11 P5 P14 - 57 M12 79 K11 PD10 I/O FT_ha - -
FMC_D15,
SAI2_SCK_A,
DS13543 Rev 2
LPTIM3_ETR,
EVENTOUT
I2C4_SMBA,
USART3_CTS,

LCD_R6,
TSC_G6_IO2,
- 58 J11 80 P4 R3 M13 M11 L12 - 58 J11 80 M13 PD11 I/O FT_ha - ADC4_IN15
FMC_CLE/FMC_A16,
SAI2_SD_A,
LPTIM2_ETR,
EVENTOUT
TIM4_CH1, I2C4_SCL,
USART3_RTS_DE,
LCD_R7,
TSC_G6_IO3,
- 59 J12 81 R3 T2 K10 L10 M13 - 59 J12 81 K10 PD12 I/O FT_fha - ADC4_IN16
FMC_ALE/FMC_A17,
SAI2_FS_A,
LPTIM2_IN1,
EVENTOUT
135/390
136/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM4_CH2, I2C4_SDA,
USART6_CTS,
LCD_VSYNC,
TSC_G6_IO4,
- 60 H11 82 U1 N3 K12 K11 N14 - 60 H11 82 K12 PD13 I/O FT_fha - LPGPIO1_P6, ADC4_IN17
FMC_A18,
DS13543 Rev 2
LPTIM4_IN1,
LPTIM2_CH1,
EVENTOUT
- - - 83 T2 C7 J12 G4 F9 - - - 83 J12 VSS S - - - -
- - - 84 R1 AC9 A11 R2 L9 - - - 84 J13 VDD S - - - -
TIM4_CH3,
USART6_CK, LCD_B2,
- 61 H10 85 N3 P2 J10 N10 N15 - 61 H10 85 J10 PD14 I/O FT_h - FMC_D0, -
LPTIM3_CH1,
EVENTOUT
TIM4_CH4,
USART6_RTS_DE,
- 62 H12 86 P2 R1 J11 K9 K12 - 62 H12 86 J11 PD15 I/O FT_h - LCD_B3, FMC_D1, -
LPTIM3_CH2,
EVENTOUT
STM32U5Axxx
SPI1_SCK, FMC_A12,
- - G10 87 N1 N1 K13 F9 G12 - - G10 87 K13 PG2 I/O FT_hs - SAI2_SCK_B, -
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
SPI1_MISO,
- - G11 88 M4 L1 J8 H9 D15 - - G11 88 J8 PG3 I/O FT_hs - FMC_A13, SAI2_FS_B, -
EVENTOUT
SPI1_MOSI,
FMC_A14,
- - G9 89 M2 M2 H11 J10 F12 - - G9 89 H11 PG4 I/O FT_hs - -
SAI2_MCLK_B,
DS13543 Rev 2
EVENTOUT
SPI1_NSS,
LPUART1_CTS,

- - G12 90 L3 L3 J9 G12 E14 - - G12 90 J9 PG5 I/O FT_hs - DSI_TE, FMC_A15, -
SAI2_SD_B,
EVENTOUT
OCTOSPIM_P1_DQS,
I2C3_SMBA,
SPI1_RDY, LCD_R1,
- - F9 91 M6 M4 H10 G10 D14 - - F9 91 H10 PG6 I/O FT_hs - -
LPUART1_RTS_DE,
UCPD1_FRSTX1,
EVENTOUT
SAI1_CK1, I2C3_SCL,
OCTOSPIM_P2_DQS,
MDF1_CCK0,
LPUART1_TX,
- - F10 92 L1 J1 G8 G14 D13 - - F10 92 G8 PG7 I/O FT_fhs - -
UCPD1_FRSTX2,
FMC_INT,
SAI1_MCLK_A,
137/390
EVENTOUT
138/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
I2C3_SDA,
- - F12 93 K4 K2 H9 F11 E13 - - F12 93 H9 PG8 I/O FT_fs - LPUART1_RX, -
EVENTOUT
- - - 94 K2 - - N4 G10 - - - 94 - VSS S - - - -
- - - 95 J1 G1 H12 E2 G11 - - - 95 H12 VDDIO2 S - - - -
DS13543 Rev 2
CSLEEP, TIM3_CH1,
TIM8_CH1,
MDF1_CKI3, LCD_R0,
SDMMC1_D0DIR,
TSC_G4_IO1,
37 63 F11 96 J3 N5 H13 D5 C15 37 63 F11 96 H13 PC6 I/O FT_a - -
DCMI_D0/PSSI_D0,
SDMMC2_D6,
SDMMC1_D6,
SAI2_MCLK_A,
EVENTOUT
CDSTOP, TIM3_CH2,
TIM8_CH2,
MDF1_SDI3, LCD_R1,
SDMMC1_D123DIR,
TSC_G4_IO2,
38 64 E10 97 L5 J3 G12 D3 B15 38 64 E10 97 G12 PC7 I/O FT_a - DCMI_D1/PSSI_D1, -
SDMMC2_D7,
STM32U5Axxx
SDMMC1_D7,
SAI2_MCLK_B,
LPTIM2_CH2,
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
SRDSTOP, TIM3_CH3,
TIM8_CH3,
USART6_RX,
TSC_G4_IO3,
39 65 E12 98 G1 K4 G10 D7 A14 39 65 E12 98 G10 PC8 I/O FT_a - -
DCMI_D2/PSSI_D2,
SDMMC1_D0,
DS13543 Rev 2
LPTIM3_CH1,
EVENTOUT
TRACED0,
TIM8_BKIN2,

TIM3_CH4, TIM8_CH4,
DCMI_D3/PSSI_D3,
40 66 E11 99 H2 L5 G9 D9 C14 40 66 E11 99 G9 PC9 I/O FT_a - USART6_TX, -
TSC_G4_IO4,
SDMMC1_D1,
LPTIM3_CH2,
EVENTOUT
MCO, TIM1_CH1,
SAI1_CK2, SPI1_RDY,
USART1_CK,
OTG_HS_SOF,
41 67 D12 100 G3 H4 G7 C8 A13 41 67 D12 100 G7 PA8 I/O FT_hv - -
TRACECLK,
SAI1_SCK_A,
LPTIM2_CH1,
EVENTOUT
139/390
140/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM1_CH2, SPI2_SCK,
DCMI_D0/PSSI_D0,
USART1_TX(boot), OTG_HS
42 68 D10 101 F2 F2 G11 C6 E12 42 68 D10 101 G11 PA9 I/O FT_u -
SAI1_FS_A, _VBUS
TIM15_BKIN,
EVENTOUT
DS13543 Rev 2
CRS_SYNC,
TIM1_CH3,
LPTIM2_IN2, SAI1_D1,
DCMI_D1/PSSI_D1,
43 69 D11 102 E3 G3 F11 C4 D12 43 69 D11 102 F11 PA10 I/O FT_u - USART1_RX(boot), -
OTG_HS_ID,
SAI1_SD_A,
TIM17_BKIN,
EVENTOUT
- - - - - - - D1 F11 - - - - - VDD11USB S - - - -
TIM1_CH4,
TIM1_BKIN2,
(5) SPI1_MISO, OTG_HS_
44 70 C12 103 E1 E1 G13 C2 B14 44 70 C12 103 G13 PA11 I/O TT
USART1_CTS, DM(boot)
FDCAN1_RX,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM1_ETR,
SPI1_MOSI,
45 71 B12 104 C1 C1 F13 B1 B13 45 71 B12 104 F13 PA12 I/O TT (5) OCTOSPIM_P2_NCS, OTG_HS_
USART1_RTS_DE, DP(boot)
FDCAN1_TX,
EVENTOUT
DS13543 Rev 2
PA13 JTMS/SWDIO,
(6)
46 72 C10 105 D2 E3 F12 B3 C13 46 72 C10 105 F12 (JTMS/ I/O FT IR_OUT, SAI1_SD_B, -
SWDIO) EVENTOUT

47 - - - C3 AA1 - P3 - 47 - - - - VSS S - - - -
48 73 A12 106 A1 A1 E13 A2 E9 48 73 A12 106 E13 VDDUSB S - - - -
- 74 H4 107 - D2 E12 R16 H10 - 74 H4 107 E12 VSS S - - - -
- 75 D9 108 - U1 D13 A6 - - 75 D9 108 D13 VDD S - - - -
JTCK/SWCLK,
LPTIM1_CH1,
PA14 I2C1_SMBA,
(6)
49 76 C11 109 H4 F4 C10 D11 A12 49 76 C11 109 C10 (JTCK/ I/O FT I2C4_SMBA, -
SWCLK) OTG_HS_SOF,
SAI1_FS_B,
EVENTOUT
141/390
142/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
JTDI, TIM2_CH1,
TIM2_ETR,
USART2_RX,
(4)
SPI1_NSS, SPI3_NSS,
50 77 A11 110 F4 B4 A10 A8 A11 50 77 A11 110 A10 PA15 (JTDI) I/O FT_c (6) UCPD1_CC1
USART3_RTS_DE,
UART4_RTS_DE,
DS13543 Rev 2
SAI2_FS_B,
EVENTOUT
TRACED1,
LPTIM3_ETR,
ADF1_CCK1,
SPI3_SCK,
USART3_TX(boot),
UART4_TX,
51 78 B11 111 D4 D4 C9 B9 A10 51 78 B11 111 C9 PC10 I/O FT_a - -
TSC_G3_IO2,
DCMI_D8/PSSI_D8,
LPGPIO1_P8,
SDMMC1_D2,
SAI2_SCK_B,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM3_IN1,
ADF1_SDI0,
DCMI_D2/PSSI_D2,
OCTOSPIM_P1_NCS,
SPI3_MISO,
USART3_RX(boot),
DS13543 Rev 2
52 79 A10 112 B4 J5 A9 C10 B10 52 79 A10 112 A9 PC11 I/O FT_ha - UART4_RX, -
TSC_G3_IO3,
DCMI_D4/PSSI_D4,
UCPD1_FRSTX2,

SDMMC1_D3,
SAI2_MCLK_B,
EVENTOUT
TRACED3,
SPI3_MOSI,
USART3_CK,
UART5_TX,
TSC_G3_IO4,
53 80 B10 113 J5 A5 E8 E14 C10 53 80 B10 113 E8 PC12 I/O FT_hav - -
DCMI_D9/PSSI_D9,
LPGPIO1_P10,
SDMMC1_CK,
SAI2_SD_B,
EVENTOUT
I2C6_SDA,
TIM8_CH4N,
- 81 C9 114 G5 C5 B9 F15 D9 - 81 C9 114 B9 PD0 I/O FT_fh - I2C5_SDA, SPI2_NSS, -
143/390
LCD_B4, FDCAN1_RX,
FMC_D2, EVENTOUT
144/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
I2C6_SCL, I2C5_SCL,
SPI2_SCK, LCD_B5,
- 82 B9 115 E5 E5 F6 A10 C9 - 82 B9 115 F6 PD1 I/O FT_fh - -
FDCAN1_TX,
FMC_D3, EVENTOUT
TRACED2, TIM3_ETR,
I2C5_SMBA,
DS13543 Rev 2
USART3_RTS_DE,
UART5_RX,
TSC_SYNC,
54 83 A9 116 C5 G5 F7 D13 B9 54 83 A9 116 F7 PD2 I/O FT - -
DCMI_D11/PSSI_D11,
LPGPIO1_P7,
SDMMC1_CMD,
LPTIM4_ETR,
EVENTOUT
I2C6_SMBA,
SPI2_SCK,
DCMI_D5/PSSI_D5,
SPI2_MISO,
MDF1_SDI0,
- 84 C8 117 A5 K6 D8 C12 A9 - 84 C8 117 D8 PD3 I/O FT_hv - -
USART2_CTS,
LCD_CLK,
OCTOSPIM_P2_NCS,
FMC_CLK,
STM32U5Axxx
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
SPI2_MOSI,
MDF1_CKI0,
USART2_RTS_DE,
- 85 B8 118 H6 B6 C8 D15 A8 - 85 B8 118 C8 PD4 I/O FT_h - -
OCTOSPIM_P1_IO4,
FMC_NOE,
EVENTOUT
DS13543 Rev 2
SPI2_RDY,
USART2_TX,
- 86 A8 119 F6 D6 E7 E16 B8 - 86 A8 119 E7 PD5 I/O FT_h - OCTOSPIM_P1_IO5, -
FMC_NWE,

EVENTOUT
- - - 120 D6 H2 B8 R20 H15 - - - 120 B8 VSS S - - - -
- - - 121 B6 U13 A8 A12 - - - - 121 A8 VDD S - - - -
SAI1_D1,
DCMI_D10/PSSI_D10,
SPI3_MOSI,
MDF1_SDI1,
USART2_RX,
- 87 A7 122 K6 F6 B7 F17 C8 - 87 A7 122 B7 PD6 I/O FT_hv - LCD_DE, -
OCTOSPIM_P1_IO6,
SDMMC2_CK,
FMC_NWAIT,
SAI1_SD_A,
EVENTOUT
145/390
146/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
MDF1_CKI1,
USART2_CK,
OCTOSPIM_P1_IO7,
- 88 D7 123 L7 H6 D7 C14 D8 - 88 D7 123 D7 PD7 I/O FT_h - SDMMC2_CMD, -
FMC_NCE/FMC_NE1,
LPTIM4_OUT,
DS13543 Rev 2
EVENTOUT
OCTOSPIM_P2_IO6,
SPI3_SCK(boot),
USART1_TX,
- - B7 124 J7 - A7 B13 A7 - - B7 124 A7 PG9 I/O FT_hs - FMC_NCE/FMC_NE2, -
SAI2_SCK_A,
TIM15_CH1N,
EVENTOUT
LPTIM1_IN1,
OCTOSPIM_P2_IO7,
SPI3_MISO(boot),
USART1_RX,
- - C7 125 E7 - C7 F19 B7 - - C7 125 C7 PG10 I/O FT_hs - -
FMC_NE3,
SAI2_FS_A,
TIM15_CH1,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_IN2,
OCTOSPIM_P1_IO5,
SPI3_MOSI,
- - - - C7 - - E18 C7 - - M11 126 M10 PG11 I/O FT_hs - USART1_CTS, -
SAI2_MCLK_A,
TIM15_CH2,
DS13543 Rev 2
EVENTOUT
LPTIM1_ETR,
OCTOSPIM_P2_NCS,
SPI3_NSS(boot),

- - A6 126 A7 - E6 D17 A6 - - A6 127 E6 PG12 I/O FT_hs - USART1_RTS_DE, -
FMC_NE4,
SAI2_SD_A,
EVENTOUT
I2C1_SDA, SPI3_RDY,
- - - 127 G7 - - A14 B6 - - M10 128 N10 PG13 I/O FT_fhs - USART1_CK, LCD_R0, -
FMC_A24, EVENTOUT
LPTIM1_CH2,
- - - 128 F8 - - C16 D7 - - M9 129 N9 PG14 I/O FT_fhs - I2C1_SCL, LCD_R1, -
FMC_A25, EVENTOUT
- - H9 129 D8 - - R24 J10 - - H9 130 - VSS S - - - -
- - D8 130 B8 - A6 A16 E8 - - D8 131 A6 VDDIO2 S - - - -
147/390
148/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_CH1,
I2C1_SMBA,
- - - 131 H8 - A5 H17 A5 - - B4 132 A5 PG15 I/O FT_hs - OCTOSPIM_P2_DQS, -
DCMI_D13/PSSI_D13,
EVENTOUT
JTDO/TRACESWO,
DS13543 Rev 2
TIM2_CH2,
LPTIM1_CH1,
ADF1_CCK0,
I2C1_SDA, SPI1_SCK,
PB3 (JTDO/
SPI3_SCK, COMP2_
55 89 C6 132 K8 B8 D6 B17 E7 55 89 C6 133 D6 TRACESW I/O FT_fa -
USART1_RTS_DE, INM2
O)
CRS_SYNC,
LPGPIO1_P11,
SDMMC2_D2,
SAI1_SCK_B,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
NJTRST,
LPTIM1_CH2,
TIM3_CH1,
ADF1_SDI0,
I2C3_SDA,
SPI1_MISO,
DS13543 Rev 2
SPI3_MISO,
PB4 (6) USART1_CTS, COMP2_
56 90 B6 133 L9 E7 B6 G18 D6 56 90 B6 134 B6 I/O FT_fa
(NJTRST) UART5_RTS_DE, INP1
TSC_G2_IO1,

DCMI_D12/PSSI_D12,
LPGPIO1_P12,
SDMMC2_D3,
SAI1_MCLK_B,
TIM17_BKIN,
EVENTOUT
149/390
150/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_IN1,
TIM3_CH2,
OCTOSPIM_P1_NCLK
, I2C1_SMBA,
SPI1_MOSI,
SPI3_MOSI(boot),
UCPD1_
DS13543 Rev 2
USART1_CK,
57 91 D6 134 A9 A9 C6 C18 B5 57 91 D6 135 C6 PB5 I/O FT_havc - DBCC1,
UART5_CTS,
WKUP6
TSC_G2_IO2,
DCMI_D10/PSSI_D10,
COMP2_OUT,
SAI1_SD_B,
TIM16_BKIN,
EVENTOUT
LPTIM1_ETR,
TIM4_CH1,
TIM8_BKIN2,
I2C1_SCL(boot),
I2C4_SCL,
COMP2_
MDF1_SDI5,
58 92 A5 135 E9 D8 B5 A18 A4 58 92 A5 136 B5 PB6 I/O FT_fa - INP2,
USART1_TX,
WKUP3
TSC_G2_IO3,
DCMI_D5/PSSI_D5,
STM32U5Axxx
SAI1_FS_B,
TIM16_CH1N,
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
LPTIM1_IN2,
TIM4_CH2,
TIM8_BKIN,
I2C1_SDA(boot),
I2C4_SDA,
COMP2_
MDF1_CKI5,
INM1,
DS13543 Rev 2
59 93 D5 136 C9 G7 F5 D19 A3 59 93 D5 137 F5 PB7 I/O FT_fhav - USART1_RX,

PVD_IN,
UART4_CTS,
WKUP4
TSC_G2_IO4,
DCMI_VSYNC/PSSI_R

DY, FMC_NL,
TIM17_CH1N,
EVENTOUT
PH3-
60 94 B5 137 G9 J7 C5 E20 B4 60 94 B5 138 C5 I/O FT - EVENTOUT -
BOOT0
TIM4_CH3, SAI1_CK1,
I2C1_SCL,
MDF1_CCK0,
SPI3_RDY, LCD_B1,
SDMMC1_CKIN,
FDCAN1_RX(boot),
61 95 C5 138 J9 C9 E5 B19 C6 61 95 C5 139 E5 PB8 I/O FT_f - WKUP5
DCMI_D6/PSSI_D6,
SDMMC2_D4,
SDMMC1_D4,
SAI1_MCLK_A,
TIM16_CH1,
151/390
EVENTOUT
152/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
IR_OUT, TIM4_CH4,
SAI1_D2, I2C1_SDA,
SPI2_NSS,
SDMMC1_CDIR,
FDCAN1_TX(boot),
- 96 A4 139 B10 F8 D5 C20 C5 62 96 A4 140 D5 PB9 I/O FT_f - DCMI_D7/PSSI_D7, -
DS13543 Rev 2
SDMMC2_D5,
SDMMC1_D5,
SAI1_FS_A,
TIM17_CH1,
EVENTOUT
TIM4_ETR,
USART6_RX,
LCD_HSYNC,
DCMI_D2/PSSI_D2,
- 97 C4 140 M10 H8 D4 A20 A2 - 97 C4 141 D4 PE0 I/O FT_h - -
LPGPIO1_P13,
FMC_NBL0,
TIM16_CH1,
EVENTOUT
USART6_TX,
LCD_VSYNC,
DCMI_D3/PSSI_D3,
- - A3 141 K10 E9 C4 B21 B3 - 98 A3 142 C4 PE1 I/O FT_h - -
FMC_NBL1,
STM32U5Axxx
TIM17_CH1,
EVENTOUT
- - - - - - - - - - - - - A4 VCAP S - - - -
62 98 B4 142 A11 B10 A4 A22 E6 - - - - - VDD11 S - - - -
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
63 99 E4 143 C11 T12 B4 R4 J15 63 99 E4 143 B4 VSS S - - - -

64 100 J9 144 B12 AC7 A3 A24 - 64 100 J9 144 A3 VDD S - - - -
- - - - - - - A26 - - - - - - VDD S - - - -
- - - - B2 B2 - A4 E11 - - - - - VDD11 S - - - -
DS13543 Rev 2
OCTOSPIM_P1_IO4,
- - - - - - F10 B7 D11 - - - - F10 PH2 I/O FT_h - -
EVENTOUT
I2C5_SDA, I2C2_SCL,

OCTOSPIM_P2_DQS,
- - - - - - E10 E10 C12 - - - - E10 PH4 I/O FT_fh - -
PSSI_D14,
EVENTOUT
I2C5_SCL, I2C2_SDA,
- - - - - - F9 F13 B12 - - - - F9 PH5 I/O FT_f - DCMI_PIXCLK/PSSI_P -
DCK, EVENTOUT
I2C5_SMBA,
I2C2_SMBA,
- - - - - - E11 H15 C11 - - - - E11 PH6 I/O FT_hv - OCTOSPIM_P2_CLK, -
DCMI_D8/PSSI_D8,
EVENTOUT
I2C3_SCL,
OCTOSPIM_P2_NCLK
- - - - - - F8 E12 B11 - - - - F8 PH7 I/O FT_fhv - -
, DCMI_D9/PSSI_D9,
EVENTOUT
153/390
154/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
I2C3_SDA,
OCTOSPIM_P2_IO3,
- - - - - - D12 G16 D10 - - - - D12 PH8 I/O FT_fh - -
DCMI_HSYNC/PSSI_D
E, EVENTOUT
I2C3_SMBA,
OCTOSPIM_P2_IO4,
DS13543 Rev 2
- - - - - - E9 M9 M14 - - - - E9 PH9 I/O FT_hv - HSPI1_NCS, -

DCMI_D0/PSSI_D0,
EVENTOUT
- - - - - - - H3 J6 - - - - - VSS S - - - -
- - - - - - J13 F1 H11 - - - - A11 VDD S - - - -
TIM5_CH1,
OCTOSPIM_P2_IO5,
- - - - - - C13 N6 L13 - - - - C13 PH10 I/O FT_hv - HSPI1_IO0, -
DCMI_D1/PSSI_D1,
EVENTOUT
TIM5_CH2,
OCTOSPIM_P2_IO6,
- - - - - - D9 N8 L14 - - - - D9 PH11 I/O FT_hv - HSPI1_IO1, -
DCMI_D2/PSSI_D2,
EVENTOUT
STM32U5Axxx
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM5_CH3,
TIM8_CH4N,
OCTOSPIM_P2_IO7,
- - - - - - B13 M5 M15 - - - - B13 PH12 I/O FT_hv - -
HSPI1_IO2,
DCMI_D3/PSSI_D3,
EVENTOUT
DS13543 Rev 2
TIM8_CH1N,
HSPI1_IO3,
- - - - - - C12 M7 L15 - - - - C12 PH13 I/O FT_hv - -
FDCAN1_TX,
EVENTOUT

- - - - - - - J4 K10 - - - - - VSS S - - - -
- - - - - - - G2 J11 - - - - - VDD S - - - -
TIM8_CH2N,
HSPI1_IO4,
- - - - - - C11 L6 K13 - - - - C11 PH14 I/O FT_hv - FDCAN1_RX, -
DCMI_D4/PSSI_D4,
EVENTOUT
TIM8_CH3N,
OCTOSPIM_P2_IO6,
- - - - - - A13 L8 K14 - - - - A13 PH15 I/O FT_hv - HSPI1_IO5, -
DCMI_D11/PSSI_D11,
EVENTOUT
155/390
156/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM5_CH4,
OCTOSPIM_P1_IO5,
SPI2_NSS,
- - - - - - B12 K7 K15 - - - - B12 PI0 I/O FT_hv - -
HSPI1_IO6,
DCMI_D13/PSSI_D13,
EVENTOUT
DS13543 Rev 2
SPI2_SCK,
OCTOSPIM_P2_IO2,
- - - - - - A12 K5 J12 - - - - A12 PI1 I/O FT_hv - HSPI1_IO7, -
DCMI_D8/PSSI_D8,
EVENTOUT
- - - - - - - K3 K7 - - - - - VSS S - - - -
- - - - - - - H1 K11 - - - - - VDD S - - - -
TIM8_CH4,
SPI2_MISO,
OCTOSPIM_P2_IO1,
- - - - - - D11 J6 J13 - - - - D11 PI2 I/O FT_hv - -
HSPI1_DQS0,
DCMI_D9/PSSI_D9,
EVENTOUT
TIM8_ETR,
SPI2_MOSI,
STM32U5Axxx
OCTOSPIM_P2_IO0,
- - - - - - D10 K1 J14 - - - - D10 PI3 I/O FT_hvp - -
HSPI1_CLK,
DCMI_D10/PSSI_D10,
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
TIM8_BKIN,
SPI2_RDY,
- - - - - - B10 J2 H14 - - - - B10 PI4 I/O FT_hvp - HSPI1_NCLK, -
DCMI_D5/PSSI_D5,
EVENTOUT
TIM8_CH1,
DS13543 Rev 2
OCTOSPIM_P2_NCS,
- - - - - - B3 C22 C4 - - - - B3 PI5 I/O FT_hv - -
DCMI_VSYNC/PSSI_R
DY, EVENTOUT

TIM8_CH2,
OCTOSPIM_P2_CLK,
- - - - - - A2 D21 D5 - - - - A2 PI6 I/O FT_hvp - -
DCMI_D6/PSSI_D6,
EVENTOUT
TIM8_CH3,
OCTOSPIM_P2_NCLK
- - - - - - C3 J18 D4 - - - - C3 PI7 I/O FT_hvp - -
, DCMI_D7/PSSI_D7,
EVENTOUT
HSPI1_DQS1,
- - - - - - - J8 H13 - - - - - PI8 I/O FT_hv - -
EVENTOUT
- - - - - - B2 L24 K8 - - - - B2 VSS S - - - -
- - - - - - B1 L2 L11 - - - - B1 VDD S - - - -
HSPI1_IO8,
- - - - - - - H5 H12 - - - - - PI9 I/O FT_hv - -
EVENTOUT
157/390
HSPI1_IO9,
- - - - - - - H7 G15 - - - - - PI10 I/O FT_hv - -
EVENTOUT
158/390

Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
HSPI1_IO10,
- - - - - - - G6 G14 - - - - - PI11 I/O FT_hv - -
EVENTOUT
HSPI1_IO11,
- - - - - - - G8 G13 - - - - - PI12 I/O FT_hv - -
EVENTOUT
- - - - - - - L4 K9 - - - - - VSS S - - - -
DS13543 Rev 2
- - - - - - - M1 - - - - - - VDD S - - - -
HSPI1_IO12,
- - - - - - - F7 F15 - - - - - PI13 I/O FT_hv - -
EVENTOUT
HSPI1_IO13,
- - - - - - - F5 F14 - - - - - PI14 I/O FT_hv - -
EVENTOUT
HSPI1_IO14,
- - - - - - - E8 F13 - - - - - PI15 I/O FT_hv - -
EVENTOUT
I2C5_SMBA,
- - - - - - - E6 E15 - - - - - PJ0 I/O FT_hv - HSPI1_IO15, -
EVENTOUT
- - - - - - - M3 L10 - - - - - VSS S - - - -
- - - - - - - N2 - - - - - - VDD S - - - -
I2C5_SDA,
- - - - - - - - G4 - - - - - PJ1 I/O FT_fhv - -
STM32U5Axxx
EVENTOUT
I2C5_SCL,
- - - - - - - - D2 - - - - - PJ2 I/O FT_fhv - -
EVENTOUT
STM32U5Axxx
Pin number
WLCSP150 DSI SMPS
WLCSP208 DSI SMPS
TFBGA216 DSI SMPS

WLCSP150 SMPS
UFBGA132 SMPS
I/O structure
TFBGA169 SMPS
LQFP100 SMPS
LQFP144 SMPS
Pin type
UFBGA132
Additional
TFBGA169
Notes
LQFP100
LQFP144
LQFP64
functions
after reset)
USART6_TX,
- - - - - - - - D1 - - - - - PJ3 I/O FT_hv - -
EVENTOUT
USART6_RX,
- - - - - - - - E3 - - - - - PJ4 I/O FT_hv - -
EVENTOUT
- - - - M12 V2 B11 - R1 - - - - B11 VSS S - - - -
DS13543 Rev 2
USART6_RTS_DE,
- - - - - - - - F3 - - - - - PJ5 I/O FT_hv - -
EVENTOUT
USART6_CK,

- - - - - - - - E2 - - - - - PJ6 I/O FT_hv - -
EVENTOUT
USART6_CTS,
- - - - - - - - E1 - - - - - PJ7 I/O FT_hv - -
EVENTOUT
I2C6_SMBA,
- - - - - - - - F2 - - - - - PJ8 I/O FT_hv - -
EVENTOUT
I2C6_SDA,
- - - - - - - - H4 - - - - - PJ9 I/O FT_fhv - -
EVENTOUT
I2C6_SCL,
- - - - - - - - F1 - - - - - PJ10 I/O FT_fhv - -
EVENTOUT
- - - - - - - - G3 - - - - - PJ11 I/O FT_hv - EVENTOUT -
- - - - - - - - R15 - - - - M7 VSS S - - - -
- - - - A3 - - - - - - - - N7 VDD S - - - -
1. Function availability depends on the chosen device.
159/390
160/390

2. PC13, PC14, and PC15 are supplied through the power switch (by VSW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs
in output mode is limited:
- The speed must not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (for example to drive a LED).
3. After a backup domain power-up, PC13, PC14, and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the
system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
4. After reset, a pull-down resistor (Rd = 5.1 kΩ from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15
(UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2).
This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.
5. GPIO is 5V-tolerant when the USB PHY is powered on.
6. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.
DS13543 Rev 2
STM32U5Axxx
4.3 Alternate functions
STM32U5Axxx
Table 28. Alternate function AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
ADF1/I2C4/
Port I2C5/6/ OCTOSPIM_P1/ DCMI/ DCMI/I2C4/MDF1/ I2C3/MDF1/
CRS/LPTIM1/ LPTIM1/ LCD/
LPTIM1/2/3/ OTG_HS/SAI1/ I2C1/2/3/4/5/ OCTOSPIM_P1/2/ OCTOSPIM_P2/
SYS_AF TIM1/2/5/8 USART1/2/3/6
TIM1/2/3/4/5 SPI2/TIM1/8/ LPTIM3 SPI1/2/3 SPI3
USART2
PA0 - TIM2_CH1 TIM5_CH1 TIM8_ETR - - SPI3_RDY USART2_CTS

USART2_RTS_
PA1 LPTIM1_CH2 TIM2_CH2 TIM5_CH2 - I2C1_SMBA SPI1_SCK -
DE
PA2 - TIM2_CH3 TIM5_CH3 - - SPI1_RDY - USART2_TX
PA3 - TIM2_CH4 TIM5_CH4 SAI1_CK1 - - - USART2_RX
DS13543 Rev 2
OCTOSPIM_P1
PA4 - - - - SPI1_NSS SPI3_NSS USART2_CK
_NCS
PA5 CSLEEP TIM2_CH1 TIM2_ETR TIM8_CH1N PSSI_D14 SPI1_SCK - USART3_RX

DCMI_
PA6 CDSTOP TIM1_BKIN TIM3_CH1 TIM8_BKIN PIXCLK/ SPI1_MISO - USART3_CTS
PSSI_PDCK
Port A
PA7 SRDSTOP TIM1_CH1N TIM3_CH2 TIM8_CH1N I2C3_SCL SPI1_MOSI - USART3_TX

PA8 MCO TIM1_CH1 - SAI1_CK2 - SPI1_RDY - USART1_CK
PA9 - TIM1_CH2 - SPI2_SCK - DCMI_D0/PSSI_D0 - USART1_TX
PA10 CRS_SYNC TIM1_CH3 LPTIM2_IN2 SAI1_D1 - DCMI_D1/PSSI_D1 - USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS
OCTOSPIM_P2 USART1_RTS_
PA12 - TIM1_ETR - - - SPI1_MOSI
_NCS DE
PA13 JTMS/SWDIO IR_OUT - - - - - -
PA14 JTCK/SWCLK LPTIM1_CH1 - - I2C1_SMBA I2C4_SMBA - -
161/390
USART3_RTS_
PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS
DE
Table 28. Alternate function AF0 to AF7(1) (continued)
162/390

ADF1/I2C4/
USART2
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N LPTIM3_CH1 SPI1_NSS - USART3_CK

USART3_RTS_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N LPTIM3_CH2 - MDF1_SDI0
DE
PB2 - LPTIM1_CH1 - TIM8_CH4N I2C3_SMBA SPI1_RDY MDF1_CKI0 -
JTDO/ USART1_RTS_
PB3 TIM2_CH2 LPTIM1_CH1 ADF1_CCK0 I2C1_SDA SPI1_SCK SPI3_SCK
TRACESWO DE
PB4 NJTRST LPTIM1_CH2 TIM3_CH1 ADF1_SDI0 I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS
DS13543 Rev 2
OCTOSPIM_P1
PB5 - LPTIM1_IN1 TIM3_CH2 I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK
_NCLK
PB6 - LPTIM1_ETR TIM4_CH1 TIM8_BKIN2 I2C1_SCL I2C4_SCL MDF1_SDI5 USART1_TX
Port B
PB7 - LPTIM1_IN2 TIM4_CH2 TIM8_BKIN I2C1_SDA I2C4_SDA MDF1_CKI5 USART1_RX

PB8 - - TIM4_CH3 SAI1_CK1 I2C1_SCL MDF1_CCK0 SPI3_RDY LCD_B1
PB9 - IR_OUT TIM4_CH4 SAI1_D2 I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 LPTIM3_CH1 I2C4_SCL I2C2_SCL SPI2_SCK - USART3_TX
PB11 - TIM2_CH4 - I2C4_SDA I2C2_SDA SPI2_RDY - USART3_RX
PB12 - TIM1_BKIN I2C6_SMBA - I2C2_SMBA SPI2_NSS MDF1_SDI1 USART3_CK
PB13 - TIM1_CH1N LPTIM3_IN1 - I2C2_SCL SPI2_SCK MDF1_CKI1 USART3_CTS
USART3_RTS_
PB14 - TIM1_CH2N LPTIM3_ETR TIM8_CH2N I2C2_SDA SPI2_MISO MDF1_SDI2
DE
STM32U5Axxx
PB15 RTC_REFIN TIM1_CH3N LPTIM2_IN2 TIM8_CH3N - SPI2_MOSI MDF1_CKI2 -
STM32U5Axxx
ADF1/I2C4/
USART2
OCTOSPIM_P1
PC0 - LPTIM1_IN1 - I2C3_SCL SPI2_RDY MDF1_SDI4 USART6_CTS
_IO7
PC1 TRACED0 LPTIM1_CH1 - SPI2_MOSI I2C3_SDA - MDF1_CKI4 USART6_CK
PC2 - LPTIM1_IN2 - - - SPI2_MISO MDF1_CCK1 USART6_RX
PC3 - LPTIM1_ETR LPTIM3_CH1 SAI1_D1 - SPI2_MOSI - USART6_TX
PC4 - - I2C6_SMBA - - - - USART3_TX
PC5 - TIM1_CH4N SAI1_D3 PSSI_D15 - - USART3_RX
DS13543 Rev 2
PC6 CSLEEP - TIM3_CH1 TIM8_CH1 - - MDF1_CKI3 LCD_R0

PC7 CDSTOP - TIM3_CH2 TIM8_CH2 - - MDF1_SDI3 LCD_R1
Port C

PC8 SRDSTOP - TIM3_CH3 TIM8_CH3 - - - USART6_RX
DCMI_D3/
PC9 TRACED0 TIM8_BKIN2 TIM3_CH4 TIM8_CH4 - - USART6_TX
PSSI_D3
PC10 TRACED1 - LPTIM3_ETR ADF1_CCK1 - - SPI3_SCK USART3_TX
DCMI_D2/ OCTOSPIM_P1_
PC11 - - LPTIM3_IN1 ADF1_SDI0 SPI3_MISO USART3_RX
PSSI_D2 NCS
PC12 TRACED3 - - - - - SPI3_MOSI USART3_CK
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -
163/390
164/390

ADF1/I2C4/
USART2
PD0 - - I2C6_SDA TIM8_CH4N I2C5_SDA SPI2_NSS - -

PD1 - - I2C6_SCL - I2C5_SCL SPI2_SCK - -
USART3_RTS_
PD2 TRACED2 - TIM3_ETR - I2C5_SMBA - -
DE
DCMI_D5/
PD3 - - I2C6_SMBA SPI2_SCK SPI2_MISO MDF1_SDI0 USART2_CTS
PSSI_D5
USART2_RTS_
PD4 - - - - - SPI2_MOSI MDF1_CKI0
DS13543 Rev 2
DE
PD5 - - - - - SPI2_RDY - USART2_TX
DCMI_D10/
PD6 - - - SAI1_D1 SPI3_MOSI MDF1_SDI1 USART2_RX
PSSI_D10
Port D
PD7 - - - - - - MDF1_CKI1 USART2_CK

PD8 - - - - - - - USART3_TX
PD9 - - LPTIM2_IN2 - - - - USART3_RX
PD10 - - LPTIM2_CH2 - I2C5_SMBA - - USART3_CK
PD11 - - - - I2C4_SMBA - - USART3_CTS
USART3_RTS_
PD12 - - TIM4_CH1 - I2C4_SCL - -
DE
PD13 - - TIM4_CH2 - I2C4_SDA - - USART6_CTS
STM32U5Axxx
PD14 - - TIM4_CH3 - - - - USART6_CK
USART6_RTS_
PD15 - - TIM4_CH4 - - - -
DE
STM32U5Axxx
ADF1/I2C4/
USART2
PE0 - - TIM4_ETR - - - - USART6_RX

PE1 - - - - - - - USART6_TX
PE2 TRACECLK - TIM3_ETR SAI1_CK1 - - - USART6_CK
OCTOSPIM_P1
PE3 TRACED0 - TIM3_CH1 - - - USART6_CTS
_DQS
USART6_RTS_
PE4 TRACED1 - TIM3_CH2 SAI1_D2 - - MDF1_SDI3
DE
DS13543 Rev 2
PE5 TRACED2 - TIM3_CH3 SAI1_CK2 - - MDF1_CKI3 -

PE6 TRACED3 - TIM3_CH4 SAI1_D1 - - - -
Port E

PE7 - TIM1_ETR - - - - MDF1_SDI2 -
PE8 - TIM1_CH1N - - - - MDF1_CKI2 -
PE9 - TIM1_CH1 - ADF1_CCK0 - - MDF1_CCK0 -
PE10 - TIM1_CH2N - ADF1_SDI0 - - MDF1_SDI4 -
PE11 - TIM1_CH2 - - - SPI1_RDY MDF1_CKI4 -
PE12 - TIM1_CH3N - - - SPI1_NSS MDF1_SDI5 -
PE13 - TIM1_CH3 - - - SPI1_SCK MDF1_CKI5 -
PE14 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - -
PE15 - TIM1_BKIN - TIM1_CH4N - SPI1_MOSI - -
165/390
166/390

ADF1/I2C4/
USART2
PF0 - - I2C6_SDA - I2C2_SDA OCTOSPIM_P2_IO0 - USART6_TX

PF1 - - I2C6_SCL - I2C2_SCL OCTOSPIM_P2_IO1 - USART6_RX
PF2 - - LPTIM3_CH2 - I2C2_SMBA OCTOSPIM_P2_IO2 - USART6_CK
PF3 - - LPTIM3_IN1 ADF1_CCK0 - OCTOSPIM_P2_IO3 MDF1_CCK0 USART6_CTS
OCTOSPIM_P2_ USART6_RTS_
PF4 - - LPTIM3_ETR ADF1_SDI0 - MDF1_SDI0
CLK DE
OCTOSPIM_P2_
DS13543 Rev 2
PF5 - - LPTIM3_CH1 - - MDF1_CKI0 -

NCLK
DCMI_D12/ OCTOSPIM_P2_
PF6 - TIM5_ETR TIM5_CH1 - - -
PSSI_D12 NCS
PF7 - - TIM5_CH2 - - - - -
Port F
PF8 - - TIM5_CH3 - PSSI_D14 - - -

PF9 - - TIM5_CH4 - PSSI_D15 - - -
OCTOSPIM_P1
PF10 - - - PSSI_D15 - MDF1_CCK1 -
_CLK
OCTOSPIM_P1
PF11 - - - - - - -
_NCLK
OCTOSPIM_P2_
PF12 - - - - - - -
DQS
PF13 - - - - I2C4_SMBA - - -
STM32U5Axxx
PF14 - - - - I2C4_SCL - - -
PF15 - - - - I2C4_SDA - - -
STM32U5Axxx
ADF1/I2C4/
USART2
PG0 - - - - - OCTOSPIM_P2_IO4 - -
PG1 - - - - - OCTOSPIM_P2_IO5 - -
PG2 - - - - - SPI1_SCK - -
PG3 - - - - - SPI1_MISO - -
PG4 - - - - - SPI1_MOSI - -
PG5 - - - - - SPI1_NSS - -
DS13543 Rev 2
OCTOSPIM_P1
PG6 - - - I2C3_SMBA SPI1_RDY - LCD_R1
_DQS
OCTOSPIM_P2_
PG7 - - - SAI1_CK1 I2C3_SCL MDF1_CCK0 -

DQS
Port G
PG8 - - - - I2C3_SDA - - -
PG9 - - - - - OCTOSPIM_P2_IO6 SPI3_SCK USART1_TX
PG10 - LPTIM1_IN1 - - - OCTOSPIM_P2_IO7 SPI3_MISO USART1_RX
OCTOSPIM_P1
PG11 - LPTIM1_IN2 - - - SPI3_MOSI USART1_CTS
_IO5
OCTOSPIM_P2_ USART1_RTS_
PG12 - LPTIM1_ETR - - - SPI3_NSS
NCS DE
PG13 - - - - I2C1_SDA - SPI3_RDY USART1_CK
PG14 - LPTIM1_CH2 - - I2C1_SCL - - -
OCTOSPIM_P2_
PG15 - LPTIM1_CH1 - - I2C1_SMBA - -
DQS
167/390
168/390

ADF1/I2C4/
USART2
PH0 - - - - - - - -
PH1 - - - - - - - -
OCTOSPIM_P1
PH2 - - - - - - -
_IO4
PH3 - - - - - - - -
OCTOSPIM_P2_
PH4 - - I2C5_SDA - I2C2_SCL - -
DQS
DS13543 Rev 2
PH5 - - I2C5_SCL - I2C2_SDA - - -

OCTOSPIM_P2_
PH6 - - I2C5_SMBA - I2C2_SMBA - -
CLK
Port H
OCTOSPIM_P2_
PH7 - - - - I2C3_SCL - -
NCLK
PH8 - - - - I2C3_SDA OCTOSPIM_P2_IO3 - -
PH9 - - - - I2C3_SMBA OCTOSPIM_P2_IO4 - -
PH10 - - TIM5_CH1 - - OCTOSPIM_P2_IO5 - -
PH11 - - TIM5_CH2 - - OCTOSPIM_P2_IO6 - -
PH12 - - TIM5_CH3 TIM8_CH4N - OCTOSPIM_P2_IO7 - -
PH13 - - - TIM8_CH1N - - - -
PH14 - - - TIM8_CH2N - - - -
STM32U5Axxx
PH15 - - - TIM8_CH3N - OCTOSPIM_P2_IO6 - -
STM32U5Axxx
ADF1/I2C4/
USART2
OCTOSPIM_P1
PI0 - - TIM5_CH4 - SPI2_NSS - -
_IO5
OCTOSPIM_P2
PI1 - - - - - SPI2_SCK -
_IO2
OCTOSPIM_P2
PI2 - - - TIM8_CH4 - SPI2_MISO -
_IO1
OCTOSPIM_P2
PI3 - - - TIM8_ETR - SPI2_MOSI -
_IO0
DS13543 Rev 2
PI4 - - - TIM8_BKIN - SPI2_RDY - -

OCTOSPIM_P2_
PI5 - - - TIM8_CH1 - - -

NCS
OCTOSPIM_P2_
Port I
PI6 - - - TIM8_CH2 - - -
CLK
OCTOSPIM_P2_
PI7 - - - TIM8_CH3 - - -
NCLK
PI8 - - - - - - - -
PI9 - - - - - - - -
PI10 - - - - - - - -
PI11 - - - - - - - -
PI12 - - - - - - - -
PI13 - - - - - - - -
PI14 - - - - - - - -
169/390
PI15 - - - - - - - -
170/390

ADF1/I2C4/
USART2
PJ0 - - - - I2C5_SMBA - - -
PJ1 - - - - I2C5_SDA - - -
PJ2 - - - - I2C5_SCL - - -
PJ3 - - - - - - - USART6_TX
PJ4 - - - - - - - USART6_RX
USART6_RTS_
PJ5 - - - - - - -
Port J
DE
DS13543 Rev 2
PJ6 - - - - - - - USART6_CK
PJ7 - - - - - - - USART6_CTS
PJ8 - - I2C6_SMBA - - - - -
PJ9 - - I2C6_SDA - - - - -
PJ10 - - I2C6_SCL - - - - -
PJ11 - - - - - - - -
1. Refer to the next table for AF8 to AF15.
STM32U5Axxx
Table 29. Alternate function AF8 to AF15(1)
STM32U5Axxx
HSPI1/LCD/ DSI/FMC/
Port CRS/DCMI/ COMP1/2/FMC/
LPUART1/ LPGPIO1/ LPTIM2/4/ LPTIM2/3/
CAN1/TSC OCTOSPIM_P1/2/ SDMMC1/2/ EVENTOUT
SDMMC1/ SDMMC2/ SAI1/2 TIM2/15/16/17
OTG_HS SYS_AF
UART4/5 UCPD1
OCTOSPIM_P2_
PA0 UART4_TX - - SDMMC2_CMD AUDIOCLK TIM2_ETR EVENTOUT
NCS
OCTOSPIM_P1_
PA1 UART4_RX - LPGPIO1_P0 - - TIM15_CH1N EVENTOUT
DQS
OCTOSPIM_P1_ UCPD1_
PA2 LPUART1_TX - - - TIM15_CH1 EVENTOUT
NCS FRSTX1
OCTOSPIM_P1_
PA3 LPUART1_RX - LPGPIO1_P1 - SAI1_MCLK_A TIM15_CH2 EVENTOUT
CLK
DS13543 Rev 2
DCMI_HSYNC/
PA4 - - - - SAI1_FS_B LPTIM2_CH1 EVENTOUT
PSSI_DE
PA5 - - - - - - LPTIM2_ETR EVENTOUT

Port A
PA6 LPUART1_CTS - OCTOSPIM_P1_IO3 LPGPIO1_P2 - - TIM16_CH1 EVENTOUT

PA7 - - OCTOSPIM_P1_IO2 - - LPTIM2_CH2 TIM17_CH1 EVENTOUT
PA8 - - OTG_HS_SOF - TRACECLK SAI1_SCK_A LPTIM2_CH1 EVENTOUT
PA9 - - - - - SAI1_FS_A TIM15_BKIN EVENTOUT
PA10 - - OTG_HS_ID - - SAI1_SD_A TIM17_BKIN EVENTOUT
PA11 - FDCAN1_RX - - - - - EVENTOUT
PA12 - FDCAN1_TX - - - - - EVENTOUT
PA13 - - - - - SAI1_SD_B - EVENTOUT
PA14 - - OTG_HS_SOF - - SAI1_FS_B - EVENTOUT
UART4_RTS_
PA15 - - - - SAI2_FS_B - EVENTOUT
DE
171/390
172/390

HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PB0 - - OCTOSPIM_P1_IO1 LPGPIO1_P9 COMP1_OUT AUDIOCLK - EVENTOUT

LPUART1_RTS_
PB1 - OCTOSPIM_P1_IO0 LPGPIO1_P3 - - LPTIM2_IN1 EVENTOUT
DE
OCTOSPIM_P1_ UCPD1_
PB2 LCD_B1 - - - - EVENTOUT
DQS FRSTX1
PB3 - - CRS_SYNC LPGPIO1_P11 SDMMC2_D2 SAI1_SCK_B - EVENTOUT
UART5_RTS_ DCMI_D12/
PB4 TSC_G2_IO1 LPGPIO1_P12 SDMMC2_D3 SAI1_MCLK_B TIM17_BKIN EVENTOUT
DE PSSI_D12
DS13543 Rev 2
DCMI_D10/
PB5 UART5_CTS TSC_G2_IO2 - COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
PSSI_D10
PB6 - TSC_G2_IO3 DCMI_D5/PSSI_D5 - - SAI1_FS_B TIM16_CH1N EVENTOUT
DCMI_VSYNC/
Port B
PB7 UART4_CTS TSC_G2_IO4 - FMC_NL - TIM17_CH1N EVENTOUT

PSSI_RDY
PB8 SDMMC1_CKIN FDCAN1_RX DCMI_D6/PSSI_D6 SDMMC2_D4 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT
PB9 SDMMC1_CDIR FDCAN1_TX DCMI_D7/PSSI_D7 SDMMC2_D5 SDMMC1_D5 SAI1_FS_A TIM17_CH1 EVENTOUT
OCTOSPIM_P1_
PB10 LPUART1_RX TSC_SYNC LPGPIO1_P4 COMP1_OUT SAI1_SCK_A - EVENTOUT
CLK
OCTOSPIM_P1_
PB11 LPUART1_TX - - COMP2_OUT - - EVENTOUT
NCS
LPUART1_RTS_ OCTOSPIM_P1_
PB12 TSC_G1_IO1 - - SAI2_FS_A TIM15_BKIN EVENTOUT
DE NCLK
STM32U5Axxx
PB13 LPUART1_CTS TSC_G1_IO2 - - - SAI2_SCK_A TIM15_CH1N EVENTOUT
PB14 - TSC_G1_IO3 - - SDMMC2_D0 SAI2_MCLK_A TIM15_CH1 EVENTOUT
PB15 - - - FMC_NBL1 SDMMC2_D1 SAI2_SD_A TIM15_CH2 EVENTOUT
STM32U5Axxx
HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PC0 LPUART1_RX - - - SDMMC1_D5 SAI2_FS_A LPTIM2_IN1 EVENTOUT

PC1 LPUART1_TX - OCTOSPIM_P1_IO4 - SDMMC2_CK SAI1_SD_A - EVENTOUT
PC2 - - OCTOSPIM_P1_IO5 LPGPIO1_P5 - - - EVENTOUT
PC3 - - OCTOSPIM_P1_IO6 - - SAI1_SD_A LPTIM2_ETR EVENTOUT
PC4 - - OCTOSPIM_P1_IO7 - - - - EVENTOUT
PC5 - - - - - - - EVENTOUT
SDMMC1_
PC6 TSC_G4_IO1 DCMI_D0/PSSI_D0 SDMMC2_D6 SDMMC1_D6 SAI2_MCLK_A - EVENTOUT
DS13543 Rev 2
D0DIR
SDMMC1_
PC7 TSC_G4_IO2 DCMI_D1/PSSI_D1 SDMMC2_D7 SDMMC1_D7 SAI2_MCLK_B LPTIM2_CH2 EVENTOUT
Port C
D123DIR

PC8 - TSC_G4_IO3 DCMI_D2/PSSI_D2 - SDMMC1_D0 - LPTIM3_CH1 EVENTOUT
PC9 - TSC_G4_IO4 - - SDMMC1_D1 - LPTIM3_CH2 EVENTOUT
PC10 UART4_TX TSC_G3_IO2 DCMI_D8/PSSI_D8 LPGPIO1_P8 SDMMC1_D2 SAI2_SCK_B - EVENTOUT
UCPD1_
PC11 UART4_RX TSC_G3_IO3 DCMI_D4/PSSI_D4 SDMMC1_D3 SAI2_MCLK_B - EVENTOUT
FRSTX2
PC12 UART5_TX TSC_G3_IO4 DCMI_D9/PSSI_D9 LPGPIO1_P10 SDMMC1_CK SAI2_SD_B - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
173/390
174/390

HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PD0 LCD_B4 FDCAN1_RX - - FMC_D2 - - EVENTOUT

PD1 LCD_B5 FDCAN1_TX - - FMC_D3 - - EVENTOUT
DCMI_D11/
PD2 UART5_RX TSC_SYNC LPGPIO1_P7 SDMMC1_CMD LPTIM4_ETR - EVENTOUT
PSSI_D11
OCTOSPIM_P2_
PD3 LCD_CLK - - FMC_CLK - - EVENTOUT
NCS
PD4 - - OCTOSPIM_P1_IO4 - FMC_NOE - - EVENTOUT
PD5 - - OCTOSPIM_P1_IO5 - FMC_NWE - - EVENTOUT
DS13543 Rev 2
PD6 LCD_DE - OCTOSPIM_P1_IO6 SDMMC2_CK FMC_NWAIT SAI1_SD_A - EVENTOUT

FMC_NCE/
PD7 - - OCTOSPIM_P1_IO7 SDMMC2_CMD LPTIM4_OUT - EVENTOUT
FMC_NE1
Port D
DCMI_HSYNC/
PD8 LCD_R3 - - FMC_D13 - - EVENTOUT
PSSI_DE
DCMI_PIXCLK/
PD9 LCD_R4 - - FMC_D14 SAI2_MCLK_A LPTIM3_IN1 EVENTOUT
PSSI_PDCK
PD10 LCD_R5 TSC_G6_IO1 - - FMC_D15 SAI2_SCK_A LPTIM3_ETR EVENTOUT
FMC_CLE/
PD11 LCD_R6 TSC_G6_IO2 - - SAI2_SD_A LPTIM2_ETR EVENTOUT
FMC_A16
FMC_ALE/
PD12 LCD_R7 TSC_G6_IO3 - - SAI2_FS_A LPTIM2_IN1 EVENTOUT
FMC_A17
PD13 LCD_VSYNC TSC_G6_IO4 - LPGPIO1_P6 FMC_A18 LPTIM4_IN1 LPTIM2_CH1 EVENTOUT
STM32U5Axxx
PD14 LCD_B2 - - - FMC_D0 - LPTIM3_CH1 EVENTOUT
PD15 LCD_B3 - - - FMC_D1 - LPTIM3_CH2 EVENTOUT
STM32U5Axxx
HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PE0 LCD_HSYNC - DCMI_D2/PSSI_D2 LPGPIO1_P13 FMC_NBL0 - TIM16_CH1 EVENTOUT

PE1 LCD_VSYNC - DCMI_D3/PSSI_D3 - FMC_NBL1 - TIM17_CH1 EVENTOUT
PE2 LCD_R0 TSC_G7_IO1 - LPGPIO1_P14 FMC_A23 SAI1_MCLK_A - EVENTOUT
PE3 LCD_R1 TSC_G7_IO2 - LPGPIO1_P15 FMC_A19 SAI1_SD_B - EVENTOUT
PE4 LCD_B0 TSC_G7_IO3 DCMI_D4/PSSI_D4 - FMC_A20 SAI1_FS_A - EVENTOUT
PE5 LCD_G0 TSC_G7_IO4 DCMI_D6/PSSI_D6 - FMC_A21 SAI1_SCK_A - EVENTOUT
PE6 LCD_G1 - DCMI_D7/PSSI_D7 - FMC_A22 SAI1_SD_A - EVENTOUT
DS13543 Rev 2
PE7 LCD_B6 - - - FMC_D4 SAI1_SD_B - EVENTOUT

PE8 LCD_B7 - - - FMC_D5 SAI1_SCK_B - EVENTOUT
Port E

OCTOSPIM_P1_
PE9 LCD_G2 - - FMC_D6 SAI1_FS_B - EVENTOUT
NCLK
OCTOSPIM_P1_CL
PE10 LCD_G3 TSC_G5_IO1 - FMC_D7 SAI1_MCLK_B - EVENTOUT
K
OCTOSPIM_P1_
PE11 LCD_G4 TSC_G5_IO2 - FMC_D8 - - EVENTOUT
NCS
PE12 LCD_G5 TSC_G5_IO3 OCTOSPIM_P1_IO0 - FMC_D9 - - EVENTOUT
PE13 LCD_G6 TSC_G5_IO4 OCTOSPIM_P1_IO1 - FMC_D10 - - EVENTOUT
PE14 LCD_G7 - OCTOSPIM_P1_IO2 - FMC_D11 - - EVENTOUT
PE15 LCD_R2 - OCTOSPIM_P1_IO3 - FMC_D12 - - EVENTOUT
175/390
176/390

HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PF0 - - - - FMC_A0 - - EVENTOUT

PF3 UART5_TX - - - FMC_A3 - - EVENTOUT
PF4 UART5_RX - - - FMC_A4 - - EVENTOUT
PF6 - - OCTOSPIM_P1_IO3 - - SAI1_SD_B - EVENTOUT
DS13543 Rev 2
PF7 - FDCAN1_RX OCTOSPIM_P1_IO2 - - SAI1_MCLK_B - EVENTOUT

PF8 - FDCAN1_TX OCTOSPIM_P1_IO0 - - SAI1_SCK_B - EVENTOUT
Port F
PF9 - - OCTOSPIM_P1_IO1 - - SAI1_FS_B TIM15_CH1 EVENTOUT

DCMI_D11/PSSI_
PF10 - - DSI_TE - SAI1_D3 TIM15_CH2 EVENTOUT
D11
DCMI_D12/PSSI_
PF11 LCD_DE - DSI_TE - LPTIM4_IN1 - EVENTOUT
D12
PF12 LCD_B0 - - - FMC_A6 LPTIM4_ETR - EVENTOUT
UCPD1_
PF13 LCD_B1 - - FMC_A7 LPTIM4_OUT - EVENTOUT
FRSTX2
PF14 LCD_G0 TSC_G8_IO1 - - FMC_A8 - - EVENTOUT
PF15 LCD_G1 TSC_G8_IO2 - - FMC_A9 - - EVENTOUT
STM32U5Axxx
STM32U5Axxx
HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PG0 - TSC_G8_IO3 - - FMC_A10 - - EVENTOUT

PG1 - TSC_G8_IO4 - - FMC_A11 - - EVENTOUT
PG2 - - - - FMC_A12 SAI2_SCK_B - EVENTOUT
PG3 - - - - FMC_A13 SAI2_FS_B - EVENTOUT
PG4 - - - - FMC_A14 SAI2_MCLK_B - EVENTOUT
PG5 LPUART1_CTS - - DSI_TE FMC_A15 SAI2_SD_B - EVENTOUT
LPUART1_RTS_ UCPD1_
PG6 - - - - - EVENTOUT
DS13543 Rev 2
DE FRSTX1
UCPD1_
PG7 LPUART1_TX - - FMC_INT SAI1_MCLK_A - EVENTOUT
FRSTX2
Port G

PG8 LPUART1_RX - - - - - - EVENTOUT
FMC_NCE/FMC
PG9 - - - - SAI2_SCK_A TIM15_CH1N EVENTOUT
_NE2
PG10 - - - - FMC_NE3 SAI2_FS_A TIM15_CH1 EVENTOUT
PG11 - - - - - SAI2_MCLK_A TIM15_CH2 EVENTOUT
PG12 - - - - FMC_NE4 SAI2_SD_A - EVENTOUT
PG13 LCD_R0 - - - FMC_A24 - - EVENTOUT
PG14 LCD_R1 - - - FMC_A25 - - EVENTOUT
DCMI_D13/PSSI_
PG15 - - - - - - EVENTOUT
D13
177/390
178/390

HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PH0 - - - - - - - EVENTOUT
PH1 - - - - - - - EVENTOUT
PH2 - - - - - - - EVENTOUT
PH3 - - - - - - - EVENTOUT
PH4 - - PSSI_D14 - - - - EVENTOUT
DCMI_PIXCLK/PSSI
PH5 - - - - - - EVENTOUT
_PDCK
DS13543 Rev 2
PH6 - - DCMI_D8/PSSI_D8 - - - - EVENTOUT

PH7 - - DCMI_D9/PSSI_D9 - - - - EVENTOUT
Port H
DCMI_HSYNC/PSSI
PH8 - - - - - - EVENTOUT
_DE
PH9 HSPI1_NCS - DCMI_D0/PSSI_D0 - - - - EVENTOUT
PH10 HSPI1_IO0 - DCMI_D1/PSSI_D1 - - - - EVENTOUT
PH13 HSPI1_IO3 FDCAN1_TX - - - - - EVENTOUT
PH14 HSPI1_IO4 FDCAN1_RX DCMI_D4/PSSI_D4 - - - - EVENTOUT
DCMI_D11/PSSI_
PH15 HSPI1_IO5 - - - - - EVENTOUT
D11
STM32U5Axxx
STM32U5Axxx
HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
DCMI_D13/PSSI_
PI0 HSPI1_IO6 - - - - - EVENTOUT
D13
PI1 HSPI1_IO7 - DCMI_D8/PSSI_D8 - - - - EVENTOUT
PI2 HSPI1_DQS0 - DCMI_D9/PSSI_D9 - - - - EVENTOUT
DCMI_D10/PSSI_
PI3 HSPI1_CLK - - - - - EVENTOUT
D10
PI4 HSPI1_NCLK - DCMI_D5/PSSI_D5 - - - - EVENTOUT
DCMI_VSYNC/PSSI
DS13543 Rev 2
PI5 - - - - - - EVENTOUT
_RDY
PI6 - - DCMI_D6/PSSI_D6 - - - - EVENTOUT
Port I

PI7 - - DCMI_D7/PSSI_D7 - - - - EVENTOUT
PI8 HSPI1_DQS1 - - - - - - EVENTOUT
PI9 HSPI1_IO8 - - - - - - EVENTOUT
179/390
180/390

HSPI1/LCD/ DSI/FMC/
OTG_HS SYS_AF
UART4/5 UCPD1
PJ0 HSPI1_IO15 - - - - - - EVENTOUT

PJ1 - - - - - - - EVENTOUT
PJ2 - - - - - - - EVENTOUT
PJ3 - - - - - - - EVENTOUT
PJ4 - - - - - - - EVENTOUT
PJ5 - - - - - - - EVENTOUT
Port J
PJ6 - - - - - - - EVENTOUT
DS13543 Rev 2
PJ7 - - - - - - - EVENTOUT
PJ8 - - - - - - - EVENTOUT
PJ9 - - - - - - - EVENTOUT
PJ10 - - - - - - - EVENTOUT
PJ11 - - - - - - - EVENTOUT
1. For AF0 to AF7 refer to the previous table.
STM32U5Axxx
STM32U5Axxx Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes, and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V.
They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range and supply voltage range, where
95% of the devices have an error less than or equal to the value indicated (mean ±2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 21.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 22.
Figure 21. Pin loading conditions Figure 22. Pin input voltage
MCU pin MCU pin

C = 50 pF VIN
MSv68045V1 MSv68046V1
5.1.6 Power supply scheme

Each power supply pair (such as VDD/VSS or VDDA/VSSA) must be decoupled with filtering
ceramic capacitors as shown in Figure 23 and Figure 24. These capacitors must be placed
DS13543 Rev 2 181/390

352
Electrical characteristics STM32U5Axxx
as close as possible to, or below, the appropriate pins on the underside of the PCB to
ensure the proper functionality of the device.
Figure 23. STM32U5Axxx power supply scheme (without SMPS)
1.65 – 3.6 V VBAT

Backup circuitry
(LSE, RTC, TAMP,
VDDUSB backup registers,
VDDUSB backup SRAM)
Power switch
100 nF
VCAP
COUT = 4.7 μF
VCORE
VDD
n x VDD LDO VCORE
regulator
VDDIO1
OUT
Level shifter
n x 100 nF GPIOs I/O
IN logic Kernel logic
+ 10 μF
(CPU, digital
and memories)
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
Level shifter
m x100 nF OUT
I/O
+ 4.7 μF GPIOs
IN
logic
m x VSS
VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/
+ 1 μF OPAMPs/
100 nF+ 1 μF VREF- COMPs/
VREFBUF
VSSA
MSv71165V2
Caution: If there are two VCAP pins (TFBGA169 package), each pin must be connected to a 2.2 µF
(typical) capacitor.
The external capacitor on VCAP pin requires the following characteristics:
• COUT = 4.7 µF or 2 × 2.2 µF ±20%
• COUT ESR < 20 mΩ at 3 MHz
• COUT rated voltage ≥ 10 V
182/390 DS13543 Rev 2

Figure 24. STM32U5AxxxxxQ power supply scheme (with SMPS)
1.65 – 3.6 V VBAT Backup circuitry

(LSE, RTC, TAMP,
backup registers,
VDDUSB
backup SRAM)
VDDUSB Power switch
100 nF
VDD
VDDDSI
100 nF
VDDSMPS
Voltage regulator
CIN = 10 μF
SMPS VCORE
VLXSMPS SMPS ON
L = 2.2 μH
2 x VDD11
COUT = 2 x 2.2 μF Kernel logic
VSSSMPS
SMPS OFF (CPU, digital
VDD11(1) and memories)
VDD11USB(1)
VDD11DSI
VDD LDO
n x VDD
VDDIO1
OUT
Level shifter
n x 100 nF GPIOs I/O

IN logic
+ 10 μF
n x VSS
VDDIO2
m x VDDIO2
VDDIO2
Level shifter
m x100 nF OUT
I/O
+ 4.7 μF GPIOs
IN
logic
m x VSS
VDDA
VDDA
VREF
ADCs/
100 nF VREF+ DACs/ (1) Only available on specific
+ 1 μF OPAMPs/
VREF- COMPs/
packages
100 nF+ 1 μF
VREFBUF
VSSA
MSv67887V3
DS13543 Rev 2 183/390

352
Note: SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on
application requirements. However, only one of them is active at the same time. When
SMPS is active, it feeds the VCORE on the two VDD11 pins supplied by the filtered SMPS
VLXSMPS output pin. When LDO is active, it supplies the VCORE and regulates it using the
same capacitors on VDD11 pins. It is recommended to add a decoupling capacitor of 100 nF
near each VDD11 pin/ball, but it is not mandatory.
The external capacitors on VDD11 pins require the following characteristics:
• COUT = 2 × 2.2 µF ±20%
• COUT ESR < 20 mΩ at 3 MHz
• COUT rated voltage ≥ 10 V
The external capacitor on VDDSMPS pin requires the following characteristics:
• CIN = 10 µF ±20%
• CIN ESR < 10 mΩ at 3 MHz
• CIN rated voltage ≥ 10 V
The external inductance between VLXSMPS and VDD11 requires the following
characteristics:
• L = 2.2 µH ±20%
• L ISAT > 0.5 A
• L DCR < 200 mΩ
5.1.7 Current consumption measurement

The IDD parameters given in various tables in the next sections, represent the total MCU
consumption including the current supplying VDD, VDDIO2, VDDA, VDDUSB, VDDDSI, VBAT, and
VDDSMPS (if the device embeds the SMPS).
Figure 25. Current consumption measurement
VBAT
IDD_VBAT
IDD
VDD
VDDA
VDDDSI
VDDUSB
VDDSMPS
VDDIO2
MSv67884V2
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 30, Table 31, and Table 32
may cause permanent damage to the device. These are stress ratings only and the
184/390 DS13543 Rev 2

functional operation of the device at these conditions is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability. Device mission profile
(application conditions) is compliant with JEDEC JESD47 qualification standard, extended
mission profiles are available on demand.
Table 30. Voltage characteristics(1) (2)

Symbol Ratings Min Max Unit
External main supply voltage (including

VDDX - VSS VDDSMPS, VDDA, VDDUSB, VDDDSI, -0.3 4.0
VBAT, VREF+)
I/O supply when HSLV = 0 -0.3 4.0
VDDIOx(3) - VSS
I/O supply when HSLV = 1 -0.3 2.75
Input voltage on FT_xx pins except Min (min (VDD, VDDA, VDDUSB, VDDIO2)
VSS - 0.3
FT_c pins + 4.0, 6.0)(5)(6) V
Input voltage on FT_t pins in Min (min (VBAT, VDDA, VDDUSB,
VIN(4) VSS - 0.3
VBAT mode VDDIO2) + 4.0, 6.0)(5)(6)
Input voltage on FT_c pins VSS - 0.3 5.5
Input voltage on any other pins VSS - 0.3 4.0
Allowed voltage difference for
VREF+ - VDDA - 0.4
VREF+ > VDDA
Variations between different VDDx
|∆VDDx| - 50.0
power pins of the same domain
mV
Variations between all the different
|VSSx-VSS| - 50.0
ground pins(7)
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VDDDSI, VBAT) and ground (VSS, VSSA, VSSSMPS) pins
must always be connected to the external power supply, in the permitted range.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed.
For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. VDDIO1 or VDDIO2, VDDIO1 = VDD.
4. VIN maximum must always be respected. Refer to Table 31 for the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
7. Including VREF- pin.
DS13543 Rev 2 185/390

352
Table 31. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1) 200
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 200
(1)
IVDD Maximum current into each VDD power pin (source) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin 20
IIO mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 120
∑I(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 120
IINJ(PIN)(3)(4) Injected current on FT_xx, TT_xx, RST pins -5/+0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDDSI, VDDIO2, VBAT) and ground (VSS, VSSA, VSSSMPS) pins
must always be connected to the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 30 for the minimum
allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN) is the absolute sum of the negative
injected currents (instantaneous values).
Table 32. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150

°C
TJ Maximum junction temperature 140
186/390 DS13543 Rev 2

5.3 Operating conditions
5.3.1 General operating conditions
Table 33. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit
IO_VDD_HSLV(1) = 0 1.71(2) - 3.6

Standard operating
VDD
voltage
IO_VDD_HSLV = 1 1.71(2) - 2.7
Supply voltage for

the internal SMPS
VDDSMPS - VDD
step-down
converter
At least one I/O in
PG[15:2] used, 1.08 - 3.6
IO_VDDIO2_HSLV = 0
Supply voltage for
VDDIO2 At least one I/O in
PG[15:2] I/Os
PG[15:2] used, 1.08 - 2.7
IO_VDDIO2_HSLV = 1
PG[15:2] I/Os not used 0 - 3.6
USB used 3.0 - 3.6
VDDUSB USB supply voltage
USB not used 0 - 3.6
COMP used 1.58 - 3.6 V
DAC or OPAMP used 1.60 - 3.6

ADC used 1.62 - 3.6
Analog supply
VDDA VREFBUF used
voltage 1.8 - 3.6
(normal mode)
ADC, DAC, COMP,
OPAMP, and VREFBUF 0 - 3.6
not used
Backup domain
VBAT - 1.65(3) - 3.6
supply voltage
All I/Os except FT_c and Min(min(VDD, VDDA, VDDUSB,
-0.3 -
TT_xx pins VDDIO2) +3.6, 5.5)(4)(5)
Min(min(VBAT, VDDA,
Input voltage on FT_t pins
VIN I/O input voltage -0.3 - VDDUSB, VDDIO2) + 3.6,
in VBAT mode
5.5)(4)(5)
FT_c I/Os -0.3 - 5.0
TT_xx I/Os -0.3 - VDDIOx + 0.3
Sum of output
current sourced by
IIO_SW - - - 3 mA
all I/Os powered by
VSW(6)
DS13543 Rev 2 187/390

352
Table 33. General operating conditions (continued)

Range 1 1.15 1.21 1.27
Internal regulator Range 2 1.05 1.1 1.15

VCORE V
ON Range 3 0.95 1.0 1.05
Range 4 0.81 0.9 0.99
Range 1 - - 160
AHB clock Range 2 - - 110

fHCLK
frequency Range 3 - - 55
Range 4 - - 25
MHz
Range 1 - - 160
APB1, APB2, Range 2 - - 110
fPCLKx
APB3 clock
(x = 1, 2, 3) frequency Range 3 - - 55
Range 4 - - 25
LQFP64
LPQF100
UFBGA132
Power dissipation LQFP144
at TA = 85 °C
for suffix 6(7) WLCSP150
TFBGA169
See Section 6.9: Package thermal
WLCSP208 characteristics for application appropriate
TFBGA216 thermal resistance and package. The power
PD dissipation is then calculated according mW
LQFP64 ambient temperature (TA) and maximum
LPQF100 junction temperature (TJ) and selected thermal
resistance.
UFBGA132
Power dissipation LQFP144
at TA = 125 °C
for suffix 3(7) WLCSP150
TFBGA169
WLCSP208
TFBGA216
188/390 DS13543 Rev 2

Table 33. General operating conditions (continued)

Ambient Maximum power

–40 85
temperature dissipation
for suffix 6 Low-power dissipation(8) –40 105
TA
Ambient Maximum power
–40 125 °C
temperature dissipation
for suffix 3 Low-power dissipation(8) –40 130
Junction Suffix 6 version –40 105

TJ
temperature range Suffix 3 version –40 130
1. HSLV means high-speed low-voltage mode (refer to the product reference manual).
2. When RESET is released, the functionality is guaranteed down to VBORx min.
3. In VBAT mode, the functionality is guaranteed down to VBOR_VBAT min.
4. This formula has to be applied only on the power supplies related to the I/O structure described by the pin definition table.
The maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDDUSB, VDDIO2)+3.6 V, and 5.5V.
5. For operation with voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors
must be disabled.
6. The I/Os powered by VSW are:
- PC13, PC14, PC15 when VDD is present,
- PC13, PC14, PC15, and all FT_t I/Os in VBAT mode.
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Section 6.9: Package thermal
characteristics).
8. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Section 6.9:
Package thermal characteristics).
5.3.2 Operating conditions at power-up/power-down

The parameters given in the table below are derived from tests performed under the
ambient temperature condition summarized in Table 33.
Table 34. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Max Unit
VDD rise-time rate - 0 ∞

µs/V
ULPMEN = 0 (default value) 20 ∞
tVDD
VDD fall-time rate Standby mode, BOR level 0 selected
250 ∞ ms/V
with ULPMEN = 1
DS13543 Rev 2 189/390

352
5.3.3 Embedded reset and power control block characteristics

ambient temperature conditions summarized in Table 33.
Table 35. Embedded reset and power control block characteristics(1)

Reset temporization after BOR0 is

tRSTTEMPO(2) VDD rising - - 900 μs
detected
Rising edge 1.6 1.66 1.71
Falling edge, range 1, 2, 3 1.58 1.64 1.69
VBOR0 Brownout reset threshold 0
Falling edge, range 4 and
1.58 1.64 1.69
low-power modes
Rising edge 1.98 2.08 2.17
Falling edge 1.9 2.00 2.1
Rising edge 2.18 2.29 2.39
Programmable voltage detector Rising edge 2.03 2.13 2.23

VPVD0 V
threshold 0 Falling edge 1.93 2.03 2.12
Rising edge 2.18 2.29 2.39
VPVD1 PVD threshold 1
Rising edge 2.33 2.44 2.55
Rising edge 2.83 2.96 3.08
Vhyst_BOR0 Hysteresis voltage of BOR0 - - 20 -
Hysteresis voltage of BOR mV
Vhyst_BOR_PVD - - 80 -
(except BOR0) and PVD
tBOR0 _sampling BOR0 sampling period ULPMEN = 1 - 30 55 ms
190/390 DS13543 Rev 2

Table 35. Embedded reset and power control block characteristics(1) (continued)
Additional BOR0 consumption if

IDD_BOR0(2) Standby mode - 60 - nA
ULPMEN = 0 versus ULPMEN = 1
BOR(3) (except BOR0) and PVD
IDD_BOR_PVD(2) - - 1 1.5 µA
consumption from VDD(4)
VBOR_VBAT VBAT brownout reset threshold - 1.58 - 1.65 V
tVBAT_BOR VBAT BOR sampling period
MONEN = 0(5) - 0.5 2.5 s
_sampling in VBAT mode
Rising edge 1.61 1.68 1.75
VAVM1 VDDA voltage monitor 1 threshold
Rising edge 1.77 1.86 1.95
VAVM2 VDDA voltage monitor 2 threshold V
VIO2VM VDDIO2 voltage monitor threshold - 0.96 1.01 1.05
VUVM VDDUSB voltage monitor threshold - 1.15 1.22 1.28
Vhyst_AVM Hysteresis of VDDA voltage monitor - - 40 - mV
Voltage monitor consumption from
IDD_VM(2) VDD (AVM1, AVM2, IO2VM or UVM - - 0.4 0.6
single instance) µA
VDDA voltage monitor consumption
IDD_AVM_A(2) - - 1.25 1.85
from VDDA (resistor bridge)
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. Specified by design. Not tested in production
3. BOR0 is enabled in all modes (except Shutdown), and its consumption is therefore included in the supply current
characteristics tables.
4. This is also the consumption saved in Standby mode when ULPMEN = 1.
5. VBAT brownout reset monitoring is discontinuous when MONEN = 0 in PWR_BDCR1, and is continuous when MONEN = 1.
5.3.4 SMPS characteristics
Table 36. SMPS characteristics

Symbol Parameter Conditions Typ Unit
VDD > 1.9 V 3

Freq Switching frequency (range 1, 2, 3)(1) MHz
VDD < 1.9 V 1.5
1. The SMPS is asynchronous in range 4 and low-power modes.
DS13543 Rev 2 191/390

352
5.3.5 Embedded voltage reference

ambient temperature and supply voltage conditions summarized in Table 33.
Table 37. Embedded internal voltage reference

Range 1, 2, 3 1.175 1.215 1.255

VREFINT(1) Internal reference voltage Range 4 and V
1.170 1.215 1.260
low-power modes
ADC sampling time when reading
tS_vrefint(2)(3) - 12.65 - -
the internal reference voltage
µs
Start time of reference voltage buffer
tstart_vrefint(3) - - 4 6
when the ADC is enabled
IDD(VREFINTBUF) VREFINT buffer consumption from
(3) - - 1.5 2.1 µA
VDD when converted by the ADC
Internal reference voltage spread
∆VREFINT(4) VDD = 3 V - 6 11.5 mV
over the temperature range
TCoeff(4) Average temperature coefficient –40°C < TJ < +130 °C - 40 125 ppm/°C
ACoeff(3) Long term stability 1000 hours, TJ = 25 °C - 400 1000 ppm
(4)
VDDCoeff Average voltage coefficient 3.0 V ≤ VDD ≤ 3.6 V - 500 2900 ppm/V
VREFINT_DIV1(3) 1/4 reference voltage 24 25 26
%
VREFINT_DIV2(3) 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3(3) 3/4 reference voltage 74 75 76
1. VREFINT does not take into account package and soldering effects.
2. The shortest sampling time for the application can be determined by multiple iterations.
3. Specified by design. Not tested in production
4. Evaluated by characterization. Not tested in production.
192/390 DS13543 Rev 2

Figure 26. VREFINT versus temperature
MSv69159V1
5.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Section 5.1.7: Current consumption
measurement.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait-state number,
depending on the fHCLK frequency (refer to the tables “Number of wait states according
to CPU clock (HCLK) frequency” available in the product reference manual).
• When the peripherals are enabled, fPCLK = fHCLK.
• The voltage scaling range is adjusted to fHCLK frequency as follows:
– Voltage range 1 for 110 MHz < fHCLK ≤ 160 MHz
– Voltage range 4 for fHCLK ≤ 25 MHz
The parameters given in the tables below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33. These parameters are
evaluated by characterization, and not tested in production unless otherwise specified.
DS13543 Rev 2 193/390

352
194/390
Electrical characteristics
Table 38. Current consumption in Run mode on LDO, code with data processing
running from flash memory, ICACHE ON in 1-way, prefetch ON(1)
Conditions Typ Max at 1.71 V ≤ VDD ≤ 3.6 V(2)
Symbol
Parameter Unit
- Voltage fHCLK 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
scaling (MHz)
24 1.85 2.50 4.45 7.4 13.0 3.1 4.8 11 20 37
16 1.45 2.10 4.05 7 12.5 2.7 4.4 11 19 36
12 1.20 1.80 3.80 6.7 12.0 2.4 4.0 9.9 19 36
fHCLK = fMSI,
all peripherals disabled, 4 0.65 1.30 3.25 6.15 11.5 1.8 3.5 9.3 18 35
Range 4
Flash bank 2 in power down, 2 0.53 1.15 3.10 6.05 11.5 1.6 3.3 9.2 18 35
all SRAMs enabled
1 0.47 1.10 3.05 6.0 11.5 1.6 3.3 9.1 18 35
0.4 0.43 1.05 3.00 5.95 11.5 1.5 3.2 9 18 35
DS13543 Rev 2
0.1 0.41 1.05 3.00 5.9 11.5 1.5 3.2 9 18 35

Supply
IDD 160 14.0 15.5 18.5 23.5 31.5 19 23 36 56 93
current in mA
(Run) Run mode
fHCLK = PLL on HSE 16 MHz Range 1 140 12.5 14.0 17.0 22 30.0 17 21 34 54 91
in bypass mode,
120 11.0 12.0 15.5 20 28.5 15 19 33 52 90
all peripherals disabled,
Flash bank 2 in power down, 110 9.15 10.0 13.0 17 24.0 12 15 26 41 68
all SRAMs enabled Range 2 72 6.35 7.35 10.0 14 21.0 9 12 22 37 65
64 5.80 6.75 9.50 13.5 20.5 8.4 12 22 37 65
fHCLK = fHSE bypass mode, 55 4.60 5.40 7.70 11 17.5 6.5 8.7 17 28 50
Range 3
Flash bank 2 in power down, 32 2.95 3.75 6.05 9.5 15.5 4.7 6.9 15 26 48
all SRAMs enabled
1. The current consumption from SRAM is similar.
STM32U5Axxx
STM32U5Axxx
running from flash memory, ICACHE ON in 1-way, prefetch ON(1)
Conditions Typ at VDD = 1.8 V Max at 1.71 V ≤ VDD ≤ 3.6 V(2)(3)
Symbol
Parameter Unit
scaling (MHz)
24 1.20 1.50 2.65 4.40 7.60 2.1 2.9 7 13 23
16 0.93 1.25 2.40 4.15 7.35 1.8 2.6 6 12 23
12 0.80 1.10 2.25 4.00 7.20 1.6 2.5 6.3 12 22
fHCLK = fMSI,
Range 4
Flash bank 2 in power down, 2 0.31 0.65 1.85 3.60 6.80 1.0 2 5.8 12 22
all SRAMs enabled
1 0.27 0.60 1.85 3.55 6.80 1.0 1.9 5.8 12 22
0.4 0.25 0.58 1.80 3.55 6.75 0.9 1.8 6 12 22
0.1 0.24 0.57 1.80 3.55 6.75 0.9 1.8 6 12 22
DS13543 Rev 2
Supply
IDD 160 11.5 12.0 14.5 18.0 24.0 15 17 27 40 64
current in mA
(Run) Run mode
fHCLK = PLL on HSE 16 MHz Range 1 140 10.0 10.5 13.0 16.5 22.5 14 16 25 38 62
in bypass mode,
120 8.75 9.35 12.0 15.5 21.5 12 14 24 37 61
Flash bank 2 in power down, 110 6.75 7.15 9.05 12.0 16.5 9 11 18 28 45
all SRAMs enabled Range 2 72 4.75 5.20 7.10 9.80 14.5 7 9 16 25 43
64 4.30 4.80 6.70 9.40 14.0 6.2 8 15 25 42
fHCLK = fHSE bypass mode, 55 3.15 3.55 5.00 7.15 11.0 4.5 6 11 19 32
Range 3
Flash bank 2 in power down,
32 2.10 2.50 4.00 6.15 10.0 3.3 4.5 10 17 31
all SRAMs enabled
3. The maximum value is at VDD = 1.71 V in Run mode on SMPS.
195/390
196/390
running from flash memory, ICACHE ON in 1-way, prefetch ON, VDD = 3.0 V(1)
Conditions Typ at VDD = 3.0 V Max at VDD = 3.0 V(2)
Symbol
Parameter Unit
scaling (MHz)
24 0.77 0.95 1.65 2.75 4.75 1.3 1.9 4.0 7 14
16 0.61 0.80 1.50 2.60 4.60 1.2 1.7 3.9 7 14
12 0.50 0.70 1.40 2.50 4.50 1.0 1.6 3.8 7 13
fHCLK = fMSI,
Range 4
Flash bank 2 in power down, 2 0.23 0.45 1.20 2.25 4.25 0.7 1.3 3.6 7 13
all SRAMs enabled
1 0.21 0.43 1.15 2.25 4.25 0.7 1.3 3.5 7 13
0.4 0.19 0.42 1.15 2.25 4.25 0.7 1.3 3.5 7 13
0.1 0.18 0.41 1.15 2.20 4.20 0.7 1.3 3.5 7 13
DS13543 Rev 2
Supply
IDD 160 7.60 8.00 9.70 12.0 16.0 10 11 17 25 39
current in mA
(Run) Run mode
fHCLK = PLL on HSE 16 MHz Range 1 140 6.80 7.20 8.90 11.5 15.5 9 10 16 24 39
in bypass mode,
120 5.95 6.40 8.05 10.5 14.5 8 9 15 23 38
Flash bank 2 in power down, 110 4.65 5.00 6.25 8.05 11.5 6 7 12 17 28
all SRAMs enabled Range 2 72 3.30 3.70 4.95 6.75 10.0 4.5 5.6 10 16 27
64 3.05 3.45 4.70 6.50 9.75 4.3 5.3 9 16 26
fHCLK = fHSE bypass mode, 55 2.30 2.60 3.60 5.05 7.70 3.2 4.0 7 12 20
Range 3
Flash bank 2 in power down, 32 1.55 1.90 2.85 4.30 6.95 2.4 3.2 6 11 19
all SRAMs enabled
STM32U5Axxx
STM32U5Axxx
running from flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ Typ
Symbol
Parameter Unit Unit
- Voltage Code 1.8 V 3V 3.3 V 1.8 V 3V 3.3 V
scaling
Reduced Code 1.85 1.85 1.85 77 77 77
CoreMark 1.85 1.85 1.85 77 77 77
fHCLK = fMSI = 24 MHz,
all peripherals disabled, SecureMark 2 2 2 83 83 83
Range 4
Flash bank 2 in power down, Dhrystone 2.1 1.95 1.95 1.95 81 81 81
all SRAMs enabled
Fibonacci 1.6 1.6 1.6 67 67 67
While(1) 1.4 1.4 1.4 58 58 58
Reduced Code 14 14 14 88 88 88
fHCLK = fPLL = 160 MHz,
CoreMark 14.5 14.5 14.5 91 91 91
DS13543 Rev 2
PLL on HSE 16 MHz in bypass

Supply mode, SecureMark 16 16 16 100 100 100
IDD
current in Range 1 mA µA/MHz
(Run) all peripherals disabled, Dhrystone 2.1 15 15 15 94 94 94
Run mode
Fibonacci 11.5 11.5 11.5 72 72 72
all SRAMs enabled
While(1) 10.5 10.5 10.5 66 66 66
Reduced Code 9.15 9.15 9.15 83 83 83
CoreMark 9.2 9.25 9.25 84 84 84
mode, SecureMark 10 10 10 91 91 91
Range 2
all peripherals disabled, Dhrystone 2.1 9.75 9.8 9.8 89 89 89
Fibonacci 7.55 7.6 7.6 69 69 69
all SRAMs enabled
While(1) 6.7 6.75 6.75 61 61 61
197/390
198/390
running from flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
Conditions Typ Typ
Symbol
Parameter Unit Unit
scaling
Reduced Code 4.5 4.6 4.6 82 84 84
CoreMark 4.6 4.65 4.7 84 85 85
fHCLK = fHSE = 55 MHz,
Supply SecureMark 5 5.05 5.1 91 92 93
IDD all peripherals disabled,
(Run) Flash bank 2 in power down, Dhrystone 2.1 4.85 4.9 4.9 88 89 89
Run mode
all SRAMs enabled
Fibonacci 3.7 3.8 3.8 67 69 69
While(1) 3.25 3.35 3.35 59 61 61
DS13543 Rev 2
STM32U5Axxx
STM32U5Axxx
running from flash memory, ICACHE ON (1-way), prefetch ON(1)
Conditions Typ Typ
Symbol
Parameter Unit Unit
scaling
Reduced Code 1.2 0.77 0.7 50 32 29
CoreMark 1.2 0.77 0.7 50 32 29
all peripherals disabled, SecureMark 1.3 0.83 0.76 54 35 31
Range 4
Flash bank 2 in power down, Dhrystone 2.1 1.25 0.81 0.74 52 34 31
all SRAMs enabled
Fibonacci 1.05 0.66 0.61 44 27 25
While(1) 0.94 0.61 0.54 39 25 22
Reduced Code 11.5 7.6 7.1 72 48 44
CoreMark 11.5 7.65 7.15 72 48 45
DS13543 Rev 2

Supply mode, SecureMark 12.5 8.4 7.85 78 53 49
IDD
(Run) all peripherals disabled, Dhrystone 2.1 12.0 8.1 7.55 75 51 47
Run mode
Fibonacci 9.35 6.35 5.9 58 40 37
all SRAMs enabled
While(1) 8.3 5.65 5.3 52 35 33
Reduced Code 6.75 4.65 4.35 61 42 40
CoreMark 6.8 4.7 4.4 62 43 40
mode, SecureMark 7.45 5.1 4.8 68 46 44
Range 2
all peripherals disabled, Dhrystone 2.1 7.2 4.95 4.6 65 45 42
Fibonacci 5.6 3.9 3.7 51 35 34
all SRAMs enabled
While(1) 5.0 3.5 3.3 45 32 30
199/390
200/390
running from flash memory, ICACHE ON (1-way), prefetch ON(1) (continued)
Conditions Typ Typ
Symbol
Parameter Unit Unit
scaling
Reduced Code 3.15 2.3 2.2 57 42 40
CoreMark 3.2 2.35 2.2 58 43 40
fHCLK = fHSE = 55 MHz,
Supply SecureMark 3.5 2.5 2.4 64 45 44
IDD all peripherals disabled,
(Run) Flash bank 2 in power down, Dhrystone 2.1 3.35 2.45 2.3 61 45 42
Run mode
all SRAMs enabled
Fibonacci 2.65 1.95 1.85 48 35 34
While(1) 2.35 1.75 1.7 43 32 31
DS13543 Rev 2
Table 43. Typical current consumption in Run mode on LDO, with different codes running
from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
Conditions Typ Typ
Symbol
Parameter Unit Unit

scaling
Reduced Code 1.65 1.65 1.65 68.8 68.8 68.8
CoreMark 1.65 1.65 1.65 68.8 68.8 68.8
Supply SecureMark 1.8 1.8 1.8 75 75 75
IDD Flash bank 1 in Low power,
(Run) Run mode Flash bank 2 in power down, Dhrystone 2.1 1.75 1.75 1.75 72.9 72.9 72.9
SRAM2 enabled,
Fibonacci 1.4 1.4 1.4 58.3 58.3 58.3
SRAM1/3/4/5 in power down
While(1) 1.2 1.2 1.2 50 50 50
STM32U5Axxx
Table 44. Typical current consumption in Run mode on SMPS, with different codes running
STM32U5Axxx
from flash memory in low-power mode, ICACHE ON (1-way), prefetch ON
Conditions Typ Typ
Symbol
Parameter Unit Unit
scaling
Reduced Code 1.05 0.66 0.61 43.8 27.5 25.4
CoreMark 1.05 0.66 0.61 43.8 27.5 25.4
Supply SecureMark 1.15 0.73 0.67 47.9 30.4 27.7
IDD Flash bank 1 in low power,
(Run) Run mode Flash bank 2 in power down, Dhrystone 2.1 1.10 0.70 0.65 45.8 29.2 26.9
SRAM2 enabled,
Fibonacci 0.94 0.56 0.52 39 23.3 21.5
SRAM1/3/4/5 in power down
While(1) 0.80 0.49 0.45 33.3 20.2 18.5
DS13543 Rev 2
201/390
Table 45. Current consumption in Sleep mode on LDO, flash memory in power down
202/390
Conditions Typ Max at 1.71 V ≤ VDD ≤ 3.6 V(1)
Symbol
Parameter Unit
scaling (MHz)
24 0.75 1.35 3.30 6.25 11.5 1.8 3.4 9.2 18 34
16 0.63 1.25 3.20 6.10 11.5 1.6 3.3 9.1 18 34
12 0.57 1.20 3.15 6.05 11.5 1.6 3.2 9.0 18 34
fHCLK = fMSI, 4 0.42 1.05 3.00 5.90 11.5 1.4 3.1 8.9 18 34
Range 4
all peripherals disabled 2 0.39 1.00 2.95 5.85 11.0 1.4 3.0 8.8 18 33
1 0.37 1.00 2.95 5.85 11.0 1.3 3.0 8.8 18 33
0.4 0.36 0.99 2.90 5.85 11.0 1.3 3.0 8.7 18 33
Supply 0.1 0.36 0.98 2.90 5.85 11.0 1.3 3.0 8.7 18 33
IDD
current in mA
DS13543 Rev 2
(Sleep) Sleep mode 160 4.80 6.00 9.15 14.0 22.0 7.7 11 21 37 64
Range 1 140 4.40 5.55 8.70 13.5 21.5 7.2 9.7 21 36 64
fHCLK = PLL on HSE 120 3.95 5.10 8.25 13.0 21.0 6.7 9.2 20 36 63
16 MHz in bypass mode,
all peripherals disabled 110 3.25 4.20 6.90 11.0 18.0 5.3 8.2 19 34 60
Range 2 72 2.50 3.45 6.15 10.0 17.0 4.5 7.4 18 33 59
64 2.35 3.30 5.95 9.90 17.0 4.3 7.2 18 33 59
Range 3
STM32U5Axxx
Table 46. Current consumption in Sleep mode on SMPS, flash memory in power down
STM32U5Axxx
Conditions Typ at VDD = 1.8 V Max at 1.71 V ≤ VDD ≤ 3.6 V(1)(2)
Symbol
Parameter Unit
scaling (MHz)
24 0.47 0.86 1.95 3.7 6.85 1.1 2.1 5.8 12 22
16 0.39 0.75 1.90 3.6 6.80 1.0 1.9 5.7 12 22
12 0.36 0.69 1.85 3.6 6.75 0.9 1.9 5.7 12 22
fHCLK = fMSI, 4 0.22 0.55 1.75 3.5 6.65 0.8 1.7 5.6 11 21
Range 4
1 0.20 0.52 1.75 3.45 6.65 0.7 1.7 5.6 11 21
0.4 0.19 0.52 1.75 3.45 6.65 0.7 1.7 5.6 11 21
Supply 0.1 0.19 0.51 1.75 3.45 6.65 0.7 1.7 5.6 11 21
IDD
current in mA
DS13543 Rev 2
(Sleep) Sleep mode 160 3.95 4.70 7.10 10.5 16.5 5.9 8 18 31 55
Range 1 140 3.60 4.35 6.75 10.0 16.5 5.5 8 18 30 55
fHCLK = PLL on HSE 120 3.25 4.00 6.40 9.85 16.0 5.1 7 17 30 54
Range 2 72 1.95 2.50 4.35 7.05 12.0 3.3 4.9 12 22 40
64 1.80 2.40 4.25 6.95 11.5 3.1 4.8 12 22 39
Range 3
2. The maximum value is at VDD = 1.71 V in Sleep mode on SMPS.
203/390
Table 47. Current consumption in Sleep mode on SMPS,
204/390
flash memory in power down, VDD = 3.0 V
Conditions Typ at VDD = 3.0 V Max at VDD = 3.0 V(1)
Symbol
Parameter Unit
scaling (MHz)
24 0.29 0.50 1.20 2.30 4.25 0.7 1.3 3.4 7 13
16 0.25 0.46 1.15 2.25 4.20 0.6 1.2 3.3 7 13
12 0.22 0.44 1.15 2.20 4.20 0.6 1.2 3.3 7 13
fHCLK = fMSI, 4 0.16 0.38 1.10 2.15 4.15 0.5 1.1 3.3 7 13
Range 4
1 0.14 0.36 1.05 2.15 4.10 0.5 1.1 3.2 7 13
0.4 0.14 0.36 1.05 2.15 4.10 0.5 1.1 3.2 7 13
Supply 0.1 0.14 0.36 1.05 2.15 4.10 0.5 1.1 3.2 7 13
DS13543 Rev 2
IDD
current in mA
(Sleep) Sleep mode 160 2.80 3.35 4.95 7.20 11.5 4.0 5.5 11 19 34
Range 1 140 2.55 3.10 4.70 7.00 11.0 3.8 5.2 11 19 33
fHCLK = PLL on HSE 120 2.35 2.85 4.45 6.75 11.0 3.5 5.0 11 19 33
Range 2 72 1.50 1.90 3.15 4.90 8.10 2.3 3.4 7 14 24
64 1.40 1.85 3.05 4.85 8.05 2.2 3.4 7 14 24
fHCLK = fHSE bypass mode, 55 1.05 1.35 2.35 3.75 6.35 1.7 2.5 5.4 10 18
Range 3
STM32U5Axxx
Table 48. SRAM1/SRAM3/SRAM5 current consumption in Run/Sleep mode with LDO and SMPS
STM32U5Axxx
Conditions Typ Max
Symbol
Parameter Unit
scaling (MHz)
Range 4 24 0.05 0.16 0.50 1.00 2.00 0.20 0.48 1.5 3.0 6.0
SRAM1 supply current in
IDD Run/Sleep mode Range 1 160 0.15 0.32 0.85 1.65 3.10 0.53 0.96 2.6 5.0 9.3
(SRAM1) (SRAM1PD = 1 versus Range 2 110 0.11 0.25 0.71 1.40 2.65 0.38 0.75 2.2 4.2 8.0
SRAM1PD = 0)
Range 3 55 0.08 0.20 0.59 1.20 2.30 0.28 0.60 1.8 3.6 6.9
Range 4 24 0.06 0.17 0.53 1.10 2.10 0.22 0.51 1.6 3.3 6.3
LDO mA
SRAM3PD = 0)
Range 3 55 0.08 0.21 0.63 1.25 2.45 0.30 0.63 1.9 3.8 7.4
DS13543 Rev 2
Range 4 24 0.06 0.17 0.53 1.10 2.15 0.22 0.51 1.6 3.3 6.5
SRAM5PD = 0)
Range 3 55 0.08 0.22 0.64 1.25 2.45 0.30 0.65 2.0 3.8 7.4
205/390
Table 48. SRAM1/SRAM3/SRAM5 current consumption in Run/Sleep mode with LDO and SMPS (continued)
206/390
Conditions Typ Max
Symbol
Parameter Unit
scaling (MHz)
Range 4 24 0.04 0.10 0.29 0.63 1.21 0.14 0.32 0.93 2.0 3.9
SRAM1PD = 0)
Range 3 55 0.05 0.14 0.41 0.83 1.60 0.21 0.44 1.3 2.7 5.1
Range 4 24 0.04 0.11 0.31 0.66 1.29 0.15 0.34 0.98 2.1 4.1
SMPS(1) mA
SRAM3PD = 0)
Range 3 55 0.06 0.15 0.44 0.88 1.67 0.23 0.47 1.4 2.8 5.3
DS13543 Rev 2
Range 4 24 0.04 0.11 0.32 0.67 1.30 0.15 0.34 1.0 2.2 4.2
SRAM5PD = 0)
Range 3 55 0.06 0.15 0.44 0.89 1.75 0.23 0.48 1.4 2.9 5.6
STM32U5Axxx
Table 48. SRAM1/SRAM3/SRAM5 current consumption in Run/Sleep mode with LDO and SMPS (continued)
STM32U5Axxx
Conditions Typ Max
Symbol
Parameter Unit
scaling (MHz)
Range 4 24 0.02 0.06 0.18 0.38 0.73 0.08 0.18 0.53 1.2 2.2
SRAM1PD = 0)
Range 3 55 0.03 0.08 0.25 0.50 0.96 0.12 0.25 0.74 1.5 2.9
Range 4 24 0.02 0.06 0.19 0.40 0.78 0.09 0.19 0.56 1.2 2.4
IDD SMPS Run/Sleep mode Range 1 160 0.07 0.17 0.45 0.87 1.60 0.27 0.51 1.4 2.6 4.8
mA
(SRAM3) (VDD = 3.0V) (SRAM3PD = 1 versus Range 2 110 0.05 0.12 0.34 0.67 1.25 0.19 0.36 1.1 2.1 3.8
SRAM3PD = 0)
Range 3 55 0.04 0.09 0.27 0.53 1.00 0.13 0.27 0.80 1.6 3.0
DS13543 Rev 2
Range 4 24 0.02 0.06 0.19 0.40 0.78 0.09 0.20 0.57 1.2 2.4
SRAM5PD = 0)
Range 3 55 0.04 0.09 0.27 0.54 1.05 0.13 0.27 0.80 1.7 3.2
1. The typical value is measured at VDD = 1.8 V. The maximum value is for 1.71 ≤ VDD ≤ 3.6V and is at VDD = 1.71 V in Run/Sleep mode on SMPS.
207/390
Table 49. Static power consumption of flash memory banks when supplied by LDO or SMPS
208/390
Typ Max
Symbol Parameter Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
Flash bank 1 static consumption

IDD(Flash_Bank1)(1) in normal mode 46 50 60 75 105 63 74 93 114 160
(PD1 = 1 versus PD1 = 0)
Flash bank 2 static consumption
IDD(Flash_Bank2)(1) in normal mode 47 51 61 75 105 64 75 94 114 160
µA
(PD2 = 1 versus PD2 = 0)
One Flash bank additional static
consumption in normal mode
IDD(Flash_Bank_LPM)(2) versus low-power mode 25 25 26 27 30 34 37 41 45 50
(LPM = 0 versus. LPM = 1)
1. When the flash memory is in power down in Sleep mode (SLEEP_PD = 1), Bank 1 and Bank 2 are in power down.
DS13543 Rev 2
2. If no bank is in power down, the additional static consumption of the flash memory in normal mode versus low-power mode is 2 × IDD(Flash_Bank_LPM).
STM32U5Axxx
Table 50. Current consumption in Stop 0 mode on LDO
STM32U5Axxx
Conditions Typ Max(1)
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 150 390 1100 2150 4000 550 1200 3300 6500 12000
Supply current in Stop 0 mode,
2.4 150 390 1100 2150 4000 550 1200 3300 6500 12000
regulator in range 4,
RTC disabled, 3 150 390 1100 2150 4050 550 1200 3300 6500 13000
8-Kbyte SRAM2 + ICACHE 3.3 150 390 1100 2150 4050 550 1200 3300 6500 13000
retained
3.6 155 390 1100 2150 4050 560 1200 3300 6500 13000
IDD(Stop 0) µA
1.8 190 465 1300 2600 4950 690 1400 3900 7800 15000
Supply current in Stop 0 mode, 2.4 190 465 1300 2600 5000 690 1400 3900 7800 15000
3 190 465 1300 2600 5000 690 1400 3900 7800 15000
RTC disabled,
all SRAMs retained 3.3 190 465 1300 2600 5000 690 1400 3900 7800 15000
DS13543 Rev 2
3.6 190 470 1300 2600 5000 690 1500 3900 7800 15000
209/390
Table 51. Current consumption in Stop 0 mode on SMPS
210/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 25°C 55°C 85°C 105°C 125°C
1.8 71 195 580 1250 2400 260 590 1800 3800 7200
2.4 57 155 465 965 1850 210 470 1400 2900 5600
RTC disabled, 3 50 135 400 790 1500 190 410 1200 2400 4500
retained
3.6 45 120 345 680 1300 170 360 1100 2100 3900
IDD(Stop 0) µA
1.8 92 230 815 1550 2950 330 690 2500 4700 8900
3 64 165 480 965 1850 240 500 1500 2900 5600
RTC disabled,
all SRAMs retained 3.3 60 150 445 880 1700 220 450 1400 2700 5100
DS13543 Rev 2
3.6 57 145 415 825 1600 210 440 1300 2500 4800
STM32U5Axxx
STM32U5Axxx
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 115 340 1000 2000 3800 420 1100 3000 6000 12000
2.4 125 345 1000 2000 3800 460 1100 3000 6000 12000
RTC disabled, 3 125 345 1050 2000 3850 460 1100 3200 6000 12000
retained
3.6 120 345 1050 2050 3850 440 1100 3200 6200 12000
IDD(Stop 1)
1.8 145 415 1250 2450 4750 530 1300 3800 7400 15000
2.4 155 410 1250 2450 4750 560 1300 3800 7400 15000
RTC disabled, 3 160 415 1250 2450 4800 580 1300 3800 7400 15000
all SRAMs retained
3.3 160 415 1250 2450 4750 580 1300 3800 7400 15000
DS13543 Rev 2
3.6 150 405 1250 2450 4800 550 1300 3800 7400 15000
µA
1.8 115 345 1000 2000 3800 420 1100 3000 6000 12000
RTC(2) clocked by LSI 32 kHz,
3 125 345 1050 2000 3850 460 1100 3200 6000 12000
8-Kbyte SRAM2 + ICACHE
retained 3.3 130 350 1050 2000 3850 470 1100 3200 6000 12000
IDD(Stop 1 3.6 120 345 1050 2050 3850 440 1100 3200 6200 12000
with RTC) 1.8 115 350 1000 2000 3750 420 1100 3000 6000 12000
2.4 125 350 1000 2000 3750 460 1100 3000 6000 12000
RTC(2) clocked by LSE
bypassed at 32768 Hz, 3 120 340 1000 2000 3750 460 1100 3200 6000 12000
3.3 130 345 1000 2000 3800 470 1100 3200 6000 12000
retained
3.6 120 350 1050 2000 3800 440 1100 3200 6200 12000
211/390
Table 52. Current consumption in Stop 1 mode on LDO (continued)
212/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
Supply current in Stop 1 mode, 1.8 135 340 1000 2000 3700 - - - - -
RTC(2) clocked by LSE quartz 2.4 140 340 1000 2000 3750 - - - - -
IDD(Stop 1 in low-drive mode,
3 135 340 1000 2000 3750 - - - - - µA
with RTC) RCC_BDCR.LSESYSEN = 0,
8-Kbyte SRAM2 + ICACHE 3.3 135 345 1000 2000 3750 - - - - -
retained
3.6 135 340 1050 2000 3800 - - - - -
2. RTC with default configuration but RTC_CALR.LPCAL = 1.
DS13543 Rev 2
STM32U5Axxx
STM32U5Axxx
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 71 195 580 1250 2400 260 590 1800 3800 7200
RTC disabled,
3 50 135 400 790 1500 180 410 1200 2400 4500
retained 3.3 46 125 370 725 1400 170 380 1200 2200 4200
3.6 44 120 345 680 1300 160 360 1100 2100 3900
IDD(Stop 1)
1.8 91 230 815 1550 2950 330 690 2500 4700 8900
2.4 74 185 575 1150 2250 270 560 1800 3500 6800
RTC disabled, 3 64 165 480 965 1850 240 500 1500 2900 5600
all SRAMs retained
3.3 60 150 445 880 1700 220 450 1400 2700 5100
DS13543 Rev 2
3.6 57 145 415 820 1600 210 440 1300 2500 4800
µA
1.8 71 195 580 1250 2400 260 590 1800 3800 7200
3 50 135 400 790 1500 190 410 1200 2400 4500
retained 3.3 47 125 370 725 1400 170 380 1200 2200 4200
IDD(Stop 1 3.6 45 120 350 680 1300 170 360 1100 2100 3900
with RTC) 1.8 71 195 585 1250 2400 260 590 1800 3800 7200
2.4 57 160 470 970 1800 210 480 1500 3000 5400
bypassed at 32768 Hz, 3 50 135 400 785 1500 190 410 1200 2400 4500
3.3 47 125 370 725 1400 170 380 1200 2200 4200
retained
3.6 45 120 345 680 1300 170 360 1100 2100 3900
213/390
Table 53. Current consumption in Stop 1 mode on SMPS (continued)
214/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
Supply current in Stop 1 mode, 1.8 79 190 575 1250 2350 - - - - -

RTC(2) clocked by LSE quartz 2.4 62 155 450 975 1800 - - - - -
IDD(Stop 1 in low-drive mode,
3 56 135 400 780 1450 - - - - - µA
with RTC) RCC_BDCR.LSESYSEN = 0,
8-Kbyte SRAM2 + ICACHE 3.3 52 125 370 720 1350 - - - - -
retained
3.6 50 120 345 675 1250 - - - - -
DS13543 Rev 2
STM32U5Axxx
STM32U5Axxx
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 12.5 30 85.5 175 355 46 90 260 530 1100

Supply current in Stop 2 mode, 2.4 12.5 26.5 85.5 175 355 46 80 260 530 1100
RTC disabled,
3 11.5 29 87 180 360 42 87 270 540 1100
retained 3.3 13 28.5 88.5 180 365 47 86 270 540 1100
3.6 12 32 91.5 185 375 44 96 280 560 1200
IDD(Stop 2)
1.8 48 110 310 650 1350 180 330 930 2000 4100
2.4 47 105 310 650 1350 170 320 930 2000 4100
RTC disabled, 3 50 105 310 655 1350 190 320 930 2000 4100
all SRAMs retained
3.3 49.5 110 310 660 1350 180 330 930 2000 4100
DS13543 Rev 2
3.6 55 110 315 665 1350 200 330 950 2000 4100
µA
1.8 12.5 30.5 86 175 355 46 92 260 530 1100
3 12 29.5 87.5 180 360 44 89 270 540 1100
retained 3.3 13.5 29 89.5 180 365 49 87 270 540 1100
IDD(Stop 2 3.6 12.5 32.5 92 185 375 46 98 280 560 1200

with RTC) 1.8 12.5 30 85.5 175 355 46 90 260 530 1100
Supply current in Stop 2 mode, 2.4 12.5 27 86 175 355 46 81 260 530 1100
RTC(2) clocked by LSI 250 Hz,
3 11 29 87 180 360 40 87 270 540 1100
retained 3.3 13 29 89 180 365 47 87 270 540 1100
3.6 12.5 32 91.5 185 375 46 96 280 560 1200
215/390
216/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 12.5 28.5 85 175 345 46 86 260 530 1100

2.4 12.5 29.5 85.5 175 350 46 89 260 530 1100
bypassed at 32768 Hz, 3 12 29.5 87 175 355 44 89 270 530 1100
8-Kbyte SRAM2 + ICACHE 3.3 13.5 29 88 180 360 49 87 270 540 1100
retained
IDD(Stop 2 3.6 12 32 91 185 365 44 96 280 560 1100
µA
with RTC) 1.8 14.5 29.5 85.5 175 345 - - - - -
2.4 14.5 27.5 86 175 345 - - - - -
RTC(2) clocked by LSE quartz
in low-drive mode, 3 12.5 28.5 87 175 350 - - - - -
8-Kbyte SRAM2 + ICACHE 3.3 14.5 29 88.5 180 355 - - - - -
DS13543 Rev 2
retained
3.6 13.5 32 91.5 185 365 - - - - -
Table 55. SRAM static power consumption in Stop 2 when supplied by LDO
Typ Max(1)
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
SRAM1 64 KB page x static consumption

IDD(SRAM1_64kB)(2) 0.7 1.7 5.7 11.5 25.0 2.70 5.10 17.0 35.0 75.0
(SRAM1PDSx = 1 versus SRAM1PDSx = 0)
SRAM2 8KB page 1 static consumption
IDD(SRAM2_8kB)(3) 0.1 0.3 1.5 2.7 6.1 0.46 0.81 4.4 8.0 19.0 µA
(SRAM2PDS1 = 1 versus SRAM2PDS1 = 0)
SRAM2 56 KB page 2 static consumption
STM32U5Axxx
IDD(SRAM2_56kB)(3) 1.0 2.4 7.8 16.5 32.5 3.40 7.10 24.0 50.0 98.0
Table 55. SRAM static power consumption in Stop 2 when supplied by LDO (continued)
STM32U5Axxx
Typ Max(1)
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD(SRAM3_64kB)(4) 0.8 1.8 5.8 12.0 25.0 2.80 5.30 18.0 36.0 75.0
SRAM4 static consumption
IDD(SRAM4) 0.1 0.4 1.8 3.5 7.5 0.37 1.20 5.3 11.0 23.0
(SRAM4PDS = 1 versus SRAM4PDS = 0)
IDD(SRAM5_64kB)(5) 0.8 1.7 5.6 11.5 25.0 2.80 5.10 17.0 35.0 75.0
ICACHE SRAM static consumption
IDD(ICRAM) 0.5 1.4 5.2 10.5 22.5 1.90 4.20 16.0 32.0 68.0
(ICRAMPDS = 1 versus ICRAMPDS = 0)
DCACHE1 SRAM static consumption
IDD(DC1RAM) 0.3 0.5 2.7 5.3 11.0 1.10 1.60 8.0 16.0 33.0
(DC1RAMPDS = 1 versus DC1RAMPDS = 0)
DS13543 Rev 2

IDD(DC2RAM) 0.3 0.5 2.7 5.3 11.0 1.10 1.60 8.0 16.0 33.0 µA
DMA2D SRAM static consumption
IDD(DMA2DRAM) (DMA2DRAMPDS = 1 versus 0.0 0.1 0.4 0.4 1.3 0.07 0.36 1.1 1.2 3.8
DMA2DRAMPDS = 0)
FMAC, FDCAN and USB peripherals SRAM
IDD(PRAM) static consumption 0.1 0.2 0.8 1.3 3.0 0.37 0.69 2.4 3.8 9.0
(PRAMPDS = 1 versus PRAMPDS = 0)
Graphic peripherals (LTDC, GFXMMU) SRAM
IDD(GPRAM) static consumption 0.0 0.2 0.7 1.3 2.0 0.00 0.59 2.2 3.8 5.9
(GPRAMPDS = 1 versus GPRAMPDS = 0)
PKA SRAM static consumption
IDD(PKARAM) 0.1 0.2 0.7 1.3 2.7 0.37 0.48 2.1 3.9 8.0
(PKARAMPDS = 1 versus PKARAMPDS = 0)
2. SRAM1 total consumption is 12 x IDD(SRAM1_64KB).
3. SRAM2 total consumption is IDD(SRAM2_8KB) + IDD(SRAM2_56KB).
217/390

218/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 6.35 15.5 47 97.5 200 23 47 140 290 590

Supply current in Stop 2 mode, 2.4 5.1 12.5 39 82 170 19 38 120 250 500
RTC disabled,
3 4.65 11.5 35.5 75 155 17 34 110 220 460
retained 3.3 4.65 11.5 34.5 72 150 17 34 110 210 440
3.6 5.25 12 35 72 150 18 35 110 210 440
IDD(Stop 2)
1.8 27.5 57.5 165 400 885 99 180 500 1200 2700
2.4 22 46.5 140 285 690 80 140 420 860 2100
RTC disabled, 3 19 41 120 255 535 69 130 360 760 1600
all SRAMs retained
3.3 18 38.5 115 235 495 65 120 350 700 1500
DS13543 Rev 2
3.6 17.5 37.5 105 225 470 62 120 320 670 1400
µA
1.8 6.65 15.5 47 97.5 200 24 47 140 290 590
Supply current in Stop 2 mode, 2.4 5.45 13 39.5 82.5 170 20 39 120 250 500
3 5.10 12 36 75.5 155 19 36 110 230 460
retained 3.3 5.15 12 35 72.5 150 19 36 110 220 440
IDD(Stop 2 3.6 5.85 12.5 35.5 72.5 150 21 36 110 210 440
with RTC) 1.8 6.5 15.5 47 97.5 200 24 47 140 290 590
3 4.75 11.5 36 75 155 17 34 110 220 460
retained 3.3 4.8 11.5 34.5 72.5 150 17 34 110 220 440
3.6 5.4 12.5 35 72 150 19 36 110 210 440
STM32U5Axxx
STM32U5Axxx
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 6.6 15.5 47 97 195 24 47 140 290 580

2.4 5.35 13 40 83 170 20 39 120 250 500
bypassed at 32768 Hz, 3 5 12 36 75 155 18 36 110 220 460
8-Kbyte SRAM2 + ICACHE 3.3 5.1 11.5 35 72.5 150 18 34 110 220 440
retained
IDD(Stop 2 3.6 5.75 12.5 35.5 72 145 20 36 110 210 420
µA
with RTC) 1.8 7.3 15.5 47 97 195 - - - - -
2.4 5.7 13 39 81.5 165 - - - - -
in low-drive mode, 3 5.4 12 36 74.5 150 - - - - -
8-Kbyte SRAM2 + ICACHE 3.3 5.4 11.5 35 72 145 - - - - -
DS13543 Rev 2
retained
3.6 6.1 12.5 35.5 71.5 145 - - - - -
Table 57. SRAM static power consumption in Stop 2 when supplied by SMPS
Typ Max(1)
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD(SRAM1_64kB)(2) 0.4 0.7 2.1 4.5 9.4 1.30 2.10 6.30 14.0 29.0
IDD(SRAM2_8kB)(3) 0.1 0.2 0.5 1.3 2.4 0.28 0.51 1.60 3.80 7.2
µA
(3) SRAM2 56 KB page 2 static consumption
IDD(SRAM2_56kB) 0.4 0.9 2.9 6.2 13.0 1.50 2.90 8.60 19.0 39.0
IDD(SRAM3_64kB)(4) 0.4 0.7 2.2 4.7 9.7 1.30 2.20 6.50 14.0 30.0
219/390

Table 57. SRAM static power consumption in Stop 2 when supplied by SMPS (continued)
220/390
Typ Max(1)
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD(SRAM4) 0.1 0.2 0.6 1.5 2.8 0.38 0.62 1.90 4.40 8.4
IDD(SRAM5_64kB)(5) 0.4 0.7 2.1 4.4 9.4 1.30 2.20 6.30 14.0 29.0
IDD(ICRAM) 0.3 0.6 1.9 4.1 8.4 1.10 1.90 5.60 13.0 26.0
IDD(DC1RAM) 0.1 0.3 0.9 2.1 4.3 0.47 0.86 2.80 6.30 13.0
IDD(DC2RAM) 0.1 0.3 0.9 2.1 4.2 0.47 0.86 2.80 6.30 13.0
DS13543 Rev 2
µA
DMA2DRAMPDS = 0)
FMAC, FDCAN and USB peripherals SRAM
IDD(PRAM) static consumption 0.05 0.09 0.26 0.67 1.15 0.18 0.27 0.78 2.00 3.5
IDD(PKARAM) 0.03 0.07 0.24 0.60 1.05 0.11 0.23 0.72 1.80 3.2
STM32U5Axxx
STM32U5Axxx
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 5.55 18.5 60.5 130 270 20 56 190 390 800

RTC disabled,
3 5.7 17 62 135 280 21 51 190 400 830
retained 3.3 7.15 19 63.5 135 285 26 57 190 400 840
3.6 7.55 19.5 66 140 290 27 57 200 420 860
IDD(Stop 3)
1.8 27.5 82 300 680 1500 99 250 900 2100 4500
2.4 29 79.5 300 685 1500 110 240 900 2100 4500
RTC disabled, 3 28.5 81 300 685 1500 110 250 900 2100 4500
all SRAMs retained
3.3 28.5 83 300 690 1500 110 250 900 2100 4500
DS13543 Rev 2
3.6 27 84.5 305 695 1550 96 260 920 2100 4700

µA
1.8 5.75 18.5 61 130 270 21 56 190 390 800
3 6.25 17.5 62.5 135 280 23 52 210 400 830
retained 3.3 7.7 19.5 64 135 285 28 58 190 400 840
IDD(Stop 3 3.6 8.15 20.5 66.5 140 290 29 60 200 420 860
with RTC) 1.8 5.55 18.5 60.5 130 270 20 56 180 390 800
3 5.95 17 62 135 280 22 51 210 400 830
retained 3.3 7.35 19 63.5 135 285 26 57 190 400 840
3.6 7.3 20 66 140 290 26 59 200 420 860
221/390
222/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 5.7 18 60 130 265 21 54 180 390 790

2.4 6.4 17.5 60.5 130 270 23 53 190 390 800
bypassed at 32768 Hz, 3 6.05 17.5 61.5 130 275 22 52 200 390 820
8-Kbyte SRAM2 + ICACHE 3.3 7.45 19 63 135 280 27 57 190 400 830
retained
IDD(Stop 3 3.6 8.1 20 66 140 285 29 59 200 420 840
µA
with RTC) 1.8 7.15 18.5 60.5 130 265 - - - - -
2.4 6.95 17 60.5 130 265 - - - - -
in low-drive mode, 3 7.1 17 62 130 270 - - - - -
8-Kbyte SRAM2 + ICACHE 3.3 8.35 19 63.5 135 275 - - - - -
DS13543 Rev 2
retained
3.6 9.05 20 66 140 285 - - - - -
STM32U5Axxx
Table 59. SRAM static power consumption in Stop 3 when supplied by LDO
STM32U5Axxx
Typ Max(1)
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD(SRAM1_64kB)(2) 0.9 1.4 6.0 14.0 30.5 3.40 4.20 18.0 42.0 92.0
IDD(SRAM2_8kB)(3) 0.1 0.3 1.1 3.1 5.3 0.47 0.86 3.30 9.2 16.0
IDD(SRAM2_56kB)(3) 1.1 1.8 7.5 17.0 36.5 4.00 5.40 23.0 51.0 110
IDD(SRAM3_64kB)(4) 1.0 1.5 6.3 14.5 31.0 3.50 4.40 19.0 44.0 93.0
IDD(SRAM4) 0.2 0.4 1.7 3.6 7.1 0.55 1.20 5.00 11.0 22.0
DS13543 Rev 2
SRAM5 64 KB page x static consumption µA

IDD(SRAM5_64kB)(5) 1.0 1.4 6.1 14.0 30.0 3.50 4.20 19.0 42.0 90.0
IDD(ICRAM) 0.7 1.1 4.4 9.9 20.5 2.60 3.20 14.0 30.0 62.0
IDD(DC1RAM) 0.3 0.5 2.2 5.0 10.0 0.94 1.60 6.60 15.0 30.0
IDD(DC2RAM) 0.3 0.5 2.2 4.9 10.0 0.94 1.50 6.60 15.0 30.0
DMA2DRAMPDS = 0)
223/390
Table 59. SRAM static power consumption in Stop 3 when supplied by LDO (continued)
224/390
Typ Max(1)
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
FMAC, FDCAN and USB peripherals SRAM static

IDD(PRAM) consumption 0.09 0.13 0.59 1.35 2.70 0.33 0.39 1.80 4.1 8.1
static consumption µA
IDD(GPRAM) 0.09 0.14 0.72 1.65 3.20 0.33 0.41 2.20 5.0 9.6
IDD(PKARAM) 0.07 0.14 0.62 1.55 2.75 0.26 0.41 1.90 4.7 8.3
DS13543 Rev 2

STM32U5Axxx
STM32U5Axxx
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 2.75 8.5 29.5 65 140 9.8 26 87 200 410

Supply current in Stop 3 mode, 2.4 2.15 6.7 23.5 52 110 7.6 20 69 160 320
RTC disabled,
3 2 6.05 21 47 100 7 18 61 140 290
retained 3.3 2.2 6.25 21 46 100 7.5 18 60 140 290
3.6 2.95 7.35 22.5 47.5 100 9.7 21 64 140 290
IDD(Stop 3)
1.8 13 38.5 140 305 730 47 120 420 920 2200
2.4 10 29.5 110 250 550 36 89 330 750 1700
RTC disabled, 3 8.45 24.5 91 210 465 30 73 280 630 1400
all SRAMs retained
3.3 8.2 23.5 85.5 195 435 29 70 260 580 1300
DS13543 Rev 2
3.6 8.55 23.5 82 185 410 30 69 250 550 1300

µA
1.8 3 8.8 30 65.5 140 11 26 89 200 410
Supply current in Stop 3 mode, 2.4 2.55 7.05 24 52.5 110 9.1 21 71 160 320
3 2.45 6.5 21.5 47.5 100 8.6 19 63 140 290
retained 3.3 2.7 6.75 21.5 46.5 100 9.3 20 62 140 290
IDD(Stop 3 3.6 3.5 7.9 23 48 100 12 22 65 140 290

with RTC) 1.8 2.85 8.6 29.5 65 140 11 26 87 200 410
Supply current in Stop 3 mode, 2.4 2.3 6.8 23.5 52 110 8.2 20 69 160 320
3 2.1 6.15 21.5 47 100 7.3 18 63 140 290
retained 3.3 2.35 6.4 21.5 46.5 100 8 19 62 140 290
3.6 3.1 7.5 22.5 47.5 100 11 21 64 140 290
225/390
226/390
VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 2.95 8.75 29.5 65 140 11 26 87 200 410

2.4 2.45 7 23.5 52 110 8.7 21 69 160 320
bypassed at 32768 Hz, 3 2.35 6.4 21.5 47 100 8.2 19 63 140 290
8-Kbyte SRAM2 + ICACHE 3.3 2.6 6.6 21.5 46.5 99 8.9 19 62 140 290
retained
IDD(Stop 3 3.6 3.45 7.75 22.5 48 100 12 22 64 140 290
µA
with RTC) 1.8 3.4 8.8 30 65 135 - - - - -
2.4 2.8 7 24 52 110 - - - - -
in low-drive mode, 3 2.6 6.4 21.5 46.5 99.5 - - - - -
8-Kbyte SRAM2 + ICACHE 3.3 2.85 6.65 21.5 46 97.5 - - - - -
DS13543 Rev 2
retained
3.6 3.65 7.75 23 47.5 98.5 - - - - -
Table 61. SRAM static power consumption in Stop 3 when supplied by SMPS
Parameter Typ Max(1)
Symbol Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD(SRAM1_64kB)(2) 0.2 0.5 1.7 4.0 9.1 0.56 1.40 5.10 12.0 28.0
IDD(SRAM2_8kB)(3) 0.0 0.1 0.4 0.7 1.8 0.12 0.30 1.20 2.30 5.4
µA
STM32U5Axxx
IDD(SRAM2_56kB) (2)
0.2 0.6 2.2 4.9 11.0 0.69 1.80 6.60 15.0 33.0
IDD(SRAM3_64kB)(4) 0.2 0.5 1.8 4.1 9.4 0.60 1.50 5.40 13.0 29.0
Table 61. SRAM static power consumption in Stop 3 when supplied by SMPS (continued)
STM32U5Axxx
Parameter Typ Max(1)
Symbol Unit
25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C

IDD(SRAM4) 0.0 0.1 0.5 1.0 2.5 0.15 0.38 1.50 3.00 7.4
IDD(SRAM5_64kB)(5) 0.2 0.5 1.8 3.9 9.2 0.58 1.40 5.30 12.0 28.0
IDD(ICRAM) 0.1 0.3 1.3 2.8 6.5 0.42 1.10 3.80 8.40 20.0
IDD(DC1RAM) 0.1 0.2 0.6 1.4 3.4 0.21 0.51 2.00 4.20 11.0
IDD(DC2RAM) 0.1 0.2 0.6 1.4 3.5 0.22 0.51 2.00 4.10 11.0
DS13543 Rev 2
µA
DMA2DRAMPDS = 0)
FMAC, FDCAN and USB peripherals SRAM static
IDD(PRAM) consumption 0.02 0.05 0.20 0.40 1.30 0.07 0.14 0.59 1.20 3.9
IDD(PKARAM) 0.02 0.05 0.21 0.39 1.25 0.06 0.15 0.63 1.20 3.8
227/390
Table 62. Current consumption in Standby mode
228/390
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.195 0.765 3.45 8.9 23 0.52 1.9 8.3 22 54

2.4 0.22 0.815 3.65 9.4 24 0.61 2.0 8.8 23 56
No independent
watchdog 3 0.38 1.2 4.85 12 29.5 1.10 3.0 12 29 69
ULPMEN = 1
3.3 0.735 1.85 6.2 14 33.5 2.20 4.6 16 34 80
3.6 1.65 3.4 8.85 18 40 5.10 8.5 22 44 96
1.8 0.255 0.84 3.5 8.9 22.5 0.59 2.0 8.4 22 53
2.4 0.285 0.89 3.7 9.35 23.5 0.68 2.1 8.9 23 56
No independent
3 0.445 1.3 4.85 12 29 1.20 3.2 12 29 70
watchdog
3.3 0.795 1.95 6.2 14 33 2.30 4.7 16 34 79
DS13543 Rev 2
Supply current in
Standby mode (backup 3.6 1.7 3.5 8.85 18 39 5.10 8.6 22 44 94
IDD(Standby) µA
registers retained), 1.8 0.54 1.1 3.8 9.25 23 0.76 2.2 8.7 22 53
RTC disabled
2.4 0.69 1.25 4.1 9.8 24 0.95 2.4 9.3 23 56
With independent
watchdog clocked 3 0.955 1.75 5.35 12.5 29 1.60 3.5 13 29 69
by LSI 32 kHz
3.3 1.4 2.45 6.75 14.5 33.5 2.70 5.2 16 35 80
3.6 2.4 4.05 9.45 18.5 39.5 5.60 9.1 23 45 95
1.8 0.355 0.94 3.65 9 23 0.70 2.2 8.5 22 53
2.4 0.39 1 3.85 9.45 23.5 0.80 2.3 9.0 23 56
With independent
watchdog clocked 3 0.565 1.4 5 12 29 1.30 3.3 12 29 69
by LSI 250 Hz
3.3 0.92 2.05 6.35 14 33 2.40 4.9 16 34 80
3.6 1.85 3.6 9 18 39 5.20 8.8 22 44 95
STM32U5Axxx
Table 62. Current consumption in Standby mode (continued)
STM32U5Axxx
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.54 1.1 3.8 9.25 23 0.76 2.2 8.7 22 53

RTC(2) clocked by 2.4 0.65 1.25 4.1 9.7 24 0.95 2.4 9.2 23 56
LSI 32 kHz,
3 0.9 1.75 5.3 12 29 1.60 3.5 12 29 69
no independent
watchdog(3) 3.3 1.3 2.45 6.75 14.5 33.5 2.70 5.2 16 35 80
3.6 2.3 4.05 9.45 18.5 39.5 5.60 9.1 23 45 95
1.8 0.355 0.94 3.65 9.05 23 0.70 2.2 8.5 22 53
(2)
RTC clocked by 2.4 0.395 1 3.85 9.45 23.5 0.80 2.3 9.0 23 56
LSI 250 Hz,
3 0.565 1.4 5 12 29 1.30 3.3 12 29 69
no independent
watchdog 3.3 0.93 2.05 6.35 14 33 2.40 4.9 16 34 80
DS13543 Rev 2
Supply current in
IDD(Standby Standby mode (backup 3.6 1.85 3.65 9.05 18 39 5.30 8.8 22 44 95
µA
with RTC) registers retained), 1.8 0.48 1.05 3.75 9.1 22.5 0.87 2.3 8.8 22 54
RTC enabled
2.4 0.555 1.15 4 9.6 23.5 1.10 2.6 9.3 23 56
RTC(2) clocked by
LSE bypassed at 3 0.785 1.6 5.2 12 29 1.70 3.7 12 29 69
32768 Hz
3.3 1.2 2.3 6.55 14.5 33 2.80 5.3 16 35 80
3.6 2.2 3.9 9.25 18.5 39 5.70 9.2 23 45 95
1.8 0.65 1.2 3.9 9.25 22.5 - - - - -
2.4 0.69 1.3 4.1 9.7 23.5 - - - - -
RTC(2) clocked by
LSE quartz in 3 0.885 1.7 5.3 12 28.5 - - - - -
low-drive mode
3.3 1.25 2.35 6.65 14.5 32.5 - - - - -
3.6 2.25 3.9 9.3 18.5 38.5 - - - - -
229/390
230/390
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.14 0.26 0.5 0.95 2 0.5 0.8 1.5 2.9 6.0
Supply current to be 2.4 0.135 0.26 0.5 0.65 2 0.5 0.8 1.5 2.0 6.0
added in Standby mode
IDD(BKPSRAM) - 3 0.13 0.25 0.5 0.5 1.5 0.5 0.8 1.5 1.5 4.5
when backup SRAM is
retained 3.3 0.135 0.2 0.5 1 2 0.5 0.6 1.5 3.0 6.0
3.6 0.15 0.25 0.5 1 2 0.6 0.8 1.5 3.0 6.0
1.8 1.695 5.36 15.5 32.1 65.5 6.2 17 47 97 200
Supply current to be 2.4 1.715 5.41 15.3 32.15 65 6.2 17 46 97 200
IDD(SRAM2) 3 1.755 5.45 15.65 32 65.5 6.4 17 47 96 200 µA
when full SRAM2 is
retained 3.3 1.755 6.25 15.3 32.5 66 6.4 19 46 98 200
DS13543 Rev 2
3.6 1.85 5.95 15.65 32.5 66 6.7 18 47 98 200

LDO
1.8 0.645 2.71 7.5 15.6 31.5 2.4 8.2 23 47 95
Supply current to be 2.4 0.665 2.66 7.3 15.65 31.5 2.4 8.0 22 47 95
IDD added in Standby mode
3 0.705 2.65 7.65 15.5 31.5 2.6 8.0 23 47 95
(SRAM2_8K) when SRAM2 8KB
page 1 is retained 3.3 0.705 2.3 7.8 15.5 32 2.6 6.9 24 47 96
3.6 0.75 3 7.65 15.5 31.5 2.8 9.0 23 47 95
STM32U5Axxx
STM32U5Axxx
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.945 2.66 8 16.6 34 3.5 8.0 24 50 110

Supply current to be 2.4 0.715 2.16 6.3 13.65 27.5 2.6 6.5 19 41 83
IDD(SRAM2) 3 0.705 1.85 5.65 11.5 24 2.6 5.6 17 35 72
when full SRAM2 is
retained 3.3 0.655 1.6 4.8 10.5 22 2.4 4.8 15 32 66
3.6 0.55 1.35 4.15 9.5 20 2.0 4.1 13 29 60
SMPS µA
1.8 0.39 1.31 3.8 8.1 16.5 1.5 4.0 12 25 50
Supply current to be 2.4 0.315 1.06 3.1 6.65 13 1.2 3.2 9.3 20 39
IDD added in Standby mode
3 0.205 0.9 2.65 5 11 0.7 2.7 8.0 15 33
(SRAM2_8K) when SRAM2 8KB
page 1 is retained 3.3 0.255 0.75 2.35 5 10 0.9 2.3 7.1 15 30
DS13543 Rev 2
3.6 0.25 0.55 1.65 4 9 0.9 1.7 5.0 12 27

3. Current consumption with IWDG enabled is similar.
231/390
Table 63. Current consumption in Shutdown mode
232/390
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.15 0.73 3.20 8.10 20.0 0.47 1.9 8.0 21 50

Supply current in
2.4 0.18 0.78 3.40 8.55 21.0 0.56 2.0 8.5 22 53
Shutdown mode
IDD(Shutdown) (backup registers - 3 0.34 1.20 4.55 11.00 26.0 1.10 3.0 12.0 28 65
retained),
3.3 0.68 1.80 5.90 13.00 30.5 2.20 4.5 15.0 33 77
RTC disabled
3.6 1.60 3.35 8.55 17.00 36.5 5.00 8.4 22.0 43 92
1.8 0.37 0.95 3.45 8.30 20.0 0.86 2.1 8.3 21 50
2.4 0.45 1.05 3.65 8.80 21.0 1.10 2.3 8.8 22 53
RTC(2) clocked by
LSE bypassed at 3 0.67 1.50 4.85 11.00 26.0 1.60 3.4 12.0 28 65 µA
32768 Hz
Supply current in 3.3 1.10 2.15 6.20 13.50 30.0 2.70 4.9 16.0 34 76
DS13543 Rev 2
Shutdown mode 3.6 2.05 3.75 8.90 17.50 36.5 5.00 8.9 22.0 44 92
IDD(Shutdown (backup registers
with RTC) retained), 1.8 0.55 1.10 3.60 8.45 20.0 - - - - -
RTC enabled 2.4 0.59 1.15 3.80 8.90 21.0 - - - - -
RTC(2) clocked by
LSE quartz in 3 0.78 1.60 4.95 11.50 26.0 - - - - -
low-drive mode
3.3 1.15 2.20 6.30 13.50 30.0 - - - - -
3.6 2.15 3.80 8.95 17.50 36.0 - - - - -
STM32U5Axxx
Table 64. Current consumption in VBAT mode
STM32U5Axxx
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.08 0.23 0.93 2.30 5.65 0.24 0.68 2.6 5.8 15
Supply current in 2.4 0.08 0.24 0.97 2.35 5.80 0.24 0.70 2.6 5.9 15
VBAT mode (backup
IDD(VBAT) - 3 0.12 0.33 1.25 2.90 6.90 0.36 0.83 3.2 7.3 18
registers retained),
RTC disabled 3.3 0.20 0.51 1.80 4.25 10 0.61 1.30 4.5 11 25
3.6 0.40 0.82 2.35 4.95 11 1.30 2.10 5.9 13 28
1.8 0.39 0.55 1.25 2.65 5.95 0.58 1.10 2.9 6.2 15
2.4 0.47 0.63 1.40 2.80 6.20 0.67 1.30 3.1 6.4 15
3 0.62 0.82 1.75 3.45 7.40 0.91 1.40 3.7 7.9 18 µA
bypassed at 32768 Hz
3.3 0.78 1.05 2.35 4.80 10.50 1.30 1.90 5.2 12 26
DS13543 Rev 2
Supply current in
IDD(VBAT VBAT mode (backup 3.6 1.05 1.40 2.95 5.60 11.50 2.00 2.70 6.6 14 29
with RTC) registers retained), 1.8 0.30 0.46 1.20 2.55 5.85 0.49 1.10 2.8 6.1 15
RTC enabled
2.4 0.34 0.51 1.25 2.70 6.10 0.53 1.10 3.0 6.3 15
bypassed at 32768 Hz, 3 0.46 0.65 1.60 3.30 7.20 0.74 1.30 3.6 7.7 18
RTC_CALR.LPCAL = 1
3.3 0.60 0.87 2.20 4.65 10.5 1.10 1.70 5.0 12 26
3.6 0.87 1.20 2.75 5.40 11.5 1.80 2.50 6.4 13 29
233/390
Table 64. Current consumption in VBAT mode (continued)
234/390
- VDD (V) 25°C 55°C 85°C 105°C 125°C 30°C 55°C 85°C 105°C 125°C
1.8 0.53 0.69 1.40 2.75 6.00 - - - - -

2.4 0.58 0.74 1.50 2.90 6.20 - - - - -
3 0.68 0.89 1.85 3.50 7.35 - - - - -
quartz in low-drive mode
3.3 0.79 1.10 2.45 4.85 10.5 - - - - -
Supply current in
IDD(VBAT VBAT mode (backup 3.6 1.05 1.45 3.00 5.60 11.5 - - - - -
with RTC) registers retained), 1.8 0.44 0.61 1.35 2.70 5.95 - - - - -
RTC enabled
2.4 0.46 0.63 1.40 2.80 6.10 - - - - -
quartz in low-drive mode, 3 0.52 0.74 1.65 3.35 7.20 - - - - - µA
RTC_CALR.LPCAL =1
3.3 0.62 0.93 2.25 4.70 10.5 - - - - -
DS13543 Rev 2
3.6 0.86 1.25 2.80 5.45 11.5 - - - - -

1.8 0.14 0.22 0.48 0.90 1.90 0.29 0.49 1.3 2.6 5.6
Supply current to 2.4 0.14 0.22 0.48 0.95 1.90 0.30 0.49 1.3 2.7 5.6
IDD add in VBAT mode
- 3 0.14 0.21 0.45 0.95 1.85 0.31 0.48 1.2 2.7 5.4
(BKPSRAM) when the backup
SRAM is retained 3.3 0.14 0.21 0.50 0.95 2.00 0.31 0.48 1.4 2.7 5.9
3.6 0.15 0.24 0.45 0.95 2.00 0.33 0.56 1.2 2.7 5.9
2. RTC with default configuration except otherwise specified.
STM32U5Axxx
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down generate current consumption when the
pin is externally held to the opposite level. The value of this current consumption can be
simply computed by using the pull-up/pull-down resistors values given in Section 5.3.15: I/O
port characteristics.
For the output pins, any internal or external pull-up or pull-down or external load must also
be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of the ADC input pins, that must be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the on-chip peripheral current consumption (see Table 65), the I/Os used by
an application also contribute to the current consumption. When an I/O pin switches, it uses
the current from the I/O supply voltage to supply the I/O pin circuitry and to
charge/discharge the capacitive load (internal and external) connected to the pin:
I SW = V DDIOx × f SW × C
where:
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load.
• VDDIOx is the I/O supply voltage.
• fSW is the I/O switching frequency.
• C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS.
• CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the table below. The MCU is
placed under the following conditions:
• All I/O pins are in analog mode.
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
DS13543 Rev 2 235/390

352
• The ambient operating temperature and supply voltage conditions are summarized
in Table 33: General operating conditions.
• The power consumption of the digital part of the on-chip peripherals is given in the table
below. The power consumption of the analog part of the peripherals (where applicable)
is indicated in each related section of the datasheet.
Table 65. Typical dynamic current consumption of peripherals

LDO SMPS
Bus Peripheral Unit
Range Range Range Range Stop Range Range Range Range Stop
1 2 3 4 1/2 1 2 3 4 1/2
AHB1 0.48 0.39 0.35 0.32 - 0.21 0.18 0.15 0.11 -

BKPSRAM 1.24 1.06 0.96 0.85 - 0.57 0.47 0.39 0.31 -
CORDIC 0.67 0.60 0.54 0.48 - 0.32 0.26 0.22 0.18 -
CRC 1.02 0.88 0.80 0.70 - 0.47 0.40 0.33 0.25 -
DCACHE1 0.39 0.28 0.26 0.21 - 0.15 0.12 0.10 0.08 -
DCACHE2 1.10 0.93 0.83 0.74 - 0.50 0.41 0.34 0.27 -
DMA2D 2.51 2.23 2.02 1.79 - 1.20 1.00 0.84 0.66 -
FLASH 2.08 1.86 1.68 1.49 - 1.00 0.83 0.70 0.55 -
FMAC 2.36 2.09 1.90 1.69 - 1.17 0.94 0.78 0.63 -
AHB1
GFXMMU 3.73 3.32 3.00 2.67 - 1.80 1.48 1.24 0.99 -

GPDMA1 3.16 2.87 2.58 2.32 - 1.55 1.29 1.08 0.84 -
GPU 11.83 10.68 9.68 8.61 - 5.79 4.81 4.02 3.18 -
GTZC1 0.96 0.81 0.73 0.64 - 0.47 0.35 0.30 0.23 -
µA/MHz
ICACHE 0.94 0.79 0.72 0.63 - 0.42 0.35 0.29 0.23 -
MDF1 8.05 7.29 6.62 5.89 - 3.99 3.28 2.75 2.19 -
(1)
MDF1 indep 0.92 0.87 0.79 0.69 - 0.47 0.39 0.33 0.26 -
RAMCFG 2.26 2.00 1.81 1.60 - 1.07 0.90 0.75 0.59 -
SRAM1 1.20 1.02 0.92 0.80 - 0.55 0.45 0.38 0.29 -
TSC 1.37 1.20 1.08 0.95 - 0.64 0.54 0.45 0.35 -
AHB2_1 1.02 0.78 0.71 0.62 - 0.42 0.34 0.29 0.24 -
ADC12 4.53 4.13 3.71 3.38 - 2.22 1.85 1.56 1.22 -
ADC12 indep(1) 0.85 0.81 0.73 0.66 - 0.44 0.36 0.30 0.25 -
AES 2.95 2.67 2.39 2.20 - 1.44 1.20 1.00 0.77 -
AHB2-1
DCMI 5.10 4.66 4.20 3.82 - 2.55 2.09 1.76 1.38 -

GPIOA 0.07 0.07 0.06 0.05 - 0.03 0.03 0.03 0.02 -
GPIOB 0.08 0.07 0.05 0.04 - 0.04 0.03 0.03 0.02 -
GPIOC 0.11 0.09 0.07 0.06 - 0.05 0.05 0.04 0.02 -
GPIOD 0.25 0.22 0.18 0.15 - 0.12 0.10 0.09 0.06 -
236/390 DS13543 Rev 2

Table 65. Typical dynamic current consumption of peripherals (continued)

LDO SMPS
Bus Peripheral Unit
1 2 3 4 1/2 1 2 3 4 1/2
GPIOE 0.14 0.12 0.09 0.09 - 0.06 0.05 0.05 0.03 -

GPIOF 0.14 0.13 0.09 0.08 - 0.06 0.05 0.05 0.03 -
GPIOG 0.20 0.18 0.15 0.13 - 0.10 0.08 0.07 0.04 -
GPIOH 0.27 0.24 0.20 0.18 - 0.13 0.11 0.09 0.06 -
GPIOI 0.30 0.26 0.22 0.20 - 0.14 0.12 0.10 0.07 -
GPIOJ 0.28 0.25 0.19 0.17 - 0.13 0.10 0.09 0.06 -
HASH1 2.00 1.82 1.61 1.48 - 0.97 0.81 0.68 0.52 -
OCTOSPIM 0.54 0.49 0.41 0.36 - 0.27 0.21 0.18 0.13 -
OTFDEC1 2.09 1.89 1.68 1.55 - 1.06 0.85 0.70 0.53 -
OTFDEC2 2.05 1.85 1.64 1.53 - 1.04 0.83 0.69 0.52 -
OTG_HS 27.98 25.52 23.12 20.71 - 13.76 11.49 9.68 9.56 -
AHB2-1
PKA 7.04 6.44 5.80 5.22 - 3.46 2.88 2.42 1.91 -

RNG 1.43 1.28 1.13 1.05 - 0.68 0.56 0.48 0.36 -
RNG indep(1) 0.07 0.07 0.07 0.06 - 0.05 0.05 0.03 0.02 -
SAES 3.38 3.07 2.75 2.50 - 1.65 1.37 1.15 0.89 -
SDMMC1 13.80 12.58 11.37 10.22 - 6.80 5.66 4.74 3.74 -
µA/MHz
SDMMC1
1.67 1.53 1.38 1.30 - 0.82 0.69 0.58 0.52 -
indep(1)
SDMMC2 12.82 11.68 10.56 9.50 - 6.31 5.26 4.41 3.48 -
SDMMC2
1.63 1.49 1.36 1.26 - 0.81 0.67 0.57 0.51 -
indep(1)
SRAM2 1.22 1.10 0.97 0.94 - 0.59 0.49 0.42 0.30 -
SRAM3 2.31 2.10 1.86 1.74 - 1.13 0.93 0.79 0.60 -
AHB2_2 0.18 0.12 0.10 0.09 - 0.10 0.05 0.04 0.02 -
FMC 6.71 6.13 5.52 5.00 - 3.30 2.74 2.30 1.82 -
HSPI1 3.36 3.05 2.72 2.51 - 1.65 1.36 1.14 0.88 -
(1)
HSPI1 indep 2.37 2.12 1.91 1.71 - 1.15 0.95 0.80 0.62 -
OCTOSPI1 1.44 1.30 1.15 1.07 - 0.70 0.58 0.48 0.36 -
AHB2-2
OCTOSPI1
1.10 1.00 0.90 0.81 - 0.54 0.45 0.38 0.29 -
indep(1)
OCTOSPI2 1.47 1.33 1.17 1.12 - 0.72 0.59 0.49 0.37 -
OCTOSPI2
1.28 1.16 1.05 0.94 - 0.63 0.53 0.44 0.34 -
indep(1)
SRAM5 2.16 1.96 1.74 1.62 - 1.06 0.87 0.73 0.56 -
DS13543 Rev 2 237/390

352

LDO SMPS
Bus Peripheral Unit
1 2 3 4 1/2 1 2 3 4 1/2
AHB3 0.16 0.13 0.11 0.10 - 0.07 0.05 0.05 0.04 -

ADC4 1.42 1.31 1.18 1.05 1.17 0.67 0.58 0.49 0.38 0.43
(1)
ADC4 indep 1.78 1.66 1.50 1.33 1.34 0.90 0.75 0.62 0.49 0.49
ADF1 1.08 1.00 0.90 0.79 0.91 0.49 0.44 0.37 0.28 0.33
ADF1 indep(1) 0.55 0.50 0.45 0.41 0.40 0.31 0.23 0.19 0.15 0.15
DAC1 1.63 1.51 1.35 1.20 1.33 0.77 0.66 0.56 0.44 0.49
AHB3
DAC1 indep(1) 1.00 0.92 0.83 0.75 0.75 0.50 0.42 0.35 0.27 0.27
GTZC2 1.31 1.20 1.09 0.96 - 0.60 0.53 0.45 0.34 -
LPDMA1 0.40 0.38 0.34 0.29 0.41 0.16 0.16 0.14 0.11 0.15
LPGPIO1 0.09 0.08 0.07 0.06 0.18 0.04 0.03 0.03 0.02 0.06
PWR 0.18 0.17 0.15 0.13 - 0.09 0.07 0.06 0.05 -
SRAM4 1.00 0.92 0.84 0.74 - 0.49 0.40 0.35 0.26 -
APB1 1.16 0.90 0.79 0.76 - 0.48 0.38 0.33 0.24 -
CRS 0.36 0.34 0.31 0.30 - 0.22 0.15 0.13 0.11 -
FDCAN1 4.88 4.46 4.06 3.64 - 2.41 2.01 1.69 1.36 -
FDCAN1
µA/MHz
2.33 2.21 2.12 1.89 - 1.28 1.07 0.88 0.71 -
indep(1)
I2C1 0.87 0.81 0.74 0.67 - 0.43 0.36 0.30 0.25 -
(1)
I2C1 indep 2.10 1.91 1.73 1.55 - 1.03 0.86 0.72 0.56 -
I2C2 3.04 2.78 2.53 2.28 - 1.50 1.24 1.05 0.85 -
(1)
I2C2 indep 2.13 1.98 1.80 1.61 - 1.12 0.89 0.75 0.59 -
I2C4 0.92 0.85 0.77 0.71 - 0.46 0.38 0.32 0.26 -
APB1
(1)
I2C4 indep 2.21 2.02 1.83 1.64 - 1.09 0.91 0.76 0.60 -
I2C5 3.15 2.88 2.61 2.33 - 1.56 1.29 1.09 0.88 -
I2C5 indep(1) 2.31 2.12 1.92 1.72 - 1.14 0.95 0.80 0.63 -
I2C6 3.02 2.77 2.50 2.23 - 1.53 1.23 1.04 0.84 -
I2C6 indep(1) 2.19 2.00 1.81 1.61 - 1.08 0.90 0.75 0.59 -
LPTIM2 1.36 1.23 1.12 1.02 - 0.66 0.55 0.46 0.38 -
LPTIM2
4.01 3.66 3.32 2.97 - 1.98 1.64 1.38 1.10 -
Indep(1)
LTDC 10.29 9.38 8.49 7.59 - 5.07 4.22 3.54 2.80 -
SPI2 1.89 1.71 1.54 1.42 - 0.91 0.76 0.64 0.53 -
SPI2 indep(1) 0.71 0.64 0.58 0.51 - 0.35 0.29 0.24 0.19 -
238/390 DS13543 Rev 2


LDO SMPS
Bus Peripheral Unit
1 2 3 4 1/2 1 2 3 4 1/2
TIM2 4.75 4.30 3.91 3.50 - 2.33 1.93 1.63 1.30 -

TIM3 4.74 4.30 3.91 3.50 - 2.32 1.93 1.62 1.30 -
TIM4 4.73 4.32 3.93 3.53 - 2.34 1.94 1.63 1.31 -
TIM5 4.82 4.41 4.01 3.60 - 2.38 1.98 1.66 1.34 -
TIM6 0.92 0.86 0.77 0.71 - 0.50 0.38 0.32 0.26 -
TIM7 0.92 0.86 0.77 0.71 - 0.45 0.39 0.32 0.26 -
UART4 2.04 1.89 1.71 1.57 - 1.05 0.84 0.71 0.58 -
(1)
UART4 indep 3.88 3.55 3.23 2.88 - 1.91 1.59 1.34 1.07 -
UART5 2.07 1.91 1.73 1.58 - 1.02 0.85 0.72 0.58 -
UART5 indep(1) 3.70 3.38 3.07 2.73 - 1.82 1.52 1.28 1.02 -
APB1
UCPD1 1.73 1.60 1.45 1.31 - 0.86 0.71 0.60 0.49 -

USART2 7.03 6.44 5.84 5.26 - 3.47 2.90 2.43 1.95 -
USART2
4.97 4.55 4.14 3.69 - 2.45 2.05 1.72 1.38 -
indep(1)
USART3 2.34 2.16 1.95 1.79 - 1.15 0.96 0.81 0.66 -
USART3
4.64 4.24 3.86 3.43 - 2.29 1.91 1.61 1.29 -
indep(1)
µA/MHz
USART6 6.61 6.03 5.48 4.89 - 3.25 2.71 2.29 1.82 -
USART6
4.49 4.11 3.73 3.32 - 2.21 1.85 1.55 1.24 -
indep(1)
WWDG 0.47 0.45 0.39 0.34 - 0.23 0.19 0.17 0.14 -
APB2 0.83 0.59 0.51 0.47 - 0.31 0.24 0.22 0.16 -
DSI 13.76 12.53 11.33 10.14 - 6.78 5.65 4.74 3.86 -
SAI1 1.68 1.51 1.36 1.22 - 0.81 0.68 0.56 0.45 -
(1)
SAI1 indep 1.30 1.18 1.08 0.95 - 0.64 0.53 0.45 0.34 -
SAI2 1.77 1.57 1.42 1.29 - 0.85 0.71 0.59 0.47 -
SAI2 indep(1) 1.40 1.29 1.17 1.00 - 0.69 0.58 0.49 0.38 -
APB2
SPI1 1.71 1.55 1.41 1.26 - 0.83 0.70 0.59 0.47 -

(1)
SPI1 indep 0.83 0.76 0.69 0.62 - 0.41 0.34 0.29 0.23 -
TIM1 7.25 6.61 6.00 5.34 - 3.56 2.97 2.50 1.99 -
TIM15 3.74 3.41 3.10 2.78 - 1.88 1.54 1.29 1.03 -
TIM16 2.61 2.38 2.17 1.94 - 1.29 1.07 0.90 0.72 -
TIM17 2.71 2.47 2.24 2.01 - 1.34 1.11 0.93 0.74 -
TIM8 7.26 6.63 5.99 5.38 - 3.57 3.00 2.50 1.98 -
DS13543 Rev 2 239/390

352

LDO SMPS
Bus Peripheral Unit
1 2 3 4 1/2 1 2 3 4 1/2
USART1 2.09 1.92 1.75 1.55 - 1.03 0.87 0.73 0.58 -

APB2
USART1
3.97 3.63 3.31 2.94 - 1.96 1.63 1.37 1.10 -
indep(1)
APB3 0.34 0.21 0.17 0.16 - 0.11 0.08 0.07 0.06 -
COMP 0.23 0.21 0.19 0.17 0.14 0.11 0.09 0.08 0.06 0.05
I2C3 0.64 0.59 0.52 0.47 0.48 0.32 0.26 0.22 0.17 0.17
(1)
I2C3 indep 1.73 1.59 1.42 1.27 1.28 0.90 0.71 0.60 0.45 0.47
LPTIM1 1.08 0.98 0.89 0.78 0.81 0.57 0.44 0.37 0.29 0.29
LPTIM1
3.03 2.74 2.47 2.20 2.24 1.48 1.21 1.03 0.81 0.82
indep(1)
LPTIM3 1.03 0.95 0.85 0.76 0.77 0.51 0.43 0.35 0.28 0.28
LPTIM3
µA/MHz
2.87 2.54 2.32 2.06 2.13 1.41 1.15 0.98 0.77 0.78
indep(1)
LPTIM4 0.65 0.60 0.54 0.48 0.49 0.33 0.27 0.22 0.18 0.18
APB3
LPTIM4
1.69 1.54 1.46 1.28 1.34 0.88 0.72 0.63 0.47 0.49
indep(1)
LPUART1 1.27 1.16 1.04 0.93 0.95 0.67 0.52 0.44 0.34 0.35
LPUART1
2.12 1.94 1.76 1.58 1.58 1.05 0.87 0.73 0.57 0.58
indep(1)
OPAMP 0.24 0.22 0.18 0.17 0.18 0.11 0.10 0.08 0.07 0.06
RTC 1.87 1.70 1.52 1.38 1.39 0.93 0.77 0.64 0.50 0.51
SPI3 1.13 1.01 0.90 0.80 0.81 0.54 0.45 0.37 0.30 0.30
(1)
SPI3 indep 0.48 0.44 0.40 0.35 0.35 0.23 0.20 0.16 0.12 0.13
SYSCFG 0.37 0.30 0.27 0.24 - 0.17 0.14 0.11 0.09 -
VREFBUF 0.14 0.12 0.11 0.10 0.11 0.07 0.06 0.05 0.04 0.04
1. Indep stands for independent clock domain.
5.3.7 Wake-up time from low-power modes and voltage scaling

transition times
The wake-up times given in the table below are the latency between the event and the
execution of the first user instruction (FSTEN = 1 in PWR_CR3 if not mentioned).
The device goes in low-power mode after the WFE (wait for event) instruction.
240/390 DS13543 Rev 2

Table 66. Low-power mode wake-up timings on LDO(1)

Typ (3V, Max
Mode Parameter Conditions Unit
25°C) (3V)
Nb of
Wake-up time from SLEEP_PD = 0 14 17 CPU
twu(Sleep) cycles
Sleep to Run mode
SLEEP_PD = 1 with MSI = 24 MHz 8.1 9
Wake-up in FLASH, range 4,
FLASHFWU = 1 and
MSI 24 MHz 2.6 3
SRAM4FWU = 1 in PWR_CR2
ICACHE OFF
Wake-up in FLASH, range 4, MSI 24 MHz 11.0 12
Wake-up time from
FLASHFWU = 0 and
twu(Stop 0) Stop 0 to Run mode HSI 16 MHz 10.7 12
All SRAMs retained ICACHE OFF MSI 1 MHz 38.1 40
MSI 24 MHz 5.0 6
Wake-up in SRAM2, range 4,
FLASHFWU = 0 and HSI 16 MHz 6.9 8
MSI 1 MHz 34.1 36
Wake-up in FLASH,
FLASHFWU = 1 and
MSI 24 MHz 13.4 17
ICACHE OFF
Wake-up in FLASH, MSI 24 MHz 21.9 25
Wake-up time from
FLASHFWU = 0 and
SRAM4FWU = 0 in PWR_CR2 µs
MSI 24 MHz 15.8 19
MSI 1 MHz 44.9 49
Wake-up in FLASH,
SRAM4FWU = 1 in PWR_CR2 MSI 24 MHz 20.3 24
ICACHE OFF
MSI 24 MHz 22.9 26
Wake-up in FLASH,
Wake-up time from
SRAM4FWU = 0 in PWR_CR2 HSI 16 MHz 22.7 27
twu(Stop 2) Stop 2 to Run mode
ICACHE OFF
All SRAMs retained MSI 1 MHz 58.0 63
MSI 24 MHz 16.9 20
HSI 16 MHz 19.0 23
MSI 1 MHz 54.0 59
Wake-up time from Wake-up in FLASH,
twu(Stop 3) Stop 3 to Run mode FSTEN = 0 in PWR_CR3 MSI 24 MHz 55.3 132
All SRAMs retained ICACHE OFF
DS13543 Rev 2 241/390

352
Table 66. Low-power mode wake-up timings on LDO(1) (continued)

Typ (3V, Max
25°C) (3V)
MSI 24 MHz 28.9 38

Wake-up in FLASH,
FSTEN = 1 in PWR_CR3 HSI 16 MHz 28.7 37
Wake-up time from ICACHE OFF
MSI 1 MHz 63.0 98
Wake-up in SRAM2, range 4 HSI 16 MHz 22.3 32
MSI 1 MHz 58.3 91
Wake-up in FLASH,
MSI 4 MHz 60.5 90
Wake-up time from FSTEN = 0 in PWR_CR3
twu(Standby
Standby with SRAM2 µs
with SRAM2) Wake-up in FLASH, MSI 4 MHz 59.7 89
to Run mode
FSTEN = 1 in PWR_CR3 MSI 1 MHz 168.1 248
Wake-up in FLASH,
MSI 4 MHz 327.3 416
FSTEN = 0 in PWR_CR3
Wake-up time from
twu(Standby)
Standby to Run mode Wake-up in FLASH, MSI 4 MHz 95.5 127
Wake-up time from
twu(Shutdown) Shutdown to Run - MSI 4 MHz 683.3 718
mode
Table 67. Low-power mode wake-up timings on SMPS(1)

Typ (3 V, Max
25 °C) (3 V)
Nb of
Wake-up time from SLEEP_PD = 0 14 17 CPU
twu(Sleep) cycles
Sleep to Run mode
SLEEP_PD = 1 with MSI = 24 MHz 8.0 9
Wake-up in FLASH, range 4,
FLASHFWU = 1 and
MSI 24 MHz 2.6 3
ICACHE OFF
Wake-up in FLASH, range 4, MSI 24 MHz 11.0 12
Wake-up time from µs
FLASHFWU = 0 and
MSI 24 MHz 5.0 6
MSI 1 MHz 34.1 36
242/390 DS13543 Rev 2

Table 67. Low-power mode wake-up timings on SMPS(1) (continued)

Typ (3 V, Max
25 °C) (3 V)
Wake-up in FLASH,
FLASHFWU = 1 and
MSI 24 MHz 7.8 9
ICACHE OFF
Wake-up in FLASH MSI 24 MHz 16.2 18
Wake-up time from
FLASHFWU = 0 and
MSI 24 MHz 10.1 12
MSI 1 MHz 39.3 42
Wake-up in FLASH
SRAM4FWU = 1 in PWR_CR2 MSI 24 MHz 17.6 20
ICACHE OFF
MSI 24 MHz 20.2 22
Wake-up in FLASH
Wake-up time from
SRAM4FWU = 0 in PWR_CR2 HSI 16 MHz 20.0 22
ICACHE OFF
MSI 24 MHz 14.2 16
HSI 16 MHz 16.2 18
MSI 1 MHz 51.1 55
µs
Wake-up in FLASH,
ICACHE OFF
MSI 24 MHz 30.9 36
Wake-up in FLASH,
Wake-up time from
FSTEN = 1 in PWR_CR3 HSI 16 MHz 30.6 35
ICACHE OFF
MSI 24 MHz 25.0 31
Wake-up in SRAM2, range 4 HSI 16 MHz 26.8 32
MSI 1 MHz 62.8 94
Wake-up in FLASH,
MSI 4 MHz 57.3 88
Wake-up time from FSTEN = 0 in PWR_CR3
twu(Standby
Standby with SRAM2
with SRAM2) Wake-up in FLASH, MSI 4 MHz 57.9 87
to Run mode
Wake-up in FLASH,
MSI 4 MHz 329.2 417
FSTEN = 0 in PWR_CR3
Wake-up time from
twu(Standby)
Standby to Run mode Wake-up in FLASH, MSI 4 MHz 94.8 125
Wake-up time from
twu(Shutdown) - MSI 4 MHz 683.2 718
Shutdown to Run mode
DS13543 Rev 2 243/390

352
Table 68. Regulator mode transition times(1)

Typ (3 V, Max
Symbol Parameter Conditions Unit
25 °C) (3 V)
Range 4 15.6 19
Range 3 14.5 18
tLDO(2) SMPS to LDO transition time
Range 2 14 18
Range 1 13.9 17
Range 4 13.1 16
Range 3 16.5 19
tSMPS(2) LDO to SMPS transition time
Range 2 16.1 19
Range 1 15.9 19
µs
LDO 18 21
Range 4 to range 3
SMPS 24.3 28
LDO 12.2 15
Range 3 to range 2
SMPS 12.2 15
tVOST(3)
LDO 11.8 14
Range 2 to range 1
SMPS 11.8 14
LDO 40.9 43
Range 4 to range 1
SMPS 47 55
2. Time to REGS change in PWR_SVMSR.
3. Time to VOSRDY = 1 in PWR_VOSR.
Table 69. Wake-up time using USART/LPUART(1)

Symbol Parameter Typ Max Unit
Wake-up time needed to calculate the maximum USART/LPUART baudrate that

tWUUSART (2)
is needed to wake up from Stop mode when the USART/LPUART kernel clock - μs
tWULPUART
source is HSI16/MSI.
1. Specified by design. Not tested in production.
2. This wake-up time is the HSI16 (see Table 74) or the MSI (see Table 75) oscillator maximum startup time.
5.3.8 External clock timing characteristics

High-speed external user clock generated from an external source
In bypass mode, the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15: I/O port
characteristics. The recommended clock input waveform is shown in Figure 27.
244/390 DS13543 Rev 2

Table 70. High-speed external user clock characteristics(1)

Voltage scaling
- 4(2) - 50
User external clock range 1, 2, 3
fHSE_ext MHz
source frequency Voltage scaling
- 4(2) - 25
range 4
OSC_IN input pin
VHSEH - 0.7 × VDD - VDD
high-level voltage
V
OSC_IN input pin
VHSEL - VSS - 0.3 × VDD
low-level voltage
Digital mode
(HSEBYP = 1, Voltage scaling
7 - -
tw(HSEH) HSEEXT = 1) range 1, 2, 3
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
range 4
DuCyHSE OSC_IN duty cycle - 45 - 55 %
VHSE_ext_ OSC_IN peak-to-peak
- 0.2 - 2/3 VDD
PP amplitude V
Analog mode
VHSE_ext OSC_IN input range (HSEBYP = 1, - 0 - VDD
HSEEXT = 0)
tr(HSE), 0.05 / 0.3 /
OSC_IN rise and fall time - - ns
tf(HSE) fHSE_ext fHSE_ext
2. Only for Analog mode. No minimum value in digital mode.
Figure 27. AC timing diagram for high-speed external clock source (digital mode)
VHSE
tw(HSEH)
VHSEH
70%
30%
VHSEL
t
THSE tw(HSEL)
MSv67850V3
DS13543 Rev 2 245/390

352
Figure 28. AC timing diagram for high-speed external clock source (analog mode)
VHSE_ext
90%
VHSE_ext_PP
10%
tf(HSE) tr(HSE)
t
tHSE_ext = 1/fHSE_ext
MSv71538V1
Low-speed external user clock generated from an external source

In bypass mode, the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.15: I/O port
characteristics. The recommended clock input waveform is shown in Figure 29 and
Figure 30.
Table 71. Low-speed external user clock characteristics(1)

Symbol Parameter Min Typ Max Unit
fLSE_ext User external clock source frequency 5 32.768 40 kHz

VLSE_ext_PP OSC32_IN peak-to-peak amplitude 0.3 - VSW
V
VLSE_ext OSC32_IN input range 0 - VSW
tw(LSEH)
OSC32_IN high or low time for square signal input 10 - - μs
tw(LSEL)
Figure 29. AC timing diagram for low-speed external square clock source
VLSE_ext
tw(LSEH)
VLSEH
70%
VLSE_ext_PP
30%
VLSEL
t
tLSE = 1/fLSE_ext tw(LSEL)
MSv67851V3
246/390 DS13543 Rev 2

Figure 30. AC timing diagram for low-speed external sinusoidal clock source
VLSE_ext
VLSE_ext_PP
tLSE_ext = 1/fLSE_ext
MSv69160V1
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in the table below.
In the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins, in order to minimize the output distortion and startup
stabilization time. Refer to the crystal resonator manufacturer for more details on the
resonator characteristics (frequency, package, accuracy).
Table 72. HSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 - 50 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 8 mA
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 4 MHz - 790 -
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 8 MHz - 910 -
HSE current
IDD(HSE) VDD = 3 V, Rm = 45 Ω, CL = 10 pF @ 8 MHz - 930 -
consumption μA
VDD = 3 V, Rm = 30 Ω, CL = 5 pF @ 48 MHz - 1430 -
VDD = 3 V, Rm = 30 Ω, CL = 10 pF @ 48 MHz - 1960 -
VDD = 3 V, Rm = 30 Ω, CL = 20 pF @ 48 MHz - 3000 -
Maximum critical crystal
Gmcritmax Startup - - 1.5 mA/V
transconductance Gm
tsu(HSE)
(4) Startup time VDD stabilized - 2 - ms
DS13543 Rev 2 247/390

352
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).
Figure 31. Typical application with a 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in the table below. In the application,
the resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. Refer to
the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 73. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV[1:0] = 00, low-drive capability - 410 -
LSE current LSEDRV[1:0] = 01, medium low-drive capability - 450 -

IDD(LSE) nA
consumption LSEDRV[1:0] = 10, medium high-drive capability - 590 -
LSEDRV[1:0] = 11, high-drive capability - 700 -
LSEDRV[1:0] = 00, low-drive capability - - 0.5
Maximum critical LSEDRV[1:0] = 01, medium low-drive capability - - 0.75

Gmcritmax µA/V
crystal Gm LSEDRV[1:0] = 10, medium high-drive capability - - 1.7
LSEDRV[1:0] = 11, high-drive capability - - 2.7
248/390 DS13543 Rev 2

Table 73. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (continued)

Internal stray
CS_PARA parasitic - - 3 - pF
capacitance(3)
tSU(LSE)(4) Startup time VDD is stabilized - 2 - s
2. Refer to the note below this table.
3. CS_PARA is the equivalent capacitance seen by the crystal due to OSC32_IN and OSC32_OUT internal parasitic
capacitances.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note ‘Oscillator design guide
for STM8AF/AL/S, STM32 MCUs and MPUs’ (AN2867).
Figure 32. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors

CL1
OSC32_IN fLSE
32.768 kHz resonator Drive
CS programmable
amplifier
OSC32_OUT
CL2
Note: CL1 and CL2 are external load capacitances. Cs (stray capacitance) is the sum of the device OSC32_IN/OSC32_OUT pins
equivalent parasitic capacitance (CS_PARA), and the PCB parasitic capacitance. MSv70418V1
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
5.3.9 Internal clock timing characteristics

The parameters given in the table below are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 33. The provided curves
are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 74. HSI16 oscillator characteristics

fHSI16 VDD = 3.0 V, TJ = 30 °C 15.92 16 16.08

TJ = –10 °C to 100 °C,
HSI16 frequency after factory 15.84 - 16.16
1.58 ≤ VDD ≤ 3.6 V MHz
fHSI16(1) calibration
TJ = –40 °C to 130 °C,
15.65 - 16.25
1.58 ≤ VDD ≤ 3.6 V
TRIMHSI16(2) HSI16 user trimming step - 18 29 40 kHz
DS13543 Rev 2 249/390

352
Table 74. HSI16 oscillator characteristics (continued)

(2)
DuCyHSI16 Duty cycle - 45 - 55 %
tsu(HSI16)(2) HSI16 oscillator startup time - - 2.5 3.6
μs
tstab(HSI16)(2) HSI16 oscillator stabilization time At 1% of target frequency - 4 6
IDD(HSI16)(2) HSI16 oscillator power consumption - - 150 210 μA
1. Evaluated by characterization. Not tested in production. It does not take into account package and soldering effects.
250/390 DS13543 Rev 2

Multi-speed internal (MSI) RC oscillator
Table 75. MSI oscillator characteristics(1)

MSI range 0
47.74 48 48.70
(MSIRC0)
MSI range 1 23.87 24 24.35
MSI range 2 15.91 16 16.23
MSI range 3 11.93 12 12.17
MSI range 4
3.98 4 4.06
(MSIRC1)
MSI range 5 1.99 2 2.03 MHz
MSI range 6 1.33 1.33 1.35
MSI range 7 0.99 1 1.01
MSI mode
MSI range 8
3.05 3.08 3.12
(MSIRC2)
MSI range 9 1.53 1.54 1.56
MSI range 10 1.02 1.03 1.04
MSI range 11 0.76 0.77 0.78
MSI range 12
397.68 400 405.71
(MSIRC3)
MSI frequency
VDD = 3 V MSI range 13 198.84 200 202.86
fMSI after factory kHz
TJ = 30 °C
calibration MSI range 14 132.56 133 135.24
MSI range 15 99.42 100 101.43
MSI range 0
- 48.005 -
(MSIRC0)
MSI range 1 - 24.003 -
MSI range 2 - 16.002 -
MSI range 3 - 12.001 -
MSI range 4
- 3.998 -
PLL (MSIRC1)
mode(2) MSI range 5 - 1.999 - MHz
XTAL =
32.768 kHz MSI range 6 - 1.333 -
MSI range 7 - 0.999 -
MSI range 8
- 3.08 -
(MSIRC2)
MSI range 9 - 1.54 -
MSI range 10 - 1.027 -
MSI range 11 - 0.77 -
DS13543 Rev 2 251/390

352
Table 75. MSI oscillator characteristics(1) (continued)

MSI range 12
- 393 -
(MSIRC3)
MSI frequency PLL mode
VDD = 3 V MSI range 13 - 196.6 -
fMSI (cont’d) after factory XTAL = kHz
TJ = 30 °C
calibration 32.768 kHz MSI range 14 - 131 -
MSI range 15 - 98.3 -
MSI range 0, 4, 8, or 12 38 - 62
(3)
DuCyMSI Duty cycle MSI range 2, 6, 10, or 14 31 - 69
Other MSI ranges 48 - 52
User trimming
TRIMMSI - - 0.4 -
step
MSI oscillator
frequency drift
(4) over
∆ TEMP(MSI) MSI mode TJ = –40 to 130 °C -4 - 2
temperature
(reference is
30 °C)
MSI range 1.58 ≤ VDD ≤ 3.6 V -4 - 1

%
0 to 3 2.4 ≤ VDD ≤ 3.6 V -1 - 1
MSI range 1.58 ≤ VDD ≤ 3.6 V -3 - 1

MSI oscillator
4 to 7 2.4 ≤ VDD ≤ 3.6 V -1 - 1
frequency drift
∆ VDD(MSI)(4) MSI mode
over VDD 1.58 ≤ VDD ≤ 3.6 V -3 - 1
MSI range
(reference is 3V)
8 to 11 2.4 ≤ VDD ≤ 3.6 V -1 - 1
MSI range 1.58 ≤ VDD ≤ 3.6 V -3 - 1

12 to 15 2.4 ≤ VDD ≤ 3.6 V -1 - 1
MSI frequency
∆ FSAMPLING variation in
(3)(4) MSI mode TJ = –40 to 130 °C - - 0.2
(MSI) sampling mode
(MSIBIAS = 1)
MSI range 0 - 60 -
CC RMS cycle-to- MSI range 4 - 160 -

PLL mode
jitter(MSI)(3) cycle jitter MSI range 8 - 200 -
MSI range 12 - 1100 -
ps
MSI range 0 - 40 -
MSI range 4 - 130 -
P jitter(MSI)(3) RMS period jitter PLL mode
MSI range 8 - 170 -
MSI range 12 - 800 -
252/390 DS13543 Rev 2


13
MSIRC0
MSI range 0 to 3 - - cycles +
11 MSI
cycles
4
MSIRC1
11 MSI
MSI oscillator cycles
tsu(MSI)(3)
startup time(5) 4
cycles
MSIRC2
11 MSI
cycles
4
MSIRC3
11 MSI
cycles
3
MSI oscillator destina-
tswitch(MSI)(3) - - -
transition time(6) tion MSI
cycles
Continuous
- - 10
Normal mode(7)
Final frequency µs
mode Sampling
- - 200
mode(8)
MSI oscillator PLL mode,
tstab(MSI)(3) All MSI 1% of final
stabilization time MSIPLL - - 0.8 ms
ranges frequency
FAST = 0
PLL mode,
cycles
MSIPLL All MSI ranges 2
FAST = 1
MSI range 0 to 3 - 6.6 -
MSI PLL-mode LDO
oscillator power MSI range 8 to 11 - 1.4 -
MSIPLL
consumption MSI range 12 to 15 - 0.8 -
IDD(MSI_OFF EN = 1 and
(3) when MSI is µA
_PLLFAST) MSIPLL MSI range 0 to 3 - 4.7 -
disabled with
FAST = 1
PLL accuracy MSI range 4 to 7 - 1.4 -
retention SMPS
MSI range 12 to 15 - 0.8 -
DS13543 Rev 2 253/390

352

21 + 2.5
MSI range 0 to 3 - -
µA/MHz
LDO
19 + 2.5
Continuous µA/MHz
mode(7) 21 + 1,3
µA/MHz
SMPS(9)
19 + 1,3
MSI oscillator µA/MHz
IDD(MSI)(3) power 3 + 2.5 µA
consumption Range 0 to 3 - -
µA/MHz
LDO 1+
Range 4 to 15 - 2.5µA/ -
Sampling MHz
mode(8)
3+1
Range 0 to 3 - -
µA/MHz
SMPS
1+1
Range 4 to 15 - -
µA/MHz
1. Evaluated by characterization and not tested in production, unless otherwise specified.
2. In PLL mode, the MSI accuracy is the LSE crystal accuracy.
4. This is a deviation for an individual part once the initial frequency has been measured.
5. The MSI startup time is the time when the four MSIRCs are in power down.
6. This delay is the time to switch from one MSIRC to another one. In case the destination MSIRC is in power down, the total
delay is tsu(MSI) + tswitch(MSI).
7. The MSI is in continuous mode when the internal regulator is in voltage range 1, 2 or 3.
8. The MSI is in sampling mode when MSIBIAS = 1 in RCC_ICSCR1, and the regulator is in voltage range 4, or when the
device is in Stop 1 or Stop 2 mode.
9. SMPS efficiency in range 1, based on VCORE current = 19.4 mA.
High-speed internal 48 MHz (HSI48) RC oscillator
Table 76. HSI48 oscillator characteristics

fHSI48 HSI48 frequency after factory calibration VDD = 3.0 V, TJ = 30 °C 47.5 48 48.5 MHz
254/390 DS13543 Rev 2

Table 76. HSI48 oscillator characteristics (continued)

(1)
TRIMHSI48 User trimming step - - 0.12 0.18
USER TRIM
User trimming coverage ±63 steps ±4.5 ±7.56 -
COVERAGE(2)
DuCyHSI48(1) Duty cycle - 45 - 55
Accuracy of the HSI48 oscillator over %
ACCHSI48_REL 1.58 V ≤ VDD ≤ 3.6 V,
(2) temperature (factory calibrated) -3 - 2
TJ = –40 to 125 °C
Reference is 3 V and 30 °C(3).
3.0 V ≤ VDD ≤ 3.6 V - 0.025 0.05
∆VDD(HSI48)(1) HSI48 frequency drift with VDD(4)
1.58 V ≤ VDD ≤ 3.6 V - 0.05 0.1
Next transition jitter
NT jitter(1) - - ±0.15 -
Accumulated jitter on 28 cycles(5)
ns
Paired transition jitter
PT jitter(1) - - ±0.25 -
Accumulated jitter on 56 cycles(5)
tsu(HSI48)(1) HSI48 oscillator startup time - - 2.5 6 μs
(1)
IDD(HSI48) HSI48 oscillator power consumption - - 350 400 μA
3. ∆fHSI = ACCHSI48_REL + ∆VDD.
4. These values are obtained with one of the following formula: (Freq(3.6 V) - Freq(3.0 V)) / Freq(3.0 V) or
(Freq(3.6 V) - Freq(1.58 V)) / Freq(1.58 V).
5. Jitter measurements are performed without clock source activated in parallel.
Figure 33. HSI48 frequency versus temperature
MSv69123V1
DS13543 Rev 2 255/390

352
Secure high-speed internal (SHSI) RC oscillator
Table 77. SHSI oscillator characteristics(1)

fSHSI SHSI frequency - - 48 - MHz

tSU(SHSI) SHSI oscillator startup time - - 2.5 6 μs
IDD(SHSI) SHSI oscillator power consumption - - 350 400 μA
Low-speed internal (LSI) RC oscillator
Table 78. LSI oscillator characteristics

VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 0 31.4 - 32.6

fLSI LSI frequency VDD = 3.0 V, TJ = 30 °C, LSIPREDIV = 1 0.245 - 0.255 kHz
1.58 V≤ VDD ≤ 3.6 V, TJ = –40 to 125 °C 30.4(1) - 33.6(1)
DuCyLSI LSI duty cycle LSIPREDIV = 1 - 50 - %
tSU(LSI) (2) LSI oscillator startup time - - 230 260
μs
(2)
tSTAB(LSI) LSI oscillator stabilization time 5% of final frequency - 230 260
LSI oscillator power LSIPREDIV = 0 - 140 255

IDD(LSI)(2) nA
consumption LSIPREDIV = 1 - 130 240
5.3.10 PLL characteristics

The parameters given in the table below are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 33.
Table 79. PLL characteristics(1)

PLL input clock - 4 - 16 MHz

fPLL_IN PLL input clock
- 10 - 90 %
duty cycle
Voltage scaling range 1 1 - 160(2)
PLL P, Q, R
fPLL_OUT Voltage scaling range 2 1 - 110
output clock
Voltage scaling range 3 1 - 55 MHz
Voltage scaling range 1, 2 128 - 544
fVCO_OUT PLL VCO output Voltage scaling range 3 128 - 330
Duty cycle with division 1 40 - 60 %
256/390 DS13543 Rev 2

Table 79. PLL characteristics(1) (continued)

Integer mode - 25 50
tLOCK(3)(4) PLL lock time μs
Fractional mode - 40 65
RMS cycle-to- Integer mode, VCO = 544 MHz - 20 -

cycle jitter Fractional mode, VCO = 544 MHz - 70 -
Integer mode, VCO = 544 MHz - 35 -
Jitter RMS period jitter ±ps
Fractional mode, VCO = 544 MHz - 45 -
Long-term Integer mode, VCO = 544 MHz - 160 -
jitter(5),
fPLL_IN = 8 MHz Fractional mode, VCO = 544 MHz - 170 -
VCO freq = 160 MHz,

Range 1 - 370 -
1 clock output
VCO freq = 160 MHz,
Range 1 - 390 -
3 clock outputs
PLL power Range 1 - 460 -
consumption on VCO freq = 200 MHz,
IDD(PLL) Range 2 - 435 -
VDD 1 clock output
with LDO Range 3 - 410 -
VCO freq = 336 MHz,
Range 1 - 710 -
1 clock output
VCO freq = 544 MHz,
Range 1 - 1100 -
1 clock output
μA
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA - 260 -
1 clock output
VCO freq = 160 MHz,
Range 1, IVCORE(6) = 19.4 mA - 270 -
3 clock outputs
PLL power Range 1, IVCORE(6) = 19.4 mA - 320 -
consumption on VCO freq = 200 MHz,
IDD(PLL) Range 2, IVCORE(6) = 11.7 mA - 300 -
VDD 1 clock output
with SMPS Range 3, IVCORE(6) = 5.74 mA - 290 -
VCO freq = 336 MHz,
Range 1, IVCORE(6) = 19.4 mA - 470 -
1 clock output
VCO freq = 544 MHz,
Range 1, IVCORE(6) = 19.4 mA - 730 -
1 clock output
1. Specified by design and not tested in production, unless otherwise specified.
2. PLL1 output Q and PLL2 output Q can be up to 200 MHz only when selected as OCTOSPI clock.
4. Lock time is the duration until PLLxRDY flag (2% of final frequency).
5. Measured on 5000 cycles.
6. SMPS efficiency based on CoreMark RUN current on VCORE at max frequency of each voltage range.
DS13543 Rev 2 257/390

352
5.3.11 Flash memory characteristics
Table 80. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max(2) Unit
Normal mode 118 119

tprog 128-bit programming time µs
Burst mode 47 48
fAHB = 160 MHz, normal mode 60.2 -
tprog_page One 8-Kbyte page programming time
fAHB = 160 MHz, burst mode 24.5 -
fAHB = 160 MHz, normal mode 15420 -
tprog_bank One 2-Mbyte bank programming time
fAHB = 160 MHz, burst mode 6280 -
ms
10 k endurance cycles 1.5 2.4
tERASE One 8-Kbyte page erase time
100 k endurance cycles 1.7 3.4
Mass erase time (one bank) 220 616
tME 10 k endurance cycles
Mass erase time (two banks) 440 1230
Write mode 2.1 -
Average consumption from VDD
Erase mode 1.3 -
IDD(3) mA
Write mode 2.6 -
Maximum current (peak)
Erase mode 3.0 -
2. Evaluated by characterization after cycling. Not tested in production.
Table 81. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
Whole bank 10
NEND Endurance TA = –40 to 125 °C kcycles
Limited to 256 Kbytes per bank 100
TA = 85 °C after 1 kcycle(2) 30
TA = 105 °C after 1 kcycle (2)
15
Whole bank
TA = 55 °C after 10 kcycle (2)
30
tRET Data retention TA = 85 °C after 10 kcycle(2) 15 Years
(2)
TA = 105 °C after 10 kcycle 10
Limited to 256 Kbytes per bank TA = 85 °C after 100 kcycle(2) 15
2. Cycling performed over the whole temperature range.
258/390 DS13543 Rev 2

5.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling two LEDs through the
I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The
failure is indicated by the LEDs as follows:
• Electrostatic discharge (ESD) (positive and negative): applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB (fast transient voltage burst) (positive and negative): applied to VDD and VSS pins
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in the table below. They are based on the EMS levels and classes
defined in application note EMC design guide for STM8, STM32 and Legacy MCUs
(AN1709).
Table 82. EMS characteristics

Level/
Symbol Parameter Conditions
Class
Voltage limits to be applied on any I/O pin to VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
VFESD 3B
induce a functional disturbance TFBGA216 conforming to IEC 61000-4-2
Fast transient voltage burst limits to be
VDD = 3.3 V, TA = +25 °C, fHCLK = 160 MHz,
VEFTB applied through 100 pF on VDD and VSS pins 5A
TFBGA216 conforming to IEC 61000-4-4
to induce a functional disturbance
Designing hardened software to avoid noise problems

The EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. Note that good EMC performance is
highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
DS13543 Rev 2 259/390

352
to prevent unrecoverable errors occurring. See application note Software techniques for
improving microcontrollers EMC performance (AN1015) for more details.
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard that specifies the test board and the pin loading.
Table 83. EMI characteristics (for fHSE = 8 MHz, fHCLK = 160 MHz)
Monitored frequency
Symbol Parameter Conditions Value Unit
band
0.1 MHz to 30 MHz 4

30 MHz to 130 MHz 11
Peak(1) VDD = 3.6 V, TA = 25 °C, dBμV
SEMI TFBGA216 package 130 MHz to 1 GHz 13
compliant with IEC 61967-2
1 GHz to 2 GHz 9
Level(2) 0.1 MHz to 2 GHz 2.5 -
1. Refer to the ‘EMI radiated test’ section of the application note EMC design guide for STM8, STM32 and legacy MCUs
(AN1709).
2. Refer to the ‘EMI level classification’ section of the same application note AN1709.
5.3.13 Electrical sensitivity characteristics

Based on three different tests (ESD, latch-up) using specific measurement methods, the
device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 84. ESD absolute maximum ratings

Symbol Ratings Conditions Packages Class Max. value(1) Unit
Electrostatic discharge TA = +25 °C, conforming to

VESD(HBM) All 2 2000
voltage (human body model) ANSI/ESDA/JEDEC JS-001
LQFP64 C2a 500
LPQF100 C1 250
LQFP144 C1 250
Electrostatic discharge V
TA = +25 °C, conforming to UFBGA132 C2b 750
VESD(CDM) voltage (charge device
ANSI/ESDA/JEDEC JS-002 WLCSP150 - -
model)
TFBGA169 C2b 750
WLCSP208 C1 250
TFBGA216 C2a 500
260/390 DS13543 Rev 2

Static latch-up
The following complementary static tests are required on three parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78E IC latch-up standard.
Table 85. Electrical sensitivities(1)

Symbol Parameter Conditions Class
LU Static latch-up class TJ = 130 °C conforming to JESD78E Class II level A

5.3.14 I/O current injection characteristics

As a general rule, the current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) must be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller if
abnormal injection accidentally happens, some susceptibility tests are performed on a
sample basis during the device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating-input mode. While this current is injected
into the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter, such as an ADC error above a certain
limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on
adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset
occurrence or oscillator frequency deviation).
DS13543 Rev 2 261/390

352
The characterization results are given in the table below. The negative induced leakage
current is caused by the negative injection.The positive induced leakage current is caused
by the positive injection.
Table 86. I/O current injection susceptibility(1)(2)

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on all pins except TT_a, PA4, PA5, DSI_DN_DL1,

DSI_DP_DL1, DSI_DN_CL1, DSI_DP_CL1, DSI_DN_DL2, DSI_DP_DL2,
5 NA
OPAMP1_VINM, OPAMP2_VINM, PA11, PA12, PE11, PE12, PE7,PB14,
PB5, PA1
IINJ Injected current on TT_a, PA4, PA5, DSI_DN_DL1, DSI_DP_DL1, mA

DSI_DN_CL1, DSI_DP_CL1, DSI_DN_DL2, DSI_DP_DL2, 0 0
OPAMP1_VINM, OPAMP2_VINM, PA11, PA12 pins
Injected current on PE11, PE12, PE7 pins 0 NA
Injected current on PB14, PB5, PA1 pins 5 0
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For
instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
5.3.15 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the conditions summarized in Table 33. All I/Os are designed as
CMOS -and TTL-compliant.
Note: For information on GPIO configuration, refer to the application note ‘STM32 GPIO
configuration for hardware settings and low-power consumption’ (AN4899).
Table 87. I/O static characteristics(1)

Symbol
Unit
Parameter Conditions Min Typ Max
1.08 V ≤ VDDIOx ≤ 3.6 V - - 0.3 VDDIOx

I/O input
VIL(2) low-level All I/Os except FT_c - - 0.38 VDDIOx(3)
voltage
FT_c I/Os - - 0.3 VDDIOx
1.08 V ≤ VDDIOx ≤ 3.6 V 0.7 VDDIOx - - V
I/O input
VIH 0.5 VDDIOx
high-level All I/Os except FT_c - -
(2) + 0.2(3)
voltage
FT_c I/Os 0.7 VDDIOx - -
Vhys Input
(3) TT_xx, FT_xx I/Os - 250 - mV
hysteresis
262/390 DS13543 Rev 2

Table 87. I/O static characteristics(1) (continued)

Symbol
Unit
Parameter Conditions Min Typ Max
VIN ≤ Max (VDDXXX)(5) - - 150

All I/Os except FT_c, Max (VDDXXX) < VIN
- - 2000
FT_d, FT_o, FT_t, ≤ Max (VDDXXX) + 1 V(6)
FT_u,TT_xx
Max (VDDXXX) + 1 V < VIN
- - 500
≤ 5.5 V(6)
FT_c I/Os
(6)
Max (VDDXXX) < VIN ≤ 5 V - - 2000
FT_d I/Os
Max (VDDXXX) < VIN ≤ 5.5 V(6) - - 5000
VIN ≤ Max (VDDXXX )(5) - - 50
Input Max (VDDXXX) < VIN

Ilkg - - 500
FT_o I/Os ≤ Max (VDDXXX) + 1 V(6)
(3)(4) leakage
current Max (VDDXXX) + 1 V < VIN
- - 200
≤ 5.5 V(6)
nA
Max (VDDXXX) < VIN
- - 2500
FT_u I/Os ≤ Max (VDDXXX) + 1 V(6)
- - 500
≤ 5.5 V(6)
Max (VDDXXX) < VIN
- - 3000
FT_t I/Os ≤ Max (VDDXXX) + 1 V(6)
- - 600
≤ 5.5 V(6)
TT_xx I/Os except
Input OPAMPx_VINM VIN ≤ Max (VDDXXX)(5) - - 500
Ilkg (x = 1, 2)
(3)(4) leakage
current OPAMPx_VINM (x = 1, 2) dedicated input leakage (7)
- -
current
Weak
RPU pull-up - 30 40 50
equivalent
Weak kΩ
pull-down
RPD - 30 40 50
equivalent
resistor(8)
I/O pin
CIO - - 5 - pF
capacitance
DS13543 Rev 2 263/390

352
2. Refer to Figure 34: I/O input characteristics (all I/Os except BOOT0 and FT_c).
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg max.
5. Max (VDDXXX) is the maximum value of all the I/O supplies. The I/O supplies depend on the I/O structure options, as
described in Table 26: Legend/abbreviations used in the pinout table.
6. To sustain a voltage higher than Min (VDD, VDDA, VDDUSB, VDDIO2) +0.3 V, the internal pull-up and pull-down resistors must
be disabled.
7. Refer to Ibias in the OPAMP characteristics table for the values of the OPAMP dedicated input leakage current.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
This PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in the figure below.
Figure 34. I/O input characteristics (all I/Os except BOOT0 and FT_c)
MSv69136V1
Output driving current

The GPIOs (except PC13, PC14, PC15) can sink or source up to ±8 mA, and sink or source
up to ± 20 mA (with a relaxed VOL/VOH). PC13, PC14, PC15 are limited in source capability:
+3 mA shared between the three I/Os. These GPIOs have the same sink capability than
other GPIOs.
264/390 DS13543 Rev 2

In the user application, the number of I/O pins tat can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2: Absolute maximum ratings:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 31: Current characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS
(see Table 31: Current characteristics).
Output voltage levels

performed under the ambient temperature and supply voltage conditions summarized in
Table 33. All I/Os are CMOS- and TTL-compliant (FT OR TT unless otherwise specified).
Table 88. Output voltage characteristics (all I/Os except FT_t I/Os in VBAT mode(1),
and FT_o I/Os)(2)(3)
VOL Output low-level voltage CMOS port(4), |IIO| = 8 mA, - 0.4

VOH Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 0.4 -
VOL(5) Output low-level voltage TTL port(4),|IIO| = 8 mA, - 0.4
VOH(5) Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V 2.4 -
VOL(5) Output low-level voltage All I/Os, |IIO| = 20 mA, - 1.3
VOH(5) Output high-level voltage 2.7 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 1.3 -
VOL(5) Output low-level voltage |IIO| = 4 mA, - 0.4
VOH(5) Output high-level voltage 1.58 V ≤ VDDIOx ≤ 3.6 V VDDIOx - 0.4 - V
VOL(5) Output low-level voltage |IIO| = 1 mA, - 0.4
VOH(5) Output high-level voltage 1.08 V ≤ VDDIOx <3.6 V VDDIOx - 0.4 -
|IIO| = 20 mA,
- 0.4
2.7 V ≤ VDDIOx ≤ 3.6 V
Output low-level voltage for |IIO| = 10 mA,
VOLFM+(5) - 0.4
a FT_f I/O pin in FM+ mode 1.58 V ≤ VDDIOx ≤ 3.6 V
|IIO| = 2 mA,
- 0.4
1.08 V ≤ VDDIOx < 3.6 V
1. FT_t I/O characteristics are degraded only in VBAT mode (refer to Table 89).
3. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 31:
Current characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
4. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
DS13543 Rev 2 265/390

352
Table 89. Output voltage characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os(1)
VOL Output low-level voltage - 0.4

|IIO| = 0.5 mA, 2.7 V ≤ VSW ≤ 3.6 V
VOH Output high-level voltage VSW - 0.4 -
V
VOL Output low-level voltage - 0.4
|IIO| = 0.25 mA, 1.58 V ≤ VSW≤ 3.6 V
VOH Output high-level voltage VSW - 0.4 -
Output AC characteristics
The definition and values of output AC characteristics are given in Figure 35: Output AC
characteristics definition and in the table below respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 33.
FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4)
Speed Symbol Parameter Conditions Min Max Unit
CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5

CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
Maximum frequency CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1
00
CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 17
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33
Output rise and fall time CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 85
tr/tf ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 25
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 50
266/390 DS13543 Rev 2

FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4) (continued)
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 55

CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12.5
Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 2.5

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 55
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12.5
CL = 10 pF, 1.08 V ≤ VDDIOx ≤<1.58 V - 2.5
01
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 5.8
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10
tr/tf ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 7.5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 12
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 100(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33(5)

Fmax MHz
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 133(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
10
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3.3(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 6.0(5)
Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 13.3
tr/tf ns
all I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.2
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 100(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33(5)
11 Fmax All I/Os except FT_c, FT_v, MHz
and TT_v CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 133(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
DS13543 Rev 2 267/390

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CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V (5)

- 140
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 40(5)

Fmax MHz
FT_v and TT_v I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 166(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 3.3(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 6.0(5)
11
tr/tf All I/Os except FT_c, FT_v,
(cont’d) CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2.0(5)
and TT_v
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.2
ns
CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 2.5(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.0(5)
tr/tf
FT_v and TT_v I/Os CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 1.66(5)
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 7
Fmax Maximum frequency CL = 550 pF, 1.08 V ≤ VDDIOx < 3.6 V - 1 MHz
CL = 100 pF, 1.58 V ≤ VDDIOx < 3.6 V - 50
Fm+ CL = 100 pF, 1.08 V ≤ VDDIOx < 1.58 V - 80
tf Output fall time(6) ns
CL = 550 pF, 1.58 V ≤ VDDIOx < 3.6 V - 100
CL = 550 pF, 1.08 V ≤ VDDIOx < 1.58 V - 220
3. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO
port configuration register.
5. Compensation system enabled.
6. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
268/390 DS13543 Rev 2


FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4)
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10

CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
Fmax Maximum frequency MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 15
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
00
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 18
CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 32
tr/tf Output rise and fall time ns
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 21
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 67
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
01
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.3
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10.6
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5.6
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75(5)
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
10
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4(5)
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.6
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4.7
DS13543 Rev 2 269/390

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(5)
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
Fmax MHz
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 110(5)

FT_v and TT_v I/Os CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 150(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 25
11
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4(5)
All I/Os except FT_c, FT_v,
and TT_v CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V 4.7
tr/tf ns
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.0(5)
FT_v and TT_v I/Os CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V 1.6(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 3.4
3. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.
5. Compensation system enabled.
Table 92. Output AC characteristics for FT_c I/Os(1)(2)

All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V - 10

All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
00
01
270/390 DS13543 Rev 2

Table 92. Output AC characteristics for FT_c I/Os(1)(2) (continued)


1x
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of
GPIO port configuration register.
Table 93. Output AC characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os(1)
CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V - 0.5

CL = 50 pF, 1.58 V ≤ VSW < 2.7 V - 0.25
CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V - 400
CL = 50 pF, 1.58 V ≤ VSW < 2.7 V - 900
Figure 35. Output AC characteristics definition
90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
MS32132V4
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5.3.16 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
performed under the ambient temperature and supply voltage conditions summarized
in Table 33.
Table 94. NRST pin characteristics(1)

VIL(NRST) NRST input low-level voltage - - - 0.3 × VDDIOx

V
VIH(NRST) NRST input high-level voltage - 0.7 × VDDIOx - -
NRST Schmitt trigger voltage
Vhys(NRST) - - 200 - mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
tF(NRST) NRST input filtered pulse - - - 50
1.71 V ≤ VDD ≤ 3.6 V 330 - - ns
tNF(NRST) NRST input not-filtered pulse
1.58 V ≤ VDD ≤ 3.6 V 1000 - -
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
Figure 36. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF(3)
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in the above table.
Otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
272/390 DS13543 Rev 2

5.3.17 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 95. EXTI input characteristics(1)
PLEC Pulse length to event controller - 20 - - ns

5.3.18 Analog switches booster
Table 96. Analog switches booster characteristics(1)

VDD Supply voltage 1.6 1.8 3.6 V

tSU(BOOST) Booster startup time - - 50 µs
IDD(BOOST) Booster consumption - - 125 µA
5.3.19 14-bit analog-to-digital converter (ADC12) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from
tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage
conditions summarized in Table 33.
Note: It is recommended to perform a calibration after each power-up.
Table 97. 14-bit ADC12 characteristics(1)(2)

Analog power supply for

VDDA - 1.62 - 3.6
ADC ON
Positive reference VDDA ≥ 2 V 2 - VDDA

VREF+ V
voltage VDDA < 2 V VDDA
Negative reference
VREF- - VSSA
voltage
ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 5(3) - 55 MHz
fADC
ADC clock ratio - 45 - 55 %
Resolution = 14 bits 0.23 - 2.5
fs Sampling rate Msps
tTRIG External trigger period Resolution = 14 bits 26 - - 1/fADC
Conversion voltage
VAIN(4) - 0 - VREF+ V
range
DS13543 Rev 2 273/390

352
Table 97. 14-bit ADC12 characteristics(1)(2) (continued)

Common mode input

VCIMV - VREF+/2 - 10% VREF+/2 VREF+/2 + 10% V
voltage
Resolution = 14 bits
- - 1000
Tj = 130 °C
Resolution = 12 bits
- - 1000
External input Tj = 130 °C
RAIN(5) Ω
impedance Resolution = 10 bits
- - 4700
Tj = 130 °C
Resolution = 8 bits
- - 22000
Tj = 130 °C
Internal sample-and-
CADC - - 5 - pF
hold capacitor
tADCVREG_
ADC LDO startup time - - - 17 µs
STUP
tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle
Offset and linearity
tCAL - - 31849 -
calibration time
tOFF_CAL Offset calibration time - - 885 -
Trigger conversion PRESC = 0 3
latency for regular and
PRESC = 1 7
tLATR injected channels,
without aborting the
PRESC = 2 13
conversion
1/fADC
Trigger conversion PRESC = 0 4
latency Injected
tLATRINJ PRESC = 1 9
channels aborting a
regular conversion PRESC = 2 17
ts Sampling time - 5 - 814
Total conversion time
tCONV (including sampling Resolution = N bits ts + N + 3
time)
274/390 DS13543 Rev 2


fs = 2.5 Msps,
- 970 -
resolution = 14 bits
fs = 1 Msps,
- 550 -
fs = 10 ksps,
- 130 -
ADC consumption on resolution = 14 bits
IDDA_D(ADC)
VDDA Differential mode fs = 2.5 Msps,
- 940 -
fs = 2.5 Msps,
- 840 -
fs = 2.5 Msps,
- 730 -
resolution = 8bits
fs = 2.5 Msps,
- 140 -
fs = 1 Msps,
- 80 -
fs = 10 ksps,
- 13 -
ADC consumption on resolution = 14 bits
IDDV_D(ADC) µA
VREF+ Differential mode f = 2.5 Msps,
s - 140 -
fs = 2.5 Msps,
- 140 -
fs = 2.5 Msps,
- 120 -
resolution = 8bits
fs = 2.5 Msps,
- 980 -
fs = 1 Msps,
- 550 -
fs = 10 ksps,
ADC consumption on - 130 -
IDDA_s(ADC) VDDA Singe-ended
mode fs = 2.5 Msps,
- 900 -
fs = 2.5 Msps,
- 840 -
fs = 2.5 Msps,
- 770 -
resolution = 8bits
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fs = 2.5 Msps,
- 160 -
fs = 1 Msps,
- 90 -
fs = 10 ksps,
ADC consumption on - 15 -
IDDV_s(ADC) VREF+ Single-ended µA
mode fs = 2.5 Msps,
- 150 -
fs = 2.5 Msps,
- 150 -
fs = 2.5 Msps,
- 150 -
resolution = 8bits
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. Degraded differential linearity error below 10 MHz.
4. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA.
5. The tolerance is 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
276/390 DS13543 Rev 2

The maximum value of RAIN can be found in the table below.
Table 98. Maximum RAIN for 14-bit ADC12(1)(2) (3)

Resolution RAIN max (Ω) Sampling time [ns] Sampling cycle at 5 MHz Sampling cycle at 55 MHz
47 142
14 bits
(2 LSB 68 145
tolerance)
100 170
47 135
68 135
100 140
12 bits 150 145
220 150
330 155
470 180 12
47 128 5
68 130
100 132
150 134
220 140
10 bits 330 146
470 160
680 176
1000 200
1500 240
20
2200 320
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352
Table 98. Maximum RAIN for 14-bit ADC12(1)(2) (3) (continued)

47 123
68 124
100 125
150 128
220 130
12
330 137
470 140
8 bits 680 157 5
1000 178
1500 204
2200 250
20
3300 313
4700 400
36
6800 546
10000 830 68
2. BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values.
3. Values without external capacitor.
Table 99. 14-bit ADC12 accuracy(1)(2)(3)

Single ended - ±6 ±12

ET Total unadjusted error
Differential - ±3 ±6
Single ended - ±6 ±12(5)
EO Offset error
Differential - ±2 ±6(5)
EG Gain error
Differential - ±2.5 ±5
LSB
Single ended -
fADC ≥ 10 MHz -0.9/+1.5 -0.9/+2.5
Differential -
ED Differential linearity error
Single ended -
fADC < 10 MHz -0.9/+1.5 -1/+3
Differential -
EL Integral linearity error
Differential - ±2 ±5
Single ended 11 12 -
ENOB Effective number of bits bits
Differential 11.8 12.8 -
278/390 DS13543 Rev 2

Table 99. 14-bit ADC12 accuracy(1)(2)(3) (continued)

Signal-to-noise and Single ended 68 74 -

SINAD
distortion ratio Differential 73 78 -
Single ended 68 74 -
SNR Signal-to-noise ratio dB
Differential 73 78 -
Single ended - -84 -80
THD Total harmonic distortion
Differential - -95 -89
1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.
2. ADC DC accuracy values are measured after the internal calibration.
3. Extended calibration mode activated.
4. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when
VDDA < 2.4 V). The booster is disabled when VDDA ≥ 2.4 V. Resolution = 14 bits, no oversampling.
5. This parameter may degrade in case of digital activity on adjacent I/Os.
Figure 37. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
DS13543 Rev 2 279/390

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Figure 38. Typical connection diagram when using the ADC

with FT/TT pins featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to the ADCx characteristic table for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance
(refer to Table 87: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades the
conversion accuracy. To remedy this, fADC must be reduced.
3. Refer to Table 87: I/O static characteristics for the values of Ilkg.
4. Refer to Section 5.1.6: Power supply scheme.
General PCB design guidelines

The power-supply decoupling must be performed as shown in the corresponding
power-supply scheme. The 100 nF capacitor must be ceramic (good quality) and must be
placed as close as possible to the chip.
5.3.20 12-bit analog-to-digital converter (ADC4) characteristics

Unless otherwise specified, the parameters given in the table below are values derived from
tests performed under ambient temperature, fHCLK frequency and VDDA supply voltage
Note: It is recommended to perform a calibration after each power-up.
Table 100. 12-bit ADC4 characteristics(1)(2)

Analog power supply for ADC

VDDA - 1.62 - 3.6
ON
V
VREF+ Positive reference voltage - 1 - VDDA
VREF- Negative reference voltage - VSSA
ADC clock frequency 1.62 V ≤ VDDA ≤ 3.6 V 0.14 - 55 MHz
fADC
ADC clock duty cycle - 45 - 55 %
fs Sampling rate Msps
Resolution = 6bits 0.0175 - 3.92
280/390 DS13543 Rev 2


tTRIG External trigger period Resolution = 12 bits 16 - - 1/fADC

VAIN(3) Conversion voltage range - 0 - VREF+ V
Resolution = 12 bits - - 2.2
External input impedance Resolution = 10 bits - - 6.8

RAIN(4) kΩ
Tj = 130 °C Resolution = 8 bits - - 33.0
Resolution = 6 bits - - 47.0
Internal sample and hold
CADC - - 5 - pF
capacitor
tADCVREG_
ADC LDO startup ready flag time - - - 25 µs
STUP
tSTAB ADC power-up time LDO already started (3 × 1/fADC) + 1 conversion Cycle
tOFF_CAL Offset calibration time - - 123 -
WAIT = 0, AUTOFF = 0,
4
DPD = 0, fADC = HCLK
tLATR Trigger conversion latency 4
DPD = 0, fADC = HCLK/2
3.75
DPD = 0, fADC = HCLK/4
ts Sampling time - 1.5 - 814.5
1/fADC
Resolution = N bits,
ts + N + 0.5
VREFPROTEN = 0
Total conversion time (including VREFPROTEN = 1 ts + N + 0.5 - ts + N + 1.5
tCONV
sampling time) VREFSECSMP = 0
VREFPROTEN = 1 ts + N + 0.5 - ts + N + 2.5
VREFSECSMP = 1
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fs = 2.5 Msps - 360 -

fs = 1 Msps - 180 -
fs = 10 ksps - 10 -
IDDA(ADC) ADC consumption on VDDA
AUTOFF = 1, DPD = 0,
- 9 -
no conversion
- 0.1 -
no conversion
µA
fs = 2.5 Msps - 18 -
fs = 1 Msps - 10.2 -
fs = 10 ksps - 0.12 -
IDDV(ADC) ADC consumption on VREF+
- 0.01 -
no conversion
- 0.01 -
no conversion
2. The voltage booster on the ADC switches must be used when VDDA < 2.4 V (embedded I/O switches).
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA.
4. The tolerance is 2 LSBs.
282/390 DS13543 Rev 2

The maximum value of RAIN can be found in the table below.
Table 101. Maximum RAIN for 12-bit ADC4(1)(2)(3)

47 276
68 288
12.5 19.5
100 306
150 336
220 377
330 442 19.5
39.5
470 526
680 650
1000 840 39.5
12 bits 79.5
1500 1134
2200 1643 79.5
3300 2395
4700 3342
6800 4754 814.5
10000 6840 814.5
15000 9967
22000 14068
33000 19933 N/A
47 86
68 90 3.5
100 95
7.5
150 108
220 116
330 136 7.5
470 161
10 bits 12.5
680 212
1000 276 12.5 19.5
1500 376 39.5
19.5
2200 516
3300 735 79.5
39.5
4700 1012
6800 1423 79.5 814.5
DS13543 Rev 2 283/390

352
Table 101. Maximum RAIN for 12-bit ADC4(1)(2)(3) (continued)

10000 2040
15000 2978
10 bits
22000 4356 814.5 814.5
(cont’d)
33000 6443
47000 8925
47 45
68 46
100 48 3.5
150 53 3.5
220 59
330 69
470 81
7.5
680 101
1000 130 7.5
8 bits 1500 177 12.5
2200 242
12.5 19.5
3300 345
4700 475 19.5
39.5
6800 670
39.5
10000 963
79.5
15000 1417
79.5
22000 2040
33000 2995 814.5
814.5
47000 4158
47 32
68 32
100 33
1.5
150 35
3.5
220 37
6 bits
330 41
470 49
680 61 3.5
1000 79
7.5
1500 106 7.5
284/390 DS13543 Rev 2

Table 101. Maximum RAIN for 12-bit ADC4(1)(2)(3) (continued)

2200 146
7.5 12.5
3300 207
4700 286 12.5 19.5
6 bits 6800 404 19.5

39.5
(cont’d) 10000 584 39.5
22000 1250 79.5
79.5
33000 1853
814.5
47000 2607 814.5
2. BOOSTEN and ANASWVDD configured properly according to VDD and VDDA values.
3. Values without external capacitor.
Table 102. 12-bit ADC4 accuracy(1)(2) (3)

ET Total unadjusted error - - ±3 ±7.5

EO Offset error - - ±2 ±5.5
EG Gain error - - ±2 ±6.5 LSB
ED Differential linearity error - - -0.9/+1 -0.9/+1.5
EL Integral linearity error - - ±2 ±3.5
ENOB Effective number of bits - 9.9 10.9 - bits
SINAD Signal-to-noise and distortion ratio - 61.4 67.4 -
SNR Signal-to-noise ratio - 61.6 67.5 - dB
THD Total harmonic distortion - - -74 -70
1. Evaluated by characterization for BGA packages. Not tested in production. The values for LQFP packages may differ.
2. ADC DC accuracy values are measured after the internal calibration.
3. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in SYSCFG_CFGR1 when
VDDA < 2.4 V). This switch is disabled when VDDA ≥ 2.4 V. Resolution = 12 bits, no oversampling.
See Figure 37: ADC accuracy characteristics, Figure 38: Typical connection diagram when
using the ADC with FT/TT pins featuring analog switch function, and General PCB design
guidelines.
5.3.21 Temperature sensor characteristics
Table 103. Temperature sensor characteristics

TL(1) VSENSE linearity with temperature - - 1.3 °C

(1)
Avg_Slope Average slope 2 2.5 3.0 mV/°C
DS13543 Rev 2 285/390

352
Table 103. Temperature sensor characteristics (continued)

V30(2) Voltage at 30°C (±1 °C) 700 752 800

∆(Vcontinuous - Difference of voltage between continuous and mV
- - -10/+4
Vsampling)(3) sampling modes(4)
tSTART
(3) Sensor buffer startup time - 1 10
(TS_BUF)
µs
tS_temp (3) ADC sampling time when reading the temperature 13 - -
Temperature sensor consumption from VDD, when

IDD(TS)(3) - 14 20 µA
selected by ADC
2. Measured at VREF+ = VDDA = 3.0 V ±10 mV. The V30 A/D conversion result is stored in the TS_CAL1 byte. Refer to
Table 16: Temperature sensor calibration values.
4. The temperature sensor is in continuous mode when the regulator is in range 1, 2 or 3. The temperature sensor is in
sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 mode.
5.3.22 VCORE monitoring characteristics
Table 104. VCORE monitoring characteristics(1)

ADC sampling time when reading the VCORE

tS_VCORE 1 - - µs
voltage
5.3.23 VBAT monitoring characteristics
Table 105. VBAT monitoring characteristics(1)

R Resistor bridge for VBAT - 4 × 25.6 - kΩ

Q Ratio on VBAT measurement - 4 - -
(2)
Er Error on Q -5 - 5 %
tS_VBAT(2) ADC sampling time when reading the VBAT 5 - - µs
1. 1.58 V ≤ VBAT ≤ 3.6 V
Table 106. VBAT charging characteristics

VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -
286/390 DS13543 Rev 2

5.3.24 Digital-to-analog converter characteristics
Table 107. DAC characteristics(1)

Analog supply voltage for

VDDA - 1.6 - 3.6
DAC ON
VREF+ Positive reference voltage - 1.6 - VDDA V
VREF- Negative reference voltage - - VSSA -
DAC output connected to VSSA 5 - -

RL Resistive load
buffer ON connected to VDDA 25 - -
RO Output impedance DAC output buffer OFF 10 13 16
Output impedance sample VDDA = 2.7 V - - 1.5
kΩ
RBON and hold mode, output
buffer ON VDDA = 2.0 V - - 2.5
Output impedance sample VDDA = 2.7 V - - 16.5

RBOFF and hold mode, output
buffer OFF VDDA = 2.0 V - - 17.5
CL DAC output buffer OFF - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF
Voltage on DAC_OUT DAC output buffer ON 0.2 - VDDA - 0.2

VDAC_OUT V
output DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 3.05
Settling time (full scale: for Normal mode
a 12-bit code transition ±1 LSB - 1.90 3
DAC output
between the lowest and the buffer ON ±2 LSB - 1.85 2.85
highest input codes when CL ≤ 50 pF,
tSETTLING ±4 LSB - 1.80 2.8
DAC_OUT reaches the RL ≥ 5 kΩ
final value of ±0.5 LSB, ±8 LSB - 1.75 2.65
±1 LSB, ±2 LSB, ±4 LSB, µs
or ±8 LSB) Normal mode DAC output
- 1.7 3
buffer OFF, ±1 LSB, CL = 10 pF
Wake-up time from off state Normal mode DAC output buffer
- 4.2 7.5
tWAKEUP (setting the ENx bit in the ON, CL ≤ 50 pF, RL = 5 kΩ
(2) DAC control register) until Normal mode DAC output
the final value ±1 LSB - 2 5
buffer OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode DAC output buffer
PSRR 35 -80 -28 dB
ratio ON, CL ≤ 50 pF, RL = 5 kΩ
DS13543 Rev 2 287/390

352
Table 107. DAC characteristics(1) (continued)

DAC output buffer

DAC_OUT - 0.7 1.9
ON, CSH = 100 nF
Sampling time in sample pin ms
and hold mode, connected DAC output buffer
- 10.5 15
CSH = 100 nF OFF, CSH = 100 nF
(code transition between
tSAMP DAC_OUT
the lowest input code and
pin not
the highest input code
connected DAC output buffer
when DACOUT reaches - 2 8 µs
(internal OFF
the final value ±1 LSB)
connection
only)
(3)
Ileak Output leakage current - - - nA
Internal sample and hold

CIint - 7 9.2 11 pF
capacitor
tTRIM Middle code offset trim time DAC output buffer ON 50 - - µs
Middle code offset for VREF+ = 3.6 V - 1520 -

Voffset µV
1 trim code step VREF+ = 1.6 V - 680 -
No load, middle
- 330 510
DAC output code (0x800)
buffer ON No load, worst
- 470 680
code (0xF1C)
DAC consumption No load,

IDDA(DAC) DAC output
from VDDA middle/worst code - - 0.3
buffer OFF
(0x800)
330 × TON 680 × TON
Sample and hold mode, /(TON + /(TON +
-
CSH = 100 nF TOFF) TOFF)
(4) (4)
No load, middle
- 170 240
DAC output code (0x800)
µA
buffer ON No load, worst
- 300 400
code (0x0E4)
No load,
DAC output
middle/worst code - 145 180
buffer OFF
(0x800)
DAC consumption
IDDV(DAC)
from VREF+ 170 × TON 400 × TON
Sample and hold mode, buffer /(TON + /(TON +
-
ON, CSH = 100 nF (worst code) TOFF) TOFF)
(4) (4)
145 × TON 180 × TON

Sample and hold mode, buffer /(TON + /(TON +
-
OFF, CSH = 100 nF (worst code) TOFF) TOFF)
(4) (4)
288/390 DS13543 Rev 2

2. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
3. Refer to Table 87: I/O static characteristics.
4. TON is the refresh phase duration. TOFF is the hold phase duration (see the product reference manual for more details).
Figure 39. 12-bit buffered/non-buffered DAC

Buffered/non-buffered DAC
Buffer(1)
RLOAD
12-bit DAC_OUTx
digital-to-analog
converter
CLOAD
(1) The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads
directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in
the DAC_CR register. MSv47959V2
Table 108. DAC accuracy(1)

Differential DAC output buffer ON - - ±2

DNL LSB
non-linearity(2) DAC output buffer OFF - - ±2
- Monotonicity 10 bits guaranteed -
Integral DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ - - ±4

INL
non-linearity(3) DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±4
Offset error at code
Offset DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±8
0x800(3)
LSB
Offset error at code
Offset1 DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±5
0x001(4)
Offset error at code VREF+ = 3.6 V - - ±5
DAC output buffer ON,
OffsetCal 0x800(3)
CL ≤ 50 pF, RL ≥ 5 kΩ VREF+ = 1.6 V - - ±5
after calibration
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ - - ±0.5
Gain Gain error(5) %
DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±0.5
DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±10
TUE Total unadjusted error DAC output buffer ON, C ≤ 50 pF, R ≥ 5 kΩ, LSB
L L - - ±14
after calibration
DS13543 Rev 2 289/390

352
Table 108. DAC accuracy(1) (continued)

DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ,

- 70.6 -
Signal-to-noise 1 kHz, BW = 500 kHz
SNR
ratio(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz,
- 72 -
BW = 500 kHz
DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - -79 - dB
Total harmonic
THD
distortion(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - -81 -
Signal-to-noise and DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 70.1 -
SINAD
distortion ratio(6) DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 71.5 -
Effective number DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz - 11.3 -
ENOB bits
of bits DAC output buffer OFF, CL ≤ 50 pF, no RL, 1 kHz - 11.6 -
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at code i and the value measured at code i on a line drawn between code 0 and
last code 4095.
4. Difference between the value measured at code (0x001) and the ideal value.
5. Difference between the ideal transfer-function slope and the measured slope computed from code 0x000 and 0xFFF when
the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5 dBFS with Fsampling = 1 MHz.
5.3.25 Voltage reference buffer characteristics
Table 109. VREFBUF characteristics(1)

VRS = 000 1.8 -

VRS = 001 2.1 -
Normal mode 3.6
VRS = 010 2.4 -
Analog supply VRS = 011 2.8 -

VDDA
voltage VRS = 000 - 1.8
Degraded VRS = 001 - 2.1

1.62 V
mode(2) VRS = 010 - 2.4
VRS = 011 - 2.8
VRS = 000 1.496 1.5 1.504
Normal mode at
VREFBUF_ VRS = 001 1.795 1.8 1.805
Voltage reference VDDA = 3 V,
OUT
(3) buffer output TJ = 30 °C, VRS = 010 2.042 2.048 2.054
Iload = 10 µA
VRS = 011 2.493 2.5 2.507
290/390 DS13543 Rev 2

Table 109. VREFBUF characteristics(1) (continued)

Min (VDDA - 0.15

VRS = 000 - 1.504
;1.496)
VREFBUF_ Min (VDDA - 0.15

VRS = 001 - 1.805
OUT Voltage reference Degraded ;1.795)
V
(3) buffer output mode(2) Min (VDDA - 0.15
(cont’d) VRS = 010 - 2.054
;2.042)
Min (VDDA - 0.15
VRS = 011 - 2.507
;2.493)
TRIM Trim step - 0.1 0.175 0.25 %
CL Load capacitor(4) - 0.5 1.10 1.50 µF
CL equivalent serial
esr - - - 2 Ω
resistor
Iload Static load current - - - 4 mA
RPD Pull-down resistance - - - 400 Ω
VDDAmin ≤ VDDA ≤ 3.6 V,
Iline_reg Line regulation Normal mode, ±0.016 ±0.033 ±0.053 %
500 µA ≤ Iload ≤ 4 mA
Normal mode, ppm/
Iload_reg Load regulation(5) - 50 400
500 μA ≤ Iload ≤ 4 mA mA
Temperature Tcoeff_vrefint ppm/
TCoeff –40 °C < TJ < +130 °C - -
coefficient + 50 °C
Power supply DC - 65 -
PSRR dB
rejection 100 kHz - 30 -
CL = 0.5 µF - 110 200
tSTART Startup time CL = 1.1 µF - 240 350 µs
CL = 1.5 µF - 320 500
Control of DC
current drive on
IINRUSH VREFBUF_ - - 8 11 mA
OUT during startup
phase (6)
Iload = 0 µA - 14 18
VREFBUF
IDDA
consumption from Iload = 500 µA - 16 20 µA
(VREFBUF) V
DDA
Iload = 4 mA - 42 50
2. In degraded mode, the voltage reference buffer can not accurately maintain the output voltage (VDDA - drop voltage).
4. The capacitive load must include a 100 nF capacitor in order to cut off the high-frequency noise.
5. The load regulation value only takes into account the die and package resistance. The parasitic resistance on PCB
degrades this value.
6. To correctly control the VREFBUF inrush current during startup phase and scaling change, the VDDA voltage must be in the
range of [1.8 V-3.6 V], [2.1 V-3.6 V], [2.4 V-3.6 V] and [2.8 V-3.6 V] for VRS = 000, 001, 010 and 011 respectively.
DS13543 Rev 2 291/390

352
Figure 40. VREFBUF_OUT versus temperature (VRS = 000)
MSv69705V1
MSv69706V1
MSv69707V1
292/390 DS13543 Rev 2

MSv69708V1
5.3.26 Comparator characteristics
Table 110. COMP characteristics(1)(2)

Analog supply voltage for

VDDA - 1.58 - 3.6
COMP ON
Comparator input voltage V
VIN - 0 - VDDA
range
VREFINT(3) Scaler input voltage - (3)
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption Scaler bridge disabled(4) - 0.20 0.25

IDDA(SCALER) µA
from VDDA Scaler bridge enabled (5)
- 0.7 1
tSTART_SCALER Scaler startup time - - 130 220
High-speed mode - - 5
Comparator startup time to µs
tSTART reach propagation delay Medium mode - - 25
specification
Ultra-low-power mode - - 80
High-speed mode - 40 100 ns
Propagation delay for
tD(6) 200 mV step with 100 mV Medium mode - 0.5 1
overdrive µs
Ultra-low-power mode - 2 7
Voffset Comparator offset error Full common mode range - ±5 ±20
No hysteresis - 0 -
Low hysteresis - 15 - mV
Vhys Comparator hysteresis
Medium hysteresis - 30 -
High hysteresis - 45 -
Comparator input bias (7)
Ibias - nA
current
DS13543 Rev 2 293/390

352
Table 110. COMP characteristics(1)(2) (continued)

High-speed mode, static - 48 90

High-speed mode, with 50 kHz,
- 50 -
±100 mV overdrive square signal
Medium mode, static - 3 6
Comparator consumption
IDDA(COMP) Medium mode, with 50 kHz, ±100 mV µA
from VDDA - 3.75 -
overdrive square signal
Ultra-low-power mode, static - 0.3 1
Ultra-low-power mode, with 50 kHz,
- 0.65
±100 mV overdrive square signal
2. The input capacitance is negligible compared to the I/O capacitance.
3. Refer to Table 37: Embedded internal voltage reference.
4. No VREFINT division, includes only buffer consumption.
5. VREFINT division, includes resistor bridge and buffer consumption.
7. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 87: I/O static characteristics.
5.3.27 Operational amplifiers characteristics
Table 111. OPAMP characteristics(1)(2)

Analog supply voltage

VDDA - 1.60 - 3.6
range for OPAMP ON
V
Common mode input
CMIR - 0 - VDDA
range
TJ = 30 °C, no load on output,
- - ±3
Normal mode
TJ= 30 °C, no load on output,
- - ±3
Low-power mode
VIOFFSET Input offset voltage mV
All voltages and temperature,
- - ±7
Normal mode
All voltages and temperature,
- - ±11.5
Low-power mode
Input offset voltage drift Normal mode - ±7 -

∆VIOFFSET μV/°C
over temperature Low-power mode - ±15 -
Offset trim step at low
TRIMOFFSETP
common input voltage - - 1.05 1.25
TRIMLPOFFSETP
(0.1 × VDDA)
mV
Offset trim step at high
TRIMOFFSETN
common input voltage - - 1.05 1.25
TRIMLPOFFSETN
(0.9 × VDDA)
294/390 DS13543 Rev 2

Table 111. OPAMP characteristics(1)(2) (continued)

Normal mode - - 500

ILOAD Drive current
Low-power mode - - 100
μA
Normal mode - - 450
ILOAD_PGA Drive current in PGA mode
Low-power mode - - 50
Resistive load (connected Normal mode 3.9 - -

RLOAD kΩ
to VSSA or VDDA) Low-power mode 20 - -
CLOAD Capacitive load - - - 50 pF
Common mode rejection Normal mode - 79 -

CMRR
ratio Low-power mode - 69 -
CLOAD ≤ 50 pF,
Normal
RLOAD ≥ 3.9 kΩ(3), 35 75 - dB
mode
Power supply rejection DC
PSRR
ratio C ≤ 50 pF,
Low-power LOAD
RLOAD ≥ 20 kΩ(3), 32 69 -
mode
DC
Normal mode 0.4 2 3.1
GBW Gain bandwidth product MHz
Low-power mode 0.23 0.5 0.76
Normal
Standard speed 0.5 1 3.2
mode
mode
Low-power (OPAHSM = 0)
0.14 0.25 0.75
Slew rate (from 10% and mode
SR(3) V/µs
90% of output voltage) Normal
1.4 3.2 5.6
mode High speed mode
Low-power (OPAHSM = 1)
0.38 0.82 1.5
mode
Normal mode 72 105 -
AO Open loop gain dB
Low-power mode 77 106 -
Normal mode 54 67 -
φm Phase margin °
Low-power mode 54 65 -
Normal mode - 9 -
GM Gain margin dB
Low-power mode - 17 -
Normal VDDA
ILOAD max or - -
mode - 100
(3)
VOHSAT High saturation voltage RLOAD min,
Low-power Input at V VDDA
DDA - -
mode - 50
mV
Normal
ILOAD max or - - 100
mode
VOLSAT(3) Low saturation voltage RLOAD min,
Low-power Input at 0 V
- - 50
mode
DS13543 Rev 2 295/390

352

CLOAD ≤ 50 pF,
Normal
RLOAD ≥ 3.9 kΩ, - 4 10
mode
Wake-up time from follower config.
tWAKEUP µs
OFF state C ≤ 50 pF,
Low-power LOAD
RLOAD ≥ 20kΩ, - 20 40
mode
follower config.
General purpose input (all (4)
- -
packages except UFBGA)
Dedicated TJ ≤ 75 °C - - 7
Ibias OPAMP input bias current input nA
TJ ≤ 85 °C - - 9
(UFBGA
and TJ ≤ 105 °C - - 18
TFBGA) TJ ≤ 125 °C - - 25
PGA_GAIN[1:0] = 00 - 2 -
PGA_GAIN[1:0] = 01 - 4 -
PGA gain(3) Non-inverting gain value -
PGA_GAIN[1:0] = 10 - 8 -
PGA_GAIN[1:0] = 11 - 16 -
PGA gain = 2 - 80/80 -
R2/R1 internal resistance PGA gain = 4 - 120/40 - kΩ/
Rnetwork values in non-inverting
PGA gain = 8 - 140/20 - kΩ
PGA mode(5)
PGA gain = 16 - 150/10 -
Resistance variation
Delta R - -18 - 18
(R1 or R2) %
PGA gain error PGA gain error - -1 - 1
PGA gain = 2 - GBW/2 -
PGA bandwidth for PGA gain = 4 - GBW/4 -

PGA BW MHz
different non inverting gain PGA gain = 8 - GBW/8 -
PGA gain = 16 - GBW/16 -
Normal At 1 kHz, output
- 220 -
mode loaded with 3.9 kΩ
Low-power At 1 kHz, output
- 350 -
mode loaded with 20 kΩ nV
en Voltage noise density
Normal At 10 kHz, output /√Hz
- 190 -
mode loaded with 3.9 kΩ
Low-power at 10 kHz, output
- 210 -
mode loaded with 20 kΩ
296/390 DS13543 Rev 2


Normal
no load, quiescent - 130 190
mode
mode,
Low-power standard speed
- 40 58
OPAMP consumption from mode
IDDA(OPAMP) µA
VDDA Normal
no load, quiescent - 138 205
mode
mode,
Low-power high-speed mode
- 42 60
mode
2. OPA_RANGE must be set to 1 in OPAMP1_CSR.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 87: I/O static characteristics.
5. R2 is the internal resistance between the OPAMP output and the OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
Figure 44. OPAMP voltage noise density, normal mode, RLOAD = 3.9 kΩ
DS13543 Rev 2 297/390

352
Figure 45. OPAMP voltage noise density, low-power mode, RLOAD = 20 kΩ
5.3.28 Temperature and backup domain supply thresholds monitoring

The temperature and backup domain supply monitoring characteristics are provided
in the technical note STM32U54xxx/STM32U58xxx/STM32U5Axxx/STM32U5Gxxx MCUs
for PCI products (TN1333) (NDA required).
5.3.29 ADF/MDF characteristics

performed under the ambient temperature, fAHB frequency and VDD supply voltage
conditions summarized in Table 33, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 10
• Capacitive load CL = 30 pF
• Measurement points done at 0.5 × VDD level
• I/O compensation cell activated
• HSLV activated when VDD ≤ 2.7 V
• Voltage scaling range 1
Refer to Section 5.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
298/390 DS13543 Rev 2

Table 112. ADF characteristics(1)

Input clock frequency via

fCCKI ADF_CCK[1:0] pin, in - - 25
SLAVE SPI mode
Output clock frequency in
fCCKO - - 25
MASTER SPI mode 1.71 ≤ VDD ≤ 3.6 V MHz
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate in
fSYMB - - 20
Manchester mode
tHCCKI ADF_CCK[1:0] input clock 2×
In SLAVE SPI mode - -
tLCCKI high and low time Tadf_proc_ck(2)
tHCCKO ADF_CCK[1:0] output clock 2×
In MASTER SPI mode - -
tLCCKO high and low time Tadf_proc_ck
tHCCKOLF ADF_CCK[1:0] output clock
In LF_MASTER SPI mode Tadf_proc_ck - -
tLCCKOLF high and low time
Data setup time with respect
tSUCCKI In SLAVE SPI mode: 4.5 - -
to ADF_CCK[1:0] input
ADF_CCK[1:0] configured in input,
Data hold time with respect measured on rising and falling edge
tHDCCKI 0 - - ns
to ADF_CCK[1:0] input
Data setup time with respect In MASTER SPI mode:
tSUCCKO 5.5 - -
to ADF_CCK[1:0] output ADF_CCK[1:0] configured in
Data hold time with respect output, measured on rising and
tHDCCKO falling edge 0 - -
to ADF_CCK[1:0] output
Data setup time with respect In LF_MASTER SPI mode:
tSUCCKOLF 19.5 - -
to ADF_CCK[1:0] output ADF_CCK[1:0] configured in
tHDCCKOLF falling edge 0 - -
to ADF_CCK[1:0] output
2. Tadf_proc_ck is the period of the ADF processing clock.
Figure 46. ADF timing diagram

fCCKI, fCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCCKI, tLCCKO, tHCCKI, tHCCKO,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKOLF tHCCKOLF
ADF_CCK (I/O)
ADF_SDIx (I)
MSv69124V1
DS13543 Rev 2 299/390

352
Table 113. MDF characteristics(1)


fCKI MDF_CKIx pin, in - - 25
SLAVE SPI mode
fCCKI MDF_CCK[1:0] pin, in - - 25
SLAVE SPI mode
1.71 ≤ VDD ≤ 3.6 V MHz
fCCKO - - 25
MASTER SPI mode
fCCKOLF - - 5
LF_MASTER SPI mode
Input symbol rate in
fSYMB - - 20
Manchester mode
MDF_CKIx input clock high 2×
tHCKI tLCKI In SLAVE SPI mode - -
and low time Tmdf_proc_ck(2)
tHCCKI MDF_CCK[1:0] input clock 2×
In SLAVE SPI mode - -
tLCCKI high and low time Tmdf_proc_ck
tHCCKO MDF_CCK[1:0] output clock 2×
In MASTER SPI mode - -
tLCCKO high and low time Tmdf_proc_ck
tHCCKOLF MDF_CCK[1:0] output clock
In LF_MASTER SPI mode Tmdf_proc_ck - -
tLCCKOLF high and low time
Data setup time with respect
tSUCKI 1.5 - -
to MDF_CKIx input In SLAVE SPI mode, measured
Data hold time with respect on rising and falling edge
tHDCKI 0 - -
to MDF_CKIx input
ns
Data setup time with respect In SLAVE SPI mode:
tSUCCKI 1.5 - -
to MDF_CCK[1:0] input MDF_CCK[1:0] configured in
Data hold time with respect input, measured on rising and
tHDCCKI falling edge 0.5 - -
to MDF_CCK[1:0] input
Data setup time with respect In MASTER SPI mode:
tSUCCKO 3.5 - -
to MDF_CCK[1:0] output MDF_CCK[1:0] configured in
tHDCCKO falling edge 1.5 - -
to MDF_CCK[1:0] output
Data setup time with respect In LF_MASTER SPI mode,
tSUCCKOLF 19.5 - -
to MDF_CCK[1:0] output MDF_CCK[1:0] configured in
tHDCCKOLF falling edge 0 - -
to MDF_CCK[1:0] output
2. Tmdf_proc_ck is the period of the MDF processing clock.
300/390 DS13543 Rev 2

Figure 47. MDF timing diagram

tSUCKI tHDCKI tSUCKI tHDCKI
fCKI, fCCKI, FCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCKI, tLCCKI, tHCKI, tHCCKI,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKO tHCCKO
MDF_CKIx (I)
MDF_CCK (I/O)
MDF_SDIx (I)
MSv69125V1
5.3.30 DCMI characteristics

performed under the ambient temperature, fHCLK frequency and VDD supply voltage
summarized in Table 33, with the following configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
Table 114. DCMI characteristics(1)

Symbol Parameter Min Max Unit
- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel clock input - 64 MHz
DPIXEL Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 2.5 -
th(DATA) Data hold time 1 -
tsu(HSYNC)
DCMI_HSYNC and DCMI_VSYNC input setup times 2 - ns
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC and DCMI_VSYNC input hold times 1 -
th(VSYNC)
DS13543 Rev 2 301/390

352
Figure 48. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
5.3.31 PSSI characteristics

• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• Data width: 32 bits
Table 115. PSSI transmit characteristics(1)

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

2.7 V ≤ VDD ≤ 3.6 V - 64(2)
PSSI_PDCK PSSI clock input MHz
1.71 V ≤ VDD ≤ 3.6 V - 47(2)
DPIXEL PSSI clock input duty cycle - 30 70 %
302/390 DS13543 Rev 2

Table 115. PSSI transmit characteristics(1) (continued)

2.7 V ≤ VDD ≤ 3.6 V - 14

tOV(DATA) Data output valid time
1.71 V ≤ VDD ≤ 3.6 V - 21
tOH(DATA) Data output hold time 7 -
tOV(DE) DE output valid time - 13.5 ns
tOH(DE) DE output hold time 1.71 V ≤ VDD ≤ 3.6 V 6 -
tSU(RDY) RDY input setup time 0 -
tH(RDY) RDY input hold time 0 -
2. This maximal frequency does not consider receiver setup and hold timings.
Figure 49. PSSI transmit timing diagram

tc(PDCK)
tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK
CKPOL=0
(input)
CKPOL=1
tv(DATA) tho(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
tv(DE) tho(DE)
DEPOL=0
PSSI_DE
(output)
DEPOL=1
ts(RDY) th(RDY)
PSSI_RDY
RDYPOL=0
(input)
RDYPOL=1
MSv63437V1
Table 116. PSSI receive characteristics(1)

- Frequency ratio DCMI_PDCK/fHCLK - - 0.4 -

PSSI_PDCK PSSI clock input 1.71 V ≤ VDD ≤ 3.6 V - 64 MHz
DPIXEL PSSI clock input duty cycle - 30 70 %
DS13543 Rev 2 303/390

352
Table 116. PSSI receive characteristics(1) (continued)

tSU(DATA) Data input setup time 2 -

tH(DATA) Data input hold time 1.5 -
tSU(DE) DE input setup time 1 -
1.71 V ≤ VDD ≤ 3.6 V ns
tH(DE) DE input hold time 2 -
tOV(RDY) RDY output valid time - 13
tOH(RDY) RDY output hold time 6 -
Figure 50. PSSI receive timing diagram
tc(PDCK)
tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK
CKPOL=0
(input)
CKPOL=1
ts(DATA)
th(DATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
ts(DE)
th(DE)
DEPOL=0
PSSI_DE
(input)
DEPOL=1
tv(RDY) tho(RDY)
PSSI_RDY
RDYPOL=0
(output)
RDYPOL=1
MSv63436V1
304/390 DS13543 Rev 2

5.3.32 LCD-TFT controller (LTDC) characteristics

• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
Table 117. LTDC characteristics(1)

2.7 V ≤ VDD ≤ 3.6 V, CL = 20 pF 116

LTDC clock output
fCLK 2.7 V ≤ VDD ≤ 3.6 V - 100 MHz
frequency
1.71 V ≤ VDD ≤ 3.6 V 66.5
DCLK LTDC clock output duty cycle 45 55 %
tW(CLKH)
Clock High time, low time tW(CLK)/2 - 0.5 tW(CLK)/2 + 0.5
tW(CLKL)
Data output valid 2.7 V ≤ VDD ≤ 3.6 V 2.5

tV(DATA) -
time 1.71 V ≤ VDD ≤ 3.6 V 7.5
tH(DATA) Data output hold time 0.5 -
ns
tV(HSYNC)
tV(VSYNC) HSYNC/VSYNC/DE output valid time - 3
tV(DE)
tH(HSYNC)
tH(VSYNC) HSYNC/VSYNC/DE output hold time 1.5 -
tH(DE)
DS13543 Rev 2 305/390

352
Figure 51. LTDC horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) th(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)
HSYNC Horizontal Active width Horizontal

width back porch back porch
One line
MS32749V2
Figure 52. LTDC vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC) th(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
VSYNC Vertical Active width Vertical

width back porch back porch
One frame
MS32750V2
306/390 DS13543 Rev 2

5.3.33 MIPI D-PHY characteristics

The parameters given in the table below are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 33.
Table 118. MIPI D-PHY characteristics(1)

High-speed input/output characteristics

UINST(2) UI instantaneous 2 - 12.5 ns
VCMTX High-speed transmit common mode voltage 150 200 250
|∆VCMTX| VCMTX mismatch when output is Differential-1 or Differential-0 - - 5
|VOD| High-speed transmit differential voltage 140 200 270 mV
|∆VOD| VOD mismatch when output is Differential-1 or Differential-0 - - 14
VOHHS High-speed output high voltage - - 360
ZOS Single-ended output impedance 40 50 62.5 Ω
∆ZOS Single-ended output impedance mismatch - - 10 %
tHSr, tHSf(2) 20%-80% rise and fall time 100 - 0.3 × UI(3) ps
Low-power receiver input characteristics
VIL Logic 0 input voltage (not in ULP state) - - 550
VIL-ULPS Logic 0 input voltage in ULP state - - 300
mV
VIH Input high-level voltage 880 - -
Vhys(2) Voltage hysteresis 25 - -
Low-power emitter output characteristics
VOL Output low level voltage -50 - 50 mV
VOH Output high level voltage 1.1 1.2 1.2 V
ZOLP Output impedance of LP transmitter 110 - - Ω
tLPr, tLPf(2) 15%-85% rise and fall time - - 25 ns
Low-power contention detector characteristics
VILCD Logic 0 contention threshold - - 200
mV
VIHCD Logic 1 contention threshold 450 - -
1. Evaluated by characterization, not tested in production unless otherwise specified.
3. UI (unit interval) equals to the duration of any HS state on the clock lane.
DS13543 Rev 2 307/390

352
Table 119. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1)

TLPX Transmitted length of any LP state period 50 - -

Time that the transmitter drives the clock lane LP-00
TCLK-PREPARE line state immediately before the HS-0 line state, 38 - 95
ns
starting the HS transmission
TCLK-PREPARE TCLK-PREPARE + time that the transmitter drives the
300 - -
+ TCLK-ZERO HS-0 state prior to starting the clock
Time that the HS clock must be driven by the
TCLK-PRE transmitter prior to any associated data lane beginning 8 - - UI(2)
the transition from LP to HS mode
Time that the transmitter continues to send HS clock
TCLK-POST after the last associated data lane transitioned to 62 + 52 × UI - -
LP mode
Time that the transmitter drives the HS-0 state after
TCLK-TRAIL 60 - -
the last payload clock bit of an HS transmission burst
Time that the transmitter drives the data lane LP-00
THS-PREPARE line state immediately before the HS-0 line state 40 + 4 × UI - 85 + 6 × UI
starting the HS transmission
THS-PREPARE THS-PREPARE + time that the transmitter drives the
145 + 10 × UI - -
+ THS-ZERO HS-0 state prior to transmitting the sync sequence ns
Time that the transmitter drives the flipped differential Max
THS-TRAIL state after last payload data bit of a HS transmission (n × 8 × UI, - -
burst 60 + n × 4 × UI)
Time that the transmitter drives LP-11 following
THS-EXIT 100 - -
a HS burst
TREOT 30%-85% rise and fall time - - 35(3)
Transmitted time interval from the start of THS-TRAIL or
105 + n ×
TEOT TCLK-TRAIL, to the start of the LP-11 state following a - -
12 × UI
HS burst
2. UI (unit interval) equals to the duration of any HS state on the clock lane.
3. For VDD above 3 V, this parameter may be degraded in the 55°C to 125°C range. For VDD = 1.8 V, this parameter may be
degraded in the 25°C to 125°C range.
308/390 DS13543 Rev 2

Figure 53. MIPI D-PHY HS/LP clock lane transition
TCLK-POST TEOT
Clock VIL
Lane
TCLK-TRAIL THS-EXIT TLPX TCLK-PREPARE TCLK-ZERO TCLK-PRE TLPX THS-PREPARE
Data VIL
Lane
MS38282V1
Figure 54. MIPI D-PHY HS/LP data lane transition
Clock
Lane
TLPX THS-PREPARE THS-ZERO
Data
VIL
Lane
TREOT
LP-11 LP-01 LP-00 TEOT
THS-TRAIL THS-EXIT
MS38283V1
Table 120. DSI-PLL characteristics(1)

Symbol Parameter Condition Min Typ Max Unit
fPLL_IN PLL input clock - 4 - 48

fPLL_INFIN PFD input clock - 2 - 48
MHz
fPLL_OUT PLL multiplier output clock - 0.976 - 1000
fVCO_OUT PLL VCO output - 500 - 1000
tLOCK PLL lock time - - - 400 µs
fVCO_OUT = 500 MHz - 0.25 0.27
PLL power consumption on VDD11DSI,
IDD_PLL fVCO_OUT = 600 MHz - 0.29 0.31
for PFD input clock = 2 MHz
fVCO_OUT = 1000 MHz - 0.51 0.53
mA
fVCO_OUT = 500 MHz - 0.7 0.95
PLL power consumption on VDD11DSI,
IDD_PLL fVCO_OUT = 600 MHz - 0.76 1.01
for PFD input clock = 48 MHz
fVCO_OUT = 1000 MHz - 1 1.22
DS13543 Rev 2 309/390

352
Table 121. DSI current consumption characteristics on VDDDSI(1)

Ultra-low-power mode
- 194 208 µA
(PLL OFF)
DSI system (Host, PLL and D-PHY) Stop state - 1 data lane
IDD_DSI - 2.74 3.2
current consumption on VDDDSI (PLL OFF)
Stop state - 2 data lanes
- 4.08 4.8
(PLL OFF)
10 MHz escape clock -
- 4.32 4.8
1 data lane (PLL OFF)
- 5.65 6.4
DSI system current consumption on 2 data lanes (PLL OFF)
IDD_DSILP
VDDDSI in LP mode communication(2) 20 MHz escape clock -
- 5.94 6.6
- 7.27 8.2
2 data lanes (PLL OFF) mA
300 Mbit/s - 1 data lane
- 2.98 3.1
(PLL ON)
300 Mbit/s - 2 data lanes
DSI system (Host, PLL and D-PHY) - 4.33 4.5
(PLL ON)
current consumption on VDDDSI
in HS mode communication(3) 500 Mbit/s - 1 data lane
- 3.21 3.4
IDD_DSIHS (PLL ON)
- 4.54 4.8
(PLL ON)
DSI system (Host, PLL and D-PHY)
current consumption on VDDDSI - 4.56 4.8
(PLL ON)
in HS mode with CLK like payload
2. Values based on an average traffic in LP command mode.
3. Values based on an average traffic (3/4 HS traffic and 1/4 LP) in Video mode.
Table 122. DSI current consumption characteristics on VDD11DSI(1)

Ultra-low--power mode
- 7.7 48 µA
(PLL OFF)
DSI system (Host, PLL and D-PHY) Stop state - 1 data lane
IDD11_DSI - 0.56 1.1
current consumption on VDD11DSI (PLL OFF)
mA
Stop state - 2 data lanes
- 0.83 1.7
(PLL OFF)
310/390 DS13543 Rev 2

Table 122. DSI current consumption characteristics on VDD11DSI(1) (continued)


- 0.56 1.2
- 0.83 1.7
DSI system current consumption on 2 data lanes (PLL OFF)
IDD11_DSILP
VDD11DSI in LP mode communication(2) 20 MHz escape clock -
- 0.56 1.2
20 MHz escape clock - 2
- 0.83 1.7
lanes (PLL OFF)
300 Mbit/s - 1 data lane
- 6.45 8.5
(PLL ON) mA
DSI system (Host, PLL and D-PHY) - 7.8 10.3
(PLL ON)
current consumption on VDD11DSI
in HS mode communication(3) 500 Mbit/s - 1 data lane
- 7.4 9.7
IDD11_DSIHS (PLL ON)
- 8.8 11.5
(PLL ON)
DSI system (Host, PLL and D-PHY)
current consumption on VDD11DSI - 10.1 13.3
(PLL ON)
in HS mode with CLK like payload
2. Values based on an average traffic in LP command mode.
3. Values based on an average traffic (3/4 HS traffic and 1/4 LP) in video mode.
5.3.34 Timer characteristics

The parameters given in the following tables are specified by design, not tested in
production.
Refer to Section 5.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 123. TIMx(1) characteristics

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 160 MHz 6.25 - ns
Timer external clock frequency on - 0 fTIMxCLK/2

fEXT MHz
CH1 to CH4 fTIMxCLK = 160 MHz 0 80
TIMx (except TIM2/3/4/5) - 16
ResTIM Timer resolution bit
TIM2/3/4/5 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 160 MHz 0.007 409.6 µs
DS13543 Rev 2 311/390

352
Table 123. TIMx(1) characteristics (continued)

Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 160 MHz - 26.843 s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Table 124. IWDG min/max timeout period at 32 kHz (LSI)(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock, so that there is always a full
RC period of uncertainty.
Table 125. WWDG min/max timeout value at 160 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.025 1.638
2 1 0.051 3.276
4 2 0.102 6.553
8 3 0.204 13.107
ms
16 4 0.409 26.214
32 5 0.819 52.428
46 6 1.177 75.366
128 7 3.276 209.715
5.3.35 FSMC characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests
• Capacitive load CL = 30 pF, unless otherwise specified
312/390 DS13543 Rev 2

Refer to Section 5.3.15: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings

Figure 55 to Figure 58 represent asynchronous waveforms and Table 126 to Table 133
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• AddressSetupTime (ADDSET) = 0x1
• AddressHoldTime (ADDHLD) = 0x1
• ByteLaneSetup (NBLSET) = 0x1
• DataSetupTime (DATAST) = 0x1 (except for asynchronous NWAIT mode,
DataSetupTime = 0x5)
• DataHoldTime (DATAHLD) = 0x1 (0x0 for write operation)
• BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
DS13543 Rev 2 313/390

352
Table 126. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 3 × tHCLK - 1 3 × tHCLK + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 5
tw(NOE) FMC_NOE low time 2 × tHCLK - 1 2 × tHCLK + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time THCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
th(A_NOE) Address hold time after FMC_NOE high 2 × tHCLK - 1 -
ns
tsu(Data_NE) Data to FMC_NEx high setup time tHCLK + 15 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 15 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 1.5
tw(NADV) FMC_NADV low time - THCLK + 1
Table 127. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1)


tw(NOE) FMC_NWE low time 7 × tHCLK - 1 7 × tHCLK + 1
tw(NWAIT) FMC_NWAIT(2) low time tHCLK - ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × tHCLK + 9.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × tHCLK + 10 -
2. NWAIT pulse is equal to one HCLK cycle.
314/390 DS13543 Rev 2

Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
Table 128. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)


tv(NWE_NE) FMC_NEx low to FMC_NWE low tHCLK - 1 tHCLK
tw(NWE) FMC_NWE low time tHCLK - 0.5 tHCLK + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time tHCLK -
th(A_NWE) Address hold time after FMC_NWE high tHCLK - 0.5 -
ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high tHCLK - 0.5 -
tv(Data_NE) FMC_NEx low to Data valid - tHCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high tHCLK -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 2
tw(NADV) FMC_NADV low time - tHCLK + 1
DS13543 Rev 2 315/390

352
Table 129. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)


tw(NWE) FMC_NWE low time 6 × tHCLK - 1 6 × tHCLK + 1
ns
(2)
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × tHCLK + 13 -
Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
316/390 DS13543 Rev 2

Table 130. Asynchronous multiplexed PSRAM/NOR read timings(1)


tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 5
tw(NOE) FMC_NOE low time 2 × tHCLK - 0.5 2 × tHCLK + 0.5
th(NE_NOE) FMC_NOE high to FMC_NE high hold time tHCLK -
tv(A_NE) FMC_NEx low to FMC_A valid - 1.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1.5
tw(NADV) FMC_NADV low time tHCLK - 0.5 tHCLK + 1 ns
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) tHCLK - 4 -
th(A_NOE) Address hold time after FMC_NOE high tHCLK - 1 -
tsu(Data_NE) Data to FMC_NEx high setup time tHCLK + 15 -
tsu(Data_NOE) Data to FMC_NOE high setup time 15 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 131. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)


tw(NOE) FMC_NOE low time 7 × tHCLK - 1 7 × tHCLK + 1
ns
tsu(NWAIT_NE) FMC_NWAIT(2) valid before FMC_NEx high 4 × tHCLK + 9.5 -
DS13543 Rev 2 317/390

352
Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)
FMC_ NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)
FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
Table 132. Asynchronous multiplexed PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 3 × tHCLK - 1 3 × tHCLK

tv(NWE_NE) FMC_NEx low to FMC_NWE low tHCLK - 1 tHCLK
tw(NWE) FMC_NWE low time 2 × tHCLK - 0.5 2 × tHCLK + 1
th(NE_NWE) FMC_NWE high to FMC_NE high hold time tHCLK -
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 2
tw(NADV) FMC_NADV low time tHCLK - 0.5 tHCLK + 1 ns
th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) tHCLK - 4.5 -
th(A_NWE) Address hold time after FMC_NWE high tHCLK - 0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high tHCLK - 0.5 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
tv(Data_NADV) FMC_NADV high to Data valid - tHCLK + 2
th(Data_NWE) Data hold time after FMC_NWE high tHCLK -
318/390 DS13543 Rev 2

Table 133. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)


tw(NWE) FMC_NWE low time 6 × tHCLK - 1 6 × tHCLK + 1
ns
(2)
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5 × tHCLK + 13 -
Synchronous waveforms and timings

Figure 59 to Figure 62 represent synchronous waveforms and Table 134 to Table 137
provide the corresponding timings. The results shown in these tables are obtained with the
following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
• Maximum FMC_CLK = 80 MHz for 2.7 V ≤ VDD ≤ 3.6 V, with CL = 15pF and
with CL = 20 pF
• Maximum FMC_CLK = 80 MHz for 1.71 V ≤ VDD ≤ 1.9 V with CL = 15pF and
with CL = 20 pF
DS13543 Rev 2 319/390

352
Figure 59. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
Table 134. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FMC_CLK period 2 × tHCLK - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - 3
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x = 0..2) tHCLK - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5 ns
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) tHCLK - 0.5 -
320/390 DS13543 Rev 2

Table 134. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued)

td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5

td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tHCLK + 1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
ns
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 4 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 -
2. Clock ratio R = (HCLK period /FMC_CLK period).
Figure 60. Synchronous multiplexed PSRAM write timings
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DS13543 Rev 2 321/390

352
Table 135. Synchronous multiplexed PSRAM write timings(1)

tw(CLK) FMC_CLK period, 2.7 V ≤ VDD ≤ 3.6 V 2 × tHCLK - 0.5 -

td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0..2) tHCLK + 1.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) tHCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5
ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high tHCLK + 1 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tHCLK + 0.5 -
322/390 DS13543 Rev 2

Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK)
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
(1)
Table 136. Synchronous non-multiplexed NOR/PSRAM read timings

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 3
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) tHCLK - 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2.5
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=0…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=0…25) tHCLK - 0.5 - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tHCLK + 1 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 4 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 4 -
DS13543 Rev 2 323/390

352
Figure 62. Synchronous non-multiplexed PSRAM write timings

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Table 137. Synchronous non-multiplexed PSRAM write timings(1)


td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x = 0..2) tHCLK + 1.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 2
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - 3
ns
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) tHCLK -
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 2.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high tHCLK + 1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tHCLK + 0.5 -
324/390 DS13543 Rev 2

Table 137. Synchronous non-multiplexed PSRAM write timings(1) (continued)


ns
NAND controller waveforms and timings

Figure 63 to Figure 66 represent synchronous waveforms, and Table 138/Table 139 provide
the corresponding timings. The results shown in these tables are obtained with the following
FMC configuration:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
Figure 63. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(NCE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MSv38003V1
DS13543 Rev 2 325/390

352
Figure 64. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MSv38004V1
Figure 65. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MSv38005V1
Figure 66. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(NCE-NWE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MSv38006V1
326/390 DS13543 Rev 2

Table 138. Switching characteristics for NAND Flash read cycles(1)

tw(N0E) FMC_NOE low width 4 × tHCLK - 0.5 4 × tHCLK + 0.5

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 13 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3 × tHCLK + 0.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4 × tHCLK - 1 -
Table 139. Switching characteristics for NAND Flash write cycles(1)

tw(NWE) FMC_NWE low width 4 × tHCLK - 0.5 4 × tHCLK + 0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2 × tHCLK + 1 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5 × tHCLK - 5 -
td(ALE_NWE) FMC_ALE valid before FMC_NWE low - 3 × tHCLK + 0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2 × tHCLK - 0.5 -
5.3.36 OCTOSPI characteristics

Unless otherwise specified, the parameters given in Table 140 toTable 142 are derived from
tests performed under the ambient temperature, fAHB frequency and VDD supply voltage
• Delay block enabled for DTR (with DQS)/HyperBus
• Voltage scaling range 1 unless otherwise specified
DS13543 Rev 2 327/390

352
Table 140. OCTOSPI characteristics in SDR mode(1)(2)(3)

1.71 V ≤ VDD ≤ 3.6 V

Voltage range 1 - - 93
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range 1 - - 100 MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
CL = 15 pF
tw(CLKH) OCTOSPI clock high t(CLK)/2 - 0.5 - t(CLK)/2
PRESCALER[7:0] = n
and low time
tw(CLKL) (even division) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2
(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock high -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1)
and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1)
Voltage range 1 2.5 - -
ts(IN) Data input setup time ns
Voltage range 4 6 - -
th(IN) Data input hold time
Voltage range 1 - 0.5 1
tv(OUT) Data output valid time
Voltage range 4 - 1.5 2.5
Voltage range 1 -0.5 - -
th(OUT) Data output hold time
Voltage range 4 -0.25 - -
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.
Table 141. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3)

1.71 V ≤ VDD ≤ 3.6 V

Voltage range 1 - - 93(4)
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range1 - - 100(4) MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4, - - 25(4)
CL = 15 pF
328/390 DS13543 Rev 2

Table 141. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)(3) (continued)

tw(CLKH) OCTOSPI clock t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5

PRESCALER[7:0] = n
high and low time
tw(CLKL) (even division) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
high and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1) + 0.5
tsr(IN) Data input setup Voltage range 1 3.25 - -

tsf(IN) time Voltage range 4 3.75 - -
thr(IN) Data input hold Voltage range 1 1 - -

thf(IN) time Voltage range 4 1.5 - - ns
Data output valid Voltage range 1 - 6 9.25

time, DHQC = 0 Voltage range 4 - 13.25 19.75
tvr(OUT)
tvf(OUT) Voltage range 1
Data output valid
All prescaler values - t(CLK)/4 + 0.75 t(CLK)/4 + 1.5
time, DHQC = 1
(except 0)
Data output hold Voltage range 1 4 - -

time DHQC = 0 Voltage range 4 8 - -
thr(OUT)
thf(OUT) Voltage range 1
Data output hold
All prescaler values t(CLK)/4 - 0.5 - -
time DHQC = 1
(except 0)
2. Measured values in this table apply to Octo- and Quad-SPI data modes.
3. Delay block bypassed.
4. Activating DHQC is mandatory to reach this frequency.
Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2)

1.71 V ≤ VDD ≤ 3.6 V

Voltage range 1 - - 93(3)(4)
CL = 15 pF
2.7 V ≤ VDD ≤ 3.6 V
OCTOSPI clock
f(CLK) Voltage range 1 - - 100(3)(4) MHz
frequency
CL = 15 pF
1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4 - - 25(4)
CL = 15 pF
tw(CLKH) OCTOSPI clock t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
high and low time ns
tw(CLKL) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(even division)
DS13543 Rev 2 329/390

352
Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus(1)(2) (continued)

(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) OCTOSPI clock -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
high and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
tw(CLKL) (odd division) -
/(n+1) - 0.5 /(n+1) + 0.5 ns
tv(CLK) Clock valid time - - - t(CLK) + 2

th(CLK) Clock hold time - t(CLK)/2 - 0.5 - -
CLK, NCLK
VODr(CLK)
(5) crossing level on VDD = 1.8 V 925 - 1040
CLK rising edge
mV
CLK, NCLK
VODf(CLK)
(5) crossing level on VDD = 1.8 V 870 - 1105
CLK falling edge
Chip select high
tw(CS) - 3 × t(CLK) - -
time
Data input valid
tv(DQ) - 0 - -
time
Data strobe input
tv(DS) - 0 - -
valid time
Data strobe input
th(DS) - 0 - -
hold time
Data strobe output
tv(RWDS) - - - 3 × t(CLK)
valid time
tsr(DQ) Data input setup Voltage range 1 -0.25 - -

tsf(DQ) time Voltage range 4 0 - -
ns
thr(DQ) Data input hold Voltage range 1 1.25 - -
thf(DQ) time Voltage range 4 1.75 - -
Data output valid Voltage range 1 - 6 9.5

time DHQC = 0 Voltage range 4 - 13 19.5
tvr(OUT)
tvf(OUT) Voltage range 1
Data output valid
All prescaler values - t(CLK)/4 + 0.5 t(CLK)/4 + 1.25
time DHQC = 1
(except 0)
thr(OUT) Data output hold Voltage range 1 4 - -

thf(OUT) time DHQC = 0 Voltage range 4 7.75 - -
Voltage range 1
Data output hold
thr(OUT) All prescaler values t(CLK)/4 - 0.5 - -
time DHQC = 1
(except 0)
2. Delay block activated.
3. Maximum frequency values are given for a RWDS to DQ skew of maximum ±1.0 ns.
4. Activating DHQC is mandatory to reach this frequency.
5. Crossing results are in line with specification, except for PA3/PB5 CLK that exceed slightly the specification.
330/390 DS13543 Rev 2

Figure 67. OCTOSPI timing diagram - SDR mode
tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V3
Figure 68. OCTOSPI timing diagram - DTR mode

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input D0 D1 D2 D3 D4 D5
MSv36879V4
Figure 69. OCTOSPI HyperBus clock

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)
NCLK
VOD(CLK)
CLK
MSv47732V3
DS13543 Rev 2 331/390

352
Figure 70. OCTOSPI HyperBus read

tw(CS)
NCS
tv(CLK) t ACC= Initial access th(CLK)
CLK, NCLK
tv(RWDS) tv(DS) th(DS)
RWDS
tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

DQ[7:0] A B A B
Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv47733V3
Figure 71. OCTOSPI HyperBus read with double latency

NCS
tRWR=Read/write recovery Additional latency tACC = Access
CLK, NCLK
tCKDS
RWDS High = 2x latency count
Low = 1x latency count
RWDS and data
are edge aligned
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
A B A B
Command address Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS. MSv49351V3
Figure 72. OCTOSPI HyperBus write

tw(CS)
NCS
Read write recovery Access latency

tv(CLK) th(CLK)
CLK, NCLK
tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

RWDS
Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B
Command address Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
MSv47734V3
332/390 DS13543 Rev 2

5.3.37 HSPI characteristics

performed under the ambient temperature, fAHB frequency and VDD supply voltage
• Voltage scaling range 1 unless otherwise specified
Table 143. HSPI characteristics in SDR mode(1)

1.71 V ≤ VDD ≤ 3.6 V

CL = 15 pF
f(CLK) HSPI clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V
CL = 15 pF
tw(CLKH) HSPI clock high and low PRESCALER[7:0] = n t(CLK)/2 - 0.5 - t(CLK)/2
t time (even division) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2
w(CLKL)
(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) -
HSPI clock high and low PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1)
time (odd division) (n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
tw(CLKL) -
/(n+1) - 0.5 /(n+1)
ts(IN) Data input setup time
Voltage range 4 2.5 - - ns
th(IN) Data input hold time
Voltage range 1 - 0.5 1
tv(OUT) Data output valid time
Voltage range 4 - 1.5 2.5
th(OUT) Data output hold time
DS13543 Rev 2 333/390

352
Table 144. HSPI characteristics in DTR mode (no DQS)(1)

1.71 V ≤ VDD ≤ 3.6 V

HSPI clock CL = 15 pF
f(CLK) MHz
frequency 1.71 V ≤ VDD ≤ 3.6 V
Voltage range 4, - - 25
CL = 15 pF
tw(CLKH) HSPI clock high t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
and low time
tw(CLKL) (even division) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) HSPI clock high -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
t (odd division) -
w(CLKL) /(n+1) - 0.5 /(n+1) + 0.5
tsr(IN) Data input setup Voltage range 1 2 - -

tsf(IN) time Voltage range 4 3 - -
thr(IN) Data input hold Voltage range 1 0.5 - -

thf(IN) time Voltage range 4 1 - - ns
Voltage range 1 - t(CLK)/4 + 0.5 t(CLK)/4 + 1.5
Voltage range 1
tvr(OUT) Data output valid
(prescaler = 0) with - 5.5 6.5
tvf(OUT) time
F(CLK) < 50 MHz
Voltage range 4 - t(CLK)/4 + 0.75 t(CLK)/4 + 3
Voltage range 1 t(CLK)/4 - 1 - -
Voltage range 1
thr(OUT) Data output hold
(prescaler = 0) with 4.75 - -
thf(OUT) time
F(CLK) < 50 MHz
Table 145. HSPI characteristics in DTR mode (with DQS)/HyperBus(1)

1.71 V ≤ VDD ≤ 3.6 V

HSPI clock CL = 15 pF
f(CLK) MHz
frequency 1.71 V ≤ VDD ≤ 3.6 V
CL = 15 pF
tw(CLKH) HSPI clock high t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
PRESCALER[7:0] = n
and low time ns
tw(CLKL) (n = 0, 1, 3, 5,..255) t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5
(even division)
334/390 DS13543 Rev 2

Table 145. HSPI characteristics in DTR mode (with DQS)/HyperBus(1) (continued)

(n/2) × t(CLK) (n/2) × t(CLK)

tw(CLKH) HSPI clock high -
PRESCALER[7:0] = n /(n+1) - 0.5 /(n+1) + 0.5
and low time
(n = 2, 4, 6,..254) ((n/2)+1) × t(CLK) ((n/2)+1) × t(CLK)
tw(CLKL) (odd division) -
/(n+1) - 0.5 /(n+1) + 0.5 ns
tv(CLK) Clock valid time - - - t(CLK) - 1.5

th(CLK) Clock hold time - t(CLK)/2 + 1 - -
CLK, NCLK
VODr(CLK) crossing level on VDD = 1.8 V 860 - 890
CLK rising edge
mV
CLK, NCLK
VODf(CLK) crossing level on VDD = 1.8 V 720 - 740
CLK falling edge
Data input valid
tv(DQ) - 0 - -
time
Data strobe input
tv(DS) - 0 - -
valid time
Data strobe input
th(DS) - 0 - -
hold time
Data strobe output
tv(RWDS) - - - t(CLK)
valid time
Voltage range 1 1 - t(CLK)/4 - -
Voltage Range 1,
tsr(DQ) Data input setup
(prescaler = 0) with - 6.5 - -
tsf(DQ) time
F(CLK) < 50 MHz
Voltage range 1 0.5 + t(CLK)/4 - -
ns
Voltage Range 1,
thr(DQ) Data input hold
(prescaler = 0) with 6 - -
thf(DQ) time
F(CLK) < 50 MHz
Voltage range 1 - t(CLK)/4 + 0.5 t(CLK)/4 + 1.5
Voltage Range 1,
tvr(OUT) Data output valid
(prescaler = 0) with - 5 6.5
tvf(OUT) time
F(CLK) < 50 MHz
Voltage range 4 - t(CLK)/4 + 0.75 t(CLK)/4 + 3
Voltage Range 1,
thr(OUT) Data output hold
(prescaler = 0) with 4.75 - -
thf(OUT) time
F(CLK) < 50 MHz
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352
Figure 73. HSPI timing diagram - SDR mode
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V3
Figure 74. HSPI timing diagram - DTR mode
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input D0 D1 D2 D3 D4 D5
MSv36879V4
Figure 75. HSPI HyperBus clock

t(CLK) tw(CLKH) tw(CLKL)
t(NCLK) tw(NCLKL) tw(NCLKH)
CLK
VOD(CLK)
NCLK
MSv69140V2
336/390 DS13543 Rev 2

Figure 76. HSPI HyperBus read
NCS
tv(CLK) tACC = initial access th(CLK)
CLK, NCLK
DQS0
tv(OUT) th(OUT) Latency count tv(DQ)
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

IO[7:0] A B A B

Command address
DQS1
tv(DQ)
Dn Dn Dn+1 Dn+1
IO[15:8] A B A B
MSv69141V2
Figure 77. HSPI HyperBus write

NCS
Read write recovery Access latency

tv(CLK) th(CLK)
CLK, NCLK
tv(RWDS) High = 2x latency count tv(OUT) th(OUT)

DQS[1:0]
Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
IO[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B
Command address
tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
IO[15:8] A B A B
MSv69142V2
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5.3.38 SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 146 and Table 147 are derived
from tests performed under the ambient temperature, fAHB frequency and VDD supply
voltage conditions summarized in Table 33, with the following configuration:
• Capacitive load CL = 30 pF, unless otherwise specified
characteristics.
Table 146. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2)

fPP Clock frequency in data transfer mode - 0 - 100(3) MHz

tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes
tISU Input setup time HS - 3.5 - -

tIH Input hold time HS - 1.5 - - ns
tIDW(5) Input valid window (variable window) - 4.5 - -
CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes
7.5/8.5
tOV Output valid time HS - - 6.5 (6)
ns
tOH Output hold time HS - 3 - -
CMD, D inputs (referenced to CK) in SD default mode
tISU Input setup time SD - 3.5 - -

ns
tIH Input hold time SD - 1.5 - -
CMD, D outputs (referenced to CK) in SD default mode
tOV Output valid default time SD - - 1.5 3

ns
tOH Output hold default time SD - 0.5 - -
2. In SD/e.MMC DDR mode, the clock OSPEEDRy[1:0] is set to 01 while data OSPEEDRy[1:0] remains at 10.
3. With capacitive load CL = 20 pF.
4. For SD 1.8 V support, an external voltage converter is needed.
5. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.
6. tOV = 7.5 ns for SDMMC1 and tOV = 8.5 ns for SDMMC2.
338/390 DS13543 Rev 2

Table 147. e•MMC characteristics (VDD = 1.71 V to 1.9 V)(1)(2)

All modes
- - 84
fPP Clock frequency in data transfer mode except DDR MHz
(3)
DDR mode - - 40
tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in e•MMC mode
tISU Input setup time HS - 3 - -

tIH Input hold time HS - 2 - - ns
tIDW(4) Input valid window (variable window) - 4 - -
CMD, D outputs (referenced to CK) in e•MMC mode
tOV Output valid time HS - - 12 14/16(5)

ns
tOH Output hold time HS - 6 - -
2. With capacitive load CL = 20 pF.
3. For DDR mode, the maximum frequency is 40 MHz and HSLV must be OFF.
4. Minimum window of time where the data needs to be stable for proper sampling in tuning mode.
5. tOV = 14 ns for SDMMC1 and tOV = 16 ns for SDMMC2.
Figure 78. SD high-speed mode

tC(CK)
tW(CKH) tW(CKL)
CK
tOH
tOV
D, CMD output
tIH
tISU
D, CMD input
MSv69709V1
Figure 79. SD default mode
CK
tOV tOH
D, CMD output MSv69710V1
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352
Figure 80. SDMMC DDR mode
D input Valid data Valid data
tISU tIH tISU tIH
tW(CKH)
CK
tW(CKL)
tOV tOV
tOH tOH
D output Valid data Valid data
MSv69158V1
5.3.39 Delay block characteristics

Table 148. Delay block characteristics(1)

tinit Initial delay - 900 1300 2100

ps
t∆ Unit delay - 34 41 51
5.3.40 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bitrate up to 100 Kbit/s
• Fast-mode (Fm): with a bitrate up to 400 Kbit/s
• Fast-mode Plus (Fm+): with a bitrate up to 1 Mbit/s
The I2C timings requirements are specified by design, not tested in production, when the
I2C peripheral is properly configured (refer to the product reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low-level output-current maximum requirement. Refer to Section 5.3.15: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics.
340/390 DS13543 Rev 2

Table 149. I2C analog filter characteristics(1)

tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 115(3) ns
2. Spikes with widths below tAF min are filtered.
3. Spikes with width above tAF max are not filtered.
5.3.41 USART characteristics

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
• Capacitive load CL = 30pF
function characteristics (NSS, CK, TX, RX for USART).
Table 150. USART characteristics(1)

Master mode, 1.71 V ≤ VDDIOX ≤ 3.6 V - - 20
USART clock Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - - 53

fCK MHz
frequency Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - - 27
Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - - 30
tsu(NSS) NSS setup time Slave mode Tker(2) + 2 - -
th(NSS) NSS hold time Slave mode 2 - -
tw(CKH) CK high and
Master mode 1/fCK / 2 - 1 1/fCK / 2 1/fCK / 2 + 1
tw(CKL) low time
tsu(RX) Data input Master mode 15 - -
tsu(TX) setup time Slave mode 2.5 - -
th(RX) Data input hold Master mode 4 - - ns
th(RX) time Slave mode 1 - -
Slave mode, 2.7 V ≤ VDDIOX ≤ 3.6 V - 13 16.5
tv(TX) Data output
Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V - 13 18.5
valid time
tv(TX) Master mode - 2.5 6.5
th(TX) Data output Slave mode 8.5 - -
th(TX) hold time Master mode 0.5 - -
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352
2. Tker is the usart_ker_ck_pres clock period.
Figure 81. USART timing diagram in master mode
1/fCK
tw(CKH)
CPHA=0
CK output
CPOL=0
CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CPOL=0
CK output
CPHA=1
CPOL=1
tsu(RX) tw(CKH)
tw(CKL)
RX input MSB IN BIT6 IN LSB IN
TX output MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX) MSv65386V5
Figure 82. USART timing diagram in slave mode
NSS input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input
CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
tsu(RX) th(RX)
TX input First bit IN Next bits IN Last bit IN
MSv65387V5
342/390 DS13543 Rev 2

5.3.42 SPI characteristics

performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 33.
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 151. SPI characteristics(1)

Master mode, 2.7 V ≤ VDDIOX ≤ 3.6 V,

- - 80
voltage range 1
Master mode, 1.71 V ≤ VDDIOX < 2.7 V 75
- -
voltage range 1 or 50(2)
Master transmitter mode,
2.7 V ≤ VDDIOX ≤ 3.6 V, voltage range - - 80
1
Master transmitter mode,
75
1.71 V ≤ VDDIOX ≤ 2.7 V, voltage range - -
or 50(2)
1
Slave receiver mode,
fSCK 1.71 V ≤ VDDIOX ≤ 3.6 V, voltage range - - 100
SPI clock frequency MHz
1/tc(SCK) 1
Slave mode transmitter/full duplex(3),
37
1.71 V ≤ VDDIOX < 2.7 V, voltage range - -
or 25(4)
1
Slave mode transmitter/full duplex(3),
2.7 V ≤ VDDIOX ≤ 3.6 V, voltage range - - 35.5
1
Master or slave mode,
1.71 V ≤ VDDIOX ≤ 3.6 V, - - 12.5
voltage range 4
Master or slave mode,
- - 15
1.08 V ≤ VDDIO2 ≤ 1.32 V(5)
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352
Table 151. SPI characteristics(1) (continued)

tsu(NSS) NSS setup time Slave mode 4 - -

th(NSS) NSS hold time Slave mode 3 - -
tw(SCKH)
SCK high and low time Master mode tSCK(6)/2 - 1 tSCK/2 tSCK/2 + 1
tw(SCKL)
tsu(MI) Master mode 4.5 - -
Data input setup time
tsu(SI) Slave mode 2.5 - -
th(MI) Master mode 3 - -
Data input hold time
th(SI) Slave mode 1 - -
Data output access
ta(SO) Slave mode 9 12 34
time
Data output disable
tdis(SO) Slave mode 9 10 16
time
Slave mode, 2.7 V ≤ VDDIOX ≤ 3.6 V, ns
- 11.5 14
voltage range 1
Slave mode, 1.71 V ≤ VDDIOX < 2.7 V, 13.5
- 11.5
tv(SO) Data output valid time
Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V, 19.5
- 17
Slave mode,
- 23 25
1.08 V ≤ VDDIO2 ≤ 1.32 V(5)
3 or 9.5(7)
tv(MO) Data output valid time Master mode - 2.5
or 12.5(8)
Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V 7 - -
th(SO) Slave mode,
Data output hold time 15 - -
1.08 V ≤ VDDIO2 ≤ 1.32 V(5)
th(MO) Master mode 0.5 - -
2. When using PA5, PA9, PC10, PB3, PB13.
3. The maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) that has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
4. When using PA11, PB4, PB14.
5. The SPI is mapped on port G I/Os, that is supplied by VDDIO2 specified down to 1.08V. The SPI is tested at this value.
6. tSCK = tspi_ker_ck × baudrate prescaler.
7. When using PA12.
8. When using PB15.
344/390 DS13543 Rev 2

Figure 83. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V2
Figure 84. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V2
DS13543 Rev 2 345/390

352
Figure 85. SPI timing diagram - master mode

High
NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output
CPOL=0
CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
CPOL=0
SCK output
CPHA=1
CPOL=1
tsu(MI) th(MI)
MISO input First bit IN Next bits IN Last bit IN
MOSI output First bit OUT Next bits OUT Last bit OUT
tv(MO) th(MO) ai14136e
5.3.43 SAI characteristics

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized inTable 33, with the following configuration:
function characteristics (SCK, SD, FS).
346/390 DS13543 Rev 2

Table 152. SAI characteristics(1)

SAI main clock

fMCK - - 50
output
Master transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 26
Master transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 18
MHz
SAI clock Master receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 21.5
fSCK
frequency(2) Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 27.5
Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 18
Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 50
Master mode, 2.7 V ≤ VDDIOX ≤ 3.6 V - 16
tv(FS) FS valid time
Master mode 1.71 V ≤ VDDIOX ≤ 3.6 V - 23
th(FS) FS hold time Master mode 7 -
tsu(FS) FS setup time Slave mode 2.5 -
th(FS) FS hold time Slave mode 1 -
tsu(SD_A_MR) Data input Master receiver 4 -
t setup time Slave receiver 3 -
su(SD_B_SR)
th(SD_A_MR) Data input hold Master receiver 2 -

ns
th(SD_B_SR) time Slave receiver 1 -
Data output Slave transmitter (after enable edge), 2.7 V ≤ VDDIOX ≤ 3.6 V - 18
tv(SD_B_ST)
valid time Slave transmitter (after enable edge), 1.71 V ≤ VDDIOX ≤ 3.6 V - 27.5
Data output
th(SD_B_ST) Slave transmitter (after enable edge) 8 -
hold time
Data output Master transmitter (after enable edge), 2.7 V ≤ VDDIOX ≤ 3.6 V - 19
tv(SD_A_MT)
valid time Master transmitter (after enable edge), 1.71 V ≤ VDDIOX ≤ 3.6 V - 27.5
Data output
th(SD_A_MT) Master transmitter (after enable edge) 8 -
hold time
2. APB clock frequency that must be at least twice SAI clock frequency.
DS13543 Rev 2 347/390

352
Figure 86. SAI master timing diagram

1/fSCK
SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)
th(FS)
SAI_FS_X
(output)
tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
(transmit) Slot n Slot n+2
tsu(SD_MR) th(SD_MR)
SAI_SD_X
(receive) Slot n
MS32771V2
Figure 87. SAI slave timing diagram

1/fSCK
SAI_SCK_X
(CKSTR = 0)
SAI_SCK_X
(CKSTR = 1)
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input)
tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X Slot n Slot n+2

(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X
Slot n
(receive)
MS32772V2
5.3.44 OTG_HS characteristics

The OTG_HS controller complies with the following specifications:
• USB On-The-Go supplement, revision 2.0
• Universal Serial Bus revision 2.0 specification
• Battery charging specification, revision 1.2
348/390 DS13543 Rev 2

The parameters given in tables below are derived from tests performed under temperature
and VDD supply voltage conditions summarized in Table 33: General operating conditions.
Table 153. OTG_HS electrical characteristics(1)

(2)
VDDUSB USB transceiver operating voltage - 3.12 - 3.6 V
fHCLK value to guarantee proper operation of
fHCLK - 30(3) - - MHz
the OTG_HS interface
RPUI Embedded OTG_HS_DP pull-up value during idle - 900 1250 1575
Embedded OTG_HS_DP pull-up value during
RPUR - 1425(3) 2250 3090(3)
reception
Ω
Embedded OTG_HS_DP and OTG_HS_DM
RPD - 14250 - 24800
pull-down value
ZDRV Output driver impedance(4) Driving high or low 40.5(3) 45 49.5(3)
tlr Rise time CL < 5 pF 0.5(3) - -
ns
tlf Fall time CL < 5 pF 0.5(3) - -
tlrfm Rise/fall time matching - 80(3) - 125(3) %
1. Evaluated by characterization. Not tested in production, unless otherwise specified.
2. The USB functionality is ensured down to 3 V but not the full USB electrical characteristics which are degraded
in 3.0 to 3.12 V voltage range.
4. No external termination series resistors are required on OTG_HS_DP (D+) and OTG_HS_DM (D-). The matching
impedance is already included in the embedded driver.
Table 154. OTG_HS DC electrical characteristics(1)

Vhssq High-speed squelch detection threshold - 100(2) - 150

Vhsdsc High-speed disconnect detection threshold - 525 - 625
Vhsdif High-speed differential detection threshold - 100 - -
Vhscm High-speed data signaling common mode voltage range - -50 - 500
Vhsoi High-speed idle level - -10 - 10 mV
Vhsoh High-speed data signaling high - 360 - 440
Vhsol High-speed data signaling low - -10 - 10
Vhchirpj Chirp J level - 700 - 1100
Vhchirpk Chirp K level - -900 - -500
2. 50 mV test waivers from usb.org have been applied.
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352
Table 155. OTG_HS PHY BCD electrical characteristics(1)

Primary detection mode consumption on VDDUSB - - 4.9

IDD(USBBCD) 5.7
Secondary detection mode consumption on VDDUSB - - 4.8
Primary detection mode consumption on VDD11USB - - 5.2 mA
IDD11(USBBCD) Secondary detection mode consumption on 7.4
- - 5.3
VDD11USB
RDAT_LKG Data line leakage resistance - 300(2) - - kΩ
VDAT_LKG (2)
Data line leakage voltage - 0.0 - 3.6 V
(2)
RDCP_DAT Dedicated charging port resistance across D+/D- - - - 200 Ω
VLGC_HI Logic high - 2.0 3.6
VLGC_LOW Logic low - - - 0.8
VLGC Logic threshold - 0.8 - 2.0
V
VDAT_REF Data detect voltage - 0.25(2) - 0.4(2)
VDP_SRC D+ source voltage - 0.5 - 0.7
VDM_SRC D- source voltage - 0.5 - 0.7
IDM_SINK D- sink current - 25 - 175
IDP_SINK D+ sink current - 25 - 175 µA
IDP_SRC Data contact detect current source - 7.0 - 13
1. Evaluated by characterization. Not tested in production, unless otherwise specified.
Table 156. OTG_HS current consumption characteristics(1)

Suspend mode(2) - 53 173 µA
USB (PLL and PHY) current Full-speed transmit(3) - 9.9 12.2

IIDD(OTG_HS)
consumption on VDDUSB High-speed idle - 5.8 6.4 mA
High-speed transmit(3) - 13.5 16.0
Suspend mode(2) - 86 1570 µA
(3)
USB (PLL and PHY) current Full-speed transmit - 7.5 10.3
IIDD11(OTG_HS)
consumption on VDD11USB High-speed idle - 7.7 10.5 mA
High-speed transmit(3) - 9 12.2
2. Suspend when operating in device mode with no far-side host termination on DP/DM during measurements.
3. Transfers include 70% transmit activity and 30% interpacket delay.
350/390 DS13543 Rev 2

5.3.45 UCPD characteristics

UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0
specifications.
Table 157. UCPD characteristics

Sink mode only 3.0 3.3 3.6

VDD UCPD operating supply voltage V
Sink and source mode 3.135 3.3 3.465
5.3.46 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in the tables below are derived from tests
performed under the ambient temperature, fHCLKx frequency and VDD supply voltage
characteristics.
Table 158. JTAG characteristics(1)

2.7 V ≤ VDD ≤ 3.6 V - - 27.5

FTCK TCK clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V - - 20.5
tisu(TMS) TMS input setup time - 2 - -
tih(TMS) TMS input hold time - 3 - -
tisu(TDI) TDI input setup time - 3 - -
tih(TDI) TDI input hold time - 1 - - ns
2.7 V ≤ VDD ≤ 3.6 V - 14 18
tov(TDO) TDO output valid time
1.71 V ≤ VDD ≤ 3.6 V - 14 24
toh(TDO) TDO output hold time - 10 - -
Table 159. SWD characteristics(1)

2.7 V ≤ VDD ≤ 3.6 V - - 60.5

FSWCLK SWCLK clock frequency MHz
1.71 V ≤ VDD ≤ 3.6 V - - 43
tisu(SWDIO) SWDIO input setup time - 1 - -
ns
tih(SWDIO) SWDIO input hold time - 2.5 - -
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352
Table 159. SWD characteristics(1) (continued)

2.7 V ≤ VDD ≤ 3.6 V - 10.5 16.5

tov(SWDIO) SWDIO output valid time
1.71 V ≤ VDD ≤ 3.6 V - 10.5 23 ns
toh(SWDIO) SWDIO output hold time - 7.5 - -
Figure 88. JTAG timing diagram

tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
Figure 89. SWD timing diagram

tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
352/390 DS13543 Rev 2

STM32U5Axxx Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DS13543 Rev 2 353/390

385
Package information STM32U5Axxx
6.1 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.
Figure 90. LQFP64 - Outline(15)

BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4
0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C
D (4)
(5) (2) D1 (9) (11)
(10)
D (3) b WITH PLATING
N (4)
1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)
A A SECTION B-B
(Section A-A)
TOP VIEW 5W_LQFP64_ME_V1
354/390 DS13543 Rev 2

Table 160. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
DS13543 Rev 2 355/390

385
Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
356/390 DS13543 Rev 2

Figure 91. LQFP64 - Footprint example
48 33
0.30
49 0.5 32
12.70
10.30
10.30
64 17
1.20
1 16
7.80
12.70
5W_LQFP64_FP_V2
1. Dimensions are expressed in millimeters.
Device marking for LQFP64

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which also depend on supply chain operations,
are not indicated below.
Figure 92. LQFP64 marking example (package top view)
STM32U5A5
Product identification(1)
RJT6
Y WW Date code
Pin 1 identifier
R Revision code
MSv71168V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS13543 Rev 2 357/390

385
6.2 LQFP100 package information (1L)

This LQFP is 100 lead, 14 x 14 mm low-profile quad flat package.
ș2 ș
(2)
R1
H
R2
B
B-
N
O
(6)
TI
C
SE
D1/4 B GAUGE PLANE
S
E1/4
B ș
4x N/4 TIPS
ș L
4x (L1)
aaa C A-B D
bbb H A-B D (1) (11)
BOTTOM VIEW SECTION A-A
(N-4) x e (13)
C
A (9) (11)
0.05
ccc C b WITH PLATING
A2 A1 b aaa C A-BD
(12)
SIDE VIEW
D (4)
(11) c
(2) (5) D1 c1 (11)
D (3)
(10) (4)
N
b1 BASE METAL
1 (11)
2
3 E1/4 SECTION B-B
D1/4 (6) (2)

A B
(5)
E1 E
SECTION A-A
A A
TOP VIEW 1L_LQFP100_ME_V3
358/390 DS13543 Rev 2


Symbol
A - 1.50 1.60 - 0.0590 0.0630

(12)
A1 0.05 - 0.15 0.0019 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 16.00 BSC 0.6299 BSC
(2)(5)
D1 14.00 BSC 0.5512 BSC
E(4) 16.00 BSC 0.6299 BSC
E1(2)(5) 14.00 BSC 0.5512 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.177 0.0236 0.0295
(1)(11)
L1 1.00 - 0.0394 -
N(13) 100
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1) 0.20 0.0079
(1)
bbb 0.20 0.0079
ccc(1) 0.08 0.0031
(1)
ddd 0.08 0.0031
Notes:
as 0.15 mm.
DS13543 Rev 2 359/390

385
from the lead tip.
body.

75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
1L_LQFP100_FP_V1
360/390 DS13543 Rev 2


location.
STM32U5A5
VJT6Q
Date code
Y WW R
Pin 1 identifier
MSv71170V2
DS13543 Rev 2 361/390

385
6.3 UFBGA132 package information (A0G8)

This UFBGA is a 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array package.
Figure 96. UFBGA132 - Outline

A1 ball identifier
E1 B A
e E
Z
D1 D
12 1
BOTTOM VIEW Øb (132 balls) TOP VIEW
Øeee M C A B
Ø fff M C
A4
ddd C
A2 A3
b A1 A
SEATING
PLANE
UFBGA132_A0G8_ME_V2
Table 162. UFBGA132 - Mechanical data

Symbol
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
362/390 DS13543 Rev 2

Table 162. UFBGA132 - Mechanical data (continued)

Symbol
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
ddd - 0.080 - - 0.0031 -
eee - 0.150 - - 0.0059 -
fff - 0.050 - - 0.0020 -
Figure 97. UFBGA132 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 163. UFBGA132 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values
Pitch 0.5 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Ball diameter 0.280 mm
DS13543 Rev 2 363/390

385
Device marking for UFBGA132

location.
Figure 98. UFBGA132 marking example (package top view)
STM32U
5A5QJI6
Date code
Y WW R Revision code
Pin 1 identifier
MSv71173V1
364/390 DS13543 Rev 2

6.4 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.
BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
(6) B GAUGE PLANE
0.25
D 1/4
S
B
L
3
E 1/4 (L1)
(1) (11)
4x N/4 TIPS
aaa C A-B D SECTION A-A
bbb H A-B D 4x
(N-4)x e
C
A
0.05 (12) ddd C A-B D
A2 A1 b ccc C
D (4)
D1 (2) (5)
(10) (3) D (9) (11)
N (4)
b WITH PLATING
1
2
3 E 1/4
(11) (11)
c c1
(6)
D 1/4 (2)
(3) A B (3) (5)
E1 E b1 BASE METAL
(11)
SECTION B-B
A A
(Section A-A)
TOP VIEW
1A_LQFP144_ME_V2
DS13543 Rev 2 365/390

385

Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 22.00 BSC 0.8661 BSC
(2)(5)
D1 20.00 BSC 0.7874 BSC
E(4) 22.00 BSC 0.8661 BSC
E1(2)(5) 20.00 BSC 0.7874 BSC
e 0.50 BSC 0.0197 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 144
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°

R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa 0.20 0.0079
bbb 0.20 0.0079
ccc 0.08 0.0031
ddd 0.08 0.0031
366/390 DS13543 Rev 2

Notes:
as 0.15 mm.
from the lead tip.
body.
DS13543 Rev 2 367/390

385
108 73
1.35
109 0.35 72
0.50
19.90 17.85
22.60
144 37
1 36
19.90
22.60
1A_LQFP144_FP
368/390 DS13543 Rev 2


location.
Product identification(1) STM32U5A5ZJT6
R Revision code
Y WW Date code
Pin 1 identifier
MSv70422V2
DS13543 Rev 2 369/390

385
6.5 WLCSP150 package information (B0DX)

This WLCSP is a 150-ball, 5.38 x 5.47 mm, 0.4 mm pitch, wafer level chip scale array
package.
Figure 102. WLCSP150 - Outline

bbb Z
A1 BALL
LOCATION A1
F
e1
G
A3 A1
B4 B2
DETAIL A
e
e2 E
D A2
BOTTOM VIEW A
SIDE VIEW
A3
A2
FRONT VIEW b BUMP

X
A1
eee Z
b Z
(150)
ccc Z XY
ddd Z
E
DETAIL A
ROTATED
90
A1 ORIENTATION
REFERENCE
aaa
D
Y
TOP VIEW B0DX_WLCSP150_ME_V2

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball, there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
370/390 DS13543 Rev 2

Table 165. WLCSP150 - Mechanical data

Symbol
A - - 0.58 - - 0.0228
(2)
A1 - 0.17 - - 0.0067 -
A2(2) - 0.38 - - 0.0150 -
A3(3) - 0.025 - - 0.0010 -
(4)
b 0.23 0.26 0.28 0.0090 0.0102 0.0110
D 5.36 5.38 5.40 0.2110 0.2118 0.2126
E 5.45 5.47 5.49 0.2146 0.2153 0.2161
e - 0.40 - - 0.0157 -
e1 - 4.16 - - 0.1638 -
e2 - 4.40 - - 0.1732 -
F(5) - 0.612 - - 0.0241 -
G(5) - 0.535 - - 0.0212 -
N 150
aaa - 0.10 - - 0.0043 -
bbb - 0.10 - - 0.0043 -
(6)
ccc - 0.10 - - 0.0043 -
(7)
ddd - 0.05 - - 0.0020 -
eee - 0.05 - - 0.0020 -
2. The maximum total package height is calculated by the RSS method (root sum square) using nominal and
tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the third decimal place resulting from process
capability.
5. Calculated dimensions are rounded to the third decimal place.
the pattern of balls with respect to datums X and Y. For each ball, there is a cylindrical tolerance zone ccc
7. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball, there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.
DS13543 Rev 2 371/390

385
Figure 103. WLCSP150 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 166. WLCSP150 - Recommended PCB design rules

Dimension Recommended values
Pitch 0.4 mm
Dpad 0,250 mm
Dsm 0.325 mm typ. (depends on soldermask registration tolerance)
Stencil thickness 0.080 to 0.100 mm
Device marking for WLCSP150

The following figure gives an example of topside marking orientation versus ball 1 identifier
location.
Figure 104. WLCSP150 marking example (package top view)
Ball A1 identifier
Product identification(1) 32U5A9ZJ6Q
Date code Y WW R Revision code
MSv71554V1
372/390 DS13543 Rev 2

6.6 TFBGA169 package information (B0MA)

This TFBGA is a 169-ball, 7 x 7 mm, 0.50 mm pitch, thin fine pitch ball grid array package.
Figure 105. TFBGA169 - Outline
C Seating plane
A4
ddd C
A
A2 A1
b
SIDE VIEW
A1 CORNER INDEX AREA

E
B
E1
A
e Z
A
B
C Z
D
E
F
G D1 D
H
J
K
L e
M
N
13 12 11 10 9 8 7 6 5 4 3 2 1
Øb (169 balls)
Ø eee M C A B
BOTTOM VIEW Ø fff M C
B0MA_TFBGA169_ME_V1

2. - The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized
markings, or other feature of package body or integral heat-slug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
Table 167. TFBGA169 - Mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A (2) - - 1.137 - - 0.0448

A1 0.125 - - 0.0049 - -
A2 - 0.29 - - 0.0114 -
A4 - 0.62 - - 0.0244 -
b(3) 0.25 0.30 0.35 0.0098 0.0118 0.0138
D 6.95 7.000 7.05 0.2736 0.2756 0.2776
D1 - 6.00 - 0.2343 0.2362 0.2382
E 6.95 7.000 7.05 0.2736 0.2756 0.2776
E1 - 6.00 - 0.2343 0.2362 0.2382
e - 0.50 - - 0.0197 -
Z - 0.50 - 0.0177 0.0197 0.0217
ddd - - 0.08 - - 0.0031
DS13543 Rev 2 373/390

385
Table 167. TFBGA169 - Mechanical data (continued)

Symbol
Min. Typ. Max. Min. Typ. Max.
eee(4) - - 0.09 - - 0.0035

fff(5) - - 0.05 - - 0.0020
2. - Thin profile: 1.00mm < A ≤ 1.20mm / Fine pitch: e < 1.00 mm pitch.
- The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A Max = A1 Typ + A2 Typ + A4 Typ +√ (A1² + A2² + A4² tolerance values)
3. The typical ball diameter before mounting is 0.25 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.
Figure 106. TFBGA169 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
374/390 DS13543 Rev 2

Table 168. TFBGA169 - Example of PCB design rules (0.5 mm pitch BGA)
Dimension Values
Pitch 0.5 mm
Dpad 0.30 mm
Dsm 0.376 mm (pad + 2 x 0.038)
Board metal pad diameter 0.25 mm to 0.30 mm
Trace width top view 0.14 mm aperture diameter.
Device marking for TFBGA169

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 107. TFBGA169 marking example (package top view)
Product
identification (1) STM32U5
A5AJH6
Revision code
R
Date code
Ball A1
identifier Y WW
MSv71540V2
DS13543 Rev 2 375/390

385
6.7 WLCSP208 package information (B0DV)

This WLCSP is a 208-ball, 5.38 x 5.47 mm, 0.35 mm pitch, wafer level chip scale package.
Figure 108. WLCSP208 - Outline

bbb Z
A2 BALL LOCATION
F A2 ORIENTATION
A1
REFERENCE
e1 aaa
(4X)
G
DETAIL A
e2 E E
e D A2
D
A
BOTTOM VIEW TOP VIEW
A3 SIDE VIEW
A2
b BUMP
FRONT VIEW
A1
eee Z
Z
b(208x)
ccc Z X Y
ddd Z
DETAIL A SEATING PLANE
ROTATED 90
B0DV_WLCSP208_ME_V1

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
376/390 DS13543 Rev 2

Table 169. WLCSP208 - Mechanical data

Symbol
A(2) - - 0.58 - - 0.0228

A1 - 0.17 - - 0.0067 -
A2 - 0.38 - - 0.0150 -
(3)
A3 - 0.025 - - 0.0010 -
(4)
b 0.22 0.24 0.27 0.0087 0.0094 0.0106
D 5.37 5.38 5.39 0.2114 0.2118 0.2122
E 5.45 5.47 5.49 0.2146 0.2154 0.2161
e - 0.35 - - 0.0138 -
e1 - 4.38 - - 0.1724 -
e2 - 4.55 - - 0.1791 -
F(5) - 0.503 - - 0.0198 -
G(5) - 0.462 - - 0.0182 -
N 208
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
(6)
ccc - - 0.10 - - 0.0039
(7)
ddd - - 0.05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 4decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
5. Calculated dimensions are rounded to the 3rd decimal place
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones.
DS13543 Rev 2 377/390

385
Figure 109. WLCSP208 - Recommended footprint
Dpad
Dsm
Table 170. WLCSP208 - Recommended PCB design rules

Dimension Recommended values
Pitch 0.35 mm
Dpad 0,210 mm
Dsm 0.275 mm typ. (depends on soldermask registration tolerance)
Stencil thickness 0.100 mm
Device marking for WLCSP208

location.
378/390 DS13543 Rev 2

Figure 110. WLCSP208 marking example (package top view)
Ball A1 identifier
Product identification(1) 32U5A9BJ6Q
Date code Y WW R Revision code
MSv70423V2
DS13543 Rev 2 379/390

385
6.8 TFBGA216 package information (A0L2)

This TFBGA is a 216-ball, 13 x 13 mm, 0.8 mm pitch, fine pitch ball grid array package.
Figure 111. TFBGA216 - Outline
Z Seating plane
ddd Z
A2
A1 A
D1 A1 ball A1 ball X
identifier index area D
e F
A
G
E1 E
e
Y
R
15 1
BOTTOM VIEW Øb (216 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z
A0L2_ME_V3

2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional
380/390 DS13543 Rev 2

Table 171. TFBGA216 - Mechanical data

Symbol
A - - 1.200 - - 0.0472
A1(2) 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
(3)
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 12.850 13.000 13.150 0.5059 0.5118 0.5177
D1 - 11.200 - - 0.4409 -
E 12.850 13.000 13.150 0.5059 0.5118 0.5177
E1 - 11.200 - - 0.4409 -
e - 0.800 - - 0.0315 -
F - 0.900 - - 0.0354 -
G - 0.900 - - 0.0354 -
ddd - - 0.100 - - 0.0039
(4)
eee - - 0.150 - - 0.0059
fff(5) - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized
markings, or other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
3. Initial ball equal 0.350 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true
position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball
must lie within this tolerance zone.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball
must lie simultaneously in both tolerance zones.
DS13543 Rev 2 381/390

385
Figure 112. TFBGA216 - Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
382/390 DS13543 Rev 2

Table 172. TFBGA216 - Example of PCB design rules (0.8 mm pitch)

Dimension Values
Pitch 0.8 mm
Dpad 0.400 mm
0.470 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Device marking for TFBGA216

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 113. TFBGA216 marking example (package top view)
Product
identification (1) STM32U5A9
NJH6Q
Revision code
R
Date code
Y WW
Ball A1
identifier
MSv70424V2
MSv69529V1
DS13543 Rev 2 383/390

385
6.9 Package thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the following equation:
TJ max = TA max + (PD max * ΘJA)
where:
• TA max is the maximum ambient temperature in °C.
• ΘJA is the package junction-to-ambient thermal resistance in °C/W.
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max).
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
PI/O max = ∑(VOL * IOL) + ∑((VDDIOx - VOH) * IOH)
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the
application.
384/390 DS13543 Rev 2

Table 173. Package thermal characteristics

Symbol Parameter Package Value Unit
LQFP64 (10 x10 mm) 36.0

LQFP100 (14 x 14 mm) 32.2
UFBGA132 (7 x 7 mm) 30.9
LQFP144 (20 x 20 mm) 34.1
ΘJA Thermal resistance junction-ambient
WLCSP150 (5.38 x 5.47 mm) 31.7
TFBGA169 (7 x 7 mm) 32.2
WLCSP208 (5.38 x 5.47 mm) 35.4
TFBGA216 (13 x 13 mm) 26.5
LQFP64 (10 x10 mm) 18.3
LQFP100 (14 x14 mm) 18.0
UFBGA132 (7 x 7 mm) 15.9
LQFP144 (20 x 20 mm) 22.9
ΘJB Thermal resistance junction-board °C/W
WLCSP150 (5.38 x 5.47 mm) 13.5
TFBGA169 (7 x 7 mm) 17.7
WLCSP208 (5.38 x 5.47 mm) 12.5
TFBGA216 (13 x 13 mm) 16.0
LQFP64 (10 x 10 mm) 6.8
LQFP100 (14 x 14 mm) 5.9
UFBGA132 (7 x 7 mm) 6.0
LQFP144 (20 x 20 mm) 6.0
ΘJC Thermal resistance junction-case
WLCSP150 (5.38 x 5.47 mm) 0.9
TFBGA169 (7 x 7 mm) 9.0
WLCSP208 (5.38 x 5.47 mm) 1.0
TFBGA216 (13 x 13 mm) 7.7
6.9.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air) available on www.jedec.org.
• For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available on www.st.com.
DS13543 Rev 2 385/390

385
Ordering information STM32U5Axxx
7 Ordering information
Example: STM32 U 5A9 B J Y 6 Q TR

Device family
STM32 = Arm® based 32-bit microcontroller
Product type
U = ultra-low-power
Device subfamily
5A9 = STM32U5A9xx with GFX accelerators and interfaces, OTG_HS,

and hardware encryption accelerators
5A5 = STM32U5A5xx with OTG_HS and hardware encryption accelerators
Pin/ball count
R = 64 pins
V = 100 pins
Q = 132 balls
Z = 144 pins or 150 balls
A = 169 balls
B = 208 balls
N= 216 balls
Flash memory size

I = 2 Mbytes
J = 4 Mbytes
Package
T = LQFP
H = TFBGA
I = UFBGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125°C (130°C junction)
Dedicated pinout
Q = Dedicated pinout supporting internal SMPS step-down converter
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.
386/390 DS13543 Rev 2

STM32U5Axxx Important security notice
8 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS13543 Rev 2 387/390

387
Revision history STM32U5Axxx
9 Revision history
Table 174. Document revision history

Date Revision Changes
16-Feb-2023 1 Initial release.

Updated:
– CoreMark® value changed in Features
– Table 2: STM32U5Axxx features and peripheral counts
– Figure 2: STM32U5AxxxxxQ power supply overview (with SMPS)
– Figure 3: STM32U5Axxx power supply overview (without SMPS)
– Section 3.9.1: Power supply schemes
– Section 3.9.3: Low-power modes
– Table 10: Functionalities depending on the working mode
– Table 15: ADC features
– Figure 23: STM32U5Axxx power supply scheme (without SMPS)
– Figure 24: STM32U5AxxxxxQ power supply scheme (with SMPS)
– Typical values for temperatures between 55 °C and 125 °C in
Section 5.3.6: Supply current characteristics
– Table 71: Low-speed external user clock characteristics
– Increased HSE consumption during startup from 8 µA to 8 mA in
Table 72: HSE oscillator characteristics
– Table 84: ESD absolute maximum ratings
– Table 89: Output voltage characteristics for FT_t I/Os in VBAT
mode, and for FT_o I/Os
18-Jul-2023 2 – Table 93: Output AC characteristics for FT_t I/Os in VBAT mode,
and for FT_o I/Os
– tCAL and tOFF_CAL values in Table 97: 14-bit ADC12 characteristics
– Table 99: 14-bit ADC12 accuracy
– tOFF_CAL values in Table 100: 12-bit ADC4 characteristics
– Section 5.3.28: Temperature and backup domain supply
thresholds monitoring
– Table 116: PSSI receive characteristics
– Table 119: MIPI D-PHY AC characteristics LP mode and HS/LP
transitions
– Table 126: Asynchronous non-multiplexed SRAM/PSRAM/NOR
read timings
– Table 140: OCTOSPI characteristics in SDR mode
– Table 144: HSPI characteristics in DTR mode (no DQS)
– Table 142: OCTOSPI characteristics in DTR mode (with
DQS)/HyperBus
– HSPI characteristics tables and figures in Section 5.3.37: HSPI
characteristics
– Figure 81: USART timing diagram in master mode
– Figure 82: USART timing diagram in slave mode
388/390 DS13543 Rev 2

STM32U5Axxx Revision history
Table 174. Document revision history (continued)

Date Revision Changes
– Figure 83: SPI timing diagram - slave mode and CPHA = 0

– Figure 84: SPI timing diagram - slave mode and CPHA = 1
– Figure 85: SPI timing diagram - master mode
– Figure 86: SAI master timing diagram
– Figure 87: SAI slave timing diagram
– Section 6.1: LQFP64 package information (5W)
– Section 6.2: LQFP100 package information (1L)
– Section 6.3: UFBGA132 package information (A0G8)
– Section 6.4: LQFP144 package information (1A)
– Section 6.5: WLCSP150 package information (B0DX)
– Section 6.6: TFBGA169 package information (B0MA)
– Section 6.7: WLCSP208 package information (B0DV)
– Section 6.8: TFBGA216 package information (A0L2)
– Figure 95: LQFP100 marking example (package top view)
2 – Figure 101: LQFP144 marking example (package top view)
18-Jul-2023 – Figure 107: TFBGA169 marking example (package top view)
(cont’d)
– Figure 110: WLCSP208 marking example (package top view)
Added:
– SESIP3 and PSA Level 3 Certified Assurance Target in Security
and cryptography
– STM32U5A5QI in Table 1: Device summary, Table 2:
STM32U5Axxx features and peripheral counts, and Section 7:
Ordering information
– Section 5.3.4: SMPS characteristics
– Maximum values for each temperature in Section 5.3.6: Supply
current characteristics
– Maximum values added in Table 66: Low-power mode wake-up
timings on LDO, Table 67: Low-power mode wake-up timings on
SMPS, and Table 68: Regulator mode transition times
– Current consumption during wake-up tables
– Figure 104: WLCSP150 marking example (package top view)
DS13543 Rev 2 389/390

389
STM32U5Axxx
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2023 STMicroelectronics – All rights reserved
390/390 DS13543 Rev 2

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STM32U5Axxx

Ultra-low-power Arm® Cortex®-M33 32-bit MCU+TrustZone®+FPU,

Ultra-low-power with FlexPowerControl

• 1.71 V to 3.6 V power supply • 655 CoreMark® (4.09 CoreMark®/MHz)

• VBAT mode: supply for RTC, 32 x 32-bit backup • 120000 SecureMark™-TLS

July 2023 DS13543 Rev 2 1/390

General-purpose input/outputs basic, 4 low-power 16-bit (available in Stop

Clock management Up to 25 communication peripherals

• 96-bit unique ID STM32U5A5AJ, STM32U5A5QI,

2/390 DS13543 Rev 2

DS13543 Rev 2 3/390

3.13 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 52

4/390 DS13543 Rev 2

3.34 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

DS13543 Rev 2 5/390

3.52 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4 Pinout, pin description and alternate functions . . . . . . . . . . . . . . . . . 100

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6/390 DS13543 Rev 2

5.3.11 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

DS13543 Rev 2 7/390

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

8/390 DS13543 Rev 2

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS13543 Rev 2 9/390

10/390 DS13543 Rev 2

Table 91. Output AC characteristics, HSLV ON (all I/Os except FT_c,

DS13543 Rev 2 11/390

Table 142. OCTOSPI characteristics in DTR mode (with DQS)/HyperBus . . . . . . . . . . . . . . . . . . . . 329

12/390 DS13543 Rev 2

Figure 1. STM32U5Axxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DS13543 Rev 2 13/390

Figure 48. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

14/390 DS13543 Rev 2

Figure 100. LQFP144 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

DS13543 Rev 2 15/390

16/390 DS13543 Rev 2

The STM32U5Axxx devices belong to an ultra-low-power microcontrollers family

DS13543 Rev 2 17/390

The devices embed mathematical accelerators (a trigonometric functions accelerator plus a

Table 2. STM32U5Axxx features and peripheral counts

18/390 DS13543 Rev 2

Table 2. STM32U5Axxx features and peripheral counts (continued)

Low power 4 (16 bits)

DS13543 Rev 2 19/390

Table 2. STM32U5Axxx features and peripheral counts (continued)

CORDIC co-processor Yes

20/390 DS13543 Rev 2

Table 2. STM32U5Axxx features and peripheral counts (continued)

DS13543 Rev 2 21/390

Figure 1. STM32U5Axxx block diagram

AHB bus matrix

SDMMC2 FIFO AHB2 160 MHz

8 groups of 4 channels max TSC MSI @VDD

PE[15:0] GPIO port E

PF[15:0] GPIO port F Standby