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    21EC63 6th Sec A QP2

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    DARSHAN DARSH

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    21EC63 6th Sec A QP2

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    DARSHAN DARSH
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    21EC63_6th_sec_A_QP2

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    21EC63 6th Sec A QP2

    Uploaded by

    DARSHAN DARSH

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    USN 1 K I E C

    Visvesvaraya Technological University


    KALPATARU INSTITUTE OF TECHNOLOGY
    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
    Even Semester 2024
    Sixth Semester B.E (Section A)
    Test : I Date : 11/06/2024 Time : 9.30am– 11.00am Marks : 50
    Course : VLSI Design &Testing Course code : 21EC63
    Note : Answer 3 Full questions by choosing any one question from Part A, Part B and Part C

    Q.No Question Marks RBT COs


    Part -A
    1 a Explain the operation of MOSFET with necessary diagrams. Also Derive equation for drain current in linear
    10 L1 CO1
    and saturation region.
    b Explain in detail Wafer formation and Photolithography process with suitable diagrams 10 L1 CO2

    OR
    2 a With necessary circuit diagram, explain the operation of tristate inverter. Also realize a 2:1 multiplexer using
    10 L2 CO1
    tristate inverter.
    b Draw schematic and stick diagram for Y=𝐴(𝐵̅̅̅̅̅̅̅̅̅̅̅̅
    + 𝐶) using Euler’s graph method. 10 L3 CO2

    Part -B
    3 a Explain DC transfer characteristics of a CMOS inverter and mark all the regions, show the status on pMOS
    10 L1 CO1
    and nMOS mode of operation.
    b Define Feature size for any semiconductor technology. Draw and list simplified Lambda based design rules
    10 L3 CO2
    for a simple 2 metal layers n-well process.
    OR
    4 a List and explain in brief following Non ideal I-V effects.

    b
    saturation d) Leakage Current. e) Temperature dependence.
    Sketch a Transistor level circuit for following compound gate function in cmos style.
    ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
    + 𝐵 + 𝐶)𝐷
    A"
    a) Channel Length modulation. b) Threshold voltage / Body effect. c) Mobility Degradation & Velocity 10 L1 CO1
    c"
    (i) Y=(𝐴
    (ii) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
    Y=(𝐴 + 𝐵) + (𝐶 + 𝐷) L3
    10 CO2
    (iii) ̅̅̅̅̅̅̅̅̅̅̅̅
    Y=𝐴𝐵𝐶 +𝐷
    Se

    (iv) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
    Y=(𝐴𝐵 + 𝐶)𝐷

    Part -C
    5 Draw and indicate dimensions for (i)Pitch of routing tracks (ii)spacing between nmos and pmos transistors.
    10 L1 CO1
    h

    Sketch stick diagram for 3 input nand gate.


    OR
    6t

    6 Implement a D Flipflop using transmission gates and explain its operation with necessary timing diagram. 10 L1 CO2

    Course outcomes: At the end of the course, the students will be able to: RBT Level:
    CO1: Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology scaling.
    CO2: Draw the basic gates using the stick and layout diagrams with the knowledge of physical design aspects.
    L1: Remembering
    CO3: Interpret Memory elements along with timing considerations L2: Understanding
    CO4: Interpret testing and testability issues in Combinational logic Design L3: Applying
    CO5: Interpret testing and testability issues in Sequential logic Design L4: Analyzing
    L5: Evaluating
    L6: Creating

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