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UC3842/UC3843/UC3844/UC3845
SMPS Controller

Features Description
• Low Start up Current The UC3842/UC3843/UC3844/UC3845 are fixed
• Maximum Duty Clamp frequencycurrent-mode PWM controller. They are specially
• UVLO With Hysteresis designed for Off-Line and DC to DC converter applications
• Operating Frequency up to 500KHz with minimum external components. These integrated
circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain
error amplifier, current sensing comparator and a high
current totempole output for driving a Power MOSFET. The
UC3842 and UC3844 have UVLO thresholds of 16V (on)
and 10V (off). The UC3843 and UC3845 are 8.5V(on) and
7.9V (off). The UC3842 and UC3843 can operate within
100% duty cycle. The UC3844 and UC3845 can operate
with 50% duty cycle.
8-DIP 8-SOP

1
1
14-SOP

Internal Block Diagram

* NORMALLY 8DIP/8SOP PIN NO.

* ( ) IS 14SOP PINNO.
* TOGGLE FLIP FLOP USED ONLY IN UC3844, UC3845

Rev. 1.0.1
©2002 Fairchild Semiconductor Corporation
UC3842/UC3843/UC3844/UC3845

Absolute Maximum Ratings

Parameter Symbol Value Unit
Supply Voltage VCC 30 V
Output Current IO ±1 A
Analog Inputs (Pin 2.3) V(ANA) -0.3 to 6.3 V
Error Amp Output Sink Current ISINK (E.A) 10 mA
Power Dissipation at TA≤25°C (8DIP) PD(Note1,2) 1200 mW
Power Dissipation at TA≤25°C (8SOP) PD(Note1,2) 460 mW
Power Dissipation at TA≤25°C (14SOP) PD(Note1,2) 680 mW
Storage Temperature Range TSTG -65 ~ +150 °C
Lead Temperature (Soldering, 10sec) TLEAD +300 °C
Note:
1. Board Thickness 1.6mm, Board Dimension 76.2mm ×114.3mm, (Reference EIA / JSED51-3, 51-7)
2. Do not exceeed PD and SOA (Safe Operation Area)

Power Dissipation Curve

1200
8DIP
1100
POWER DISSIPATION (mW)

1000

900
800 14SOP

700

600 8SOP

500
400
300
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

AMBIENT TEMPERATURE (℃)

Thermal Data
Characteristic Symbol 8-DIP 8-SOP 14-SOP Unit
Thermal Resistance Junction-ambient Rthj-amb(MAX) 100 265 180 °C/W

Pin Array
8DIP,8SOP 14SOP

COMP 1 8 VREF COMP 1 14 VREF

VFB 2 7 VCC N/C 2 13 N/C

CURRENT SENSE 3 6 OUTPUT VFB 3 12 VCC

RT/ CT 4 5 GND N/C 4 11 PWR VC

CURRENT SENSE 5 10 OUTPUT

N/C 6 9 GND

RT/C T 7 8 PWR GND

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 UC3842/UC3843/UC3844/UC3845

Electrical Characteristics
(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. Unit

REFERENCE SECTION
Reference Output Voltage VREF TJ = 25°C, IREF = 1mA 4.90 5.00 5.10 V
Line Regulation ∆VREF 12V ≤ VCC ≤ 25V - 6 20 mV
Load Regulation ∆VREF 1mA ≤ IREF ≤ 20mA - 6 25 mV
Short Circuit Output Current ISC TA = 25°C - -100 -180 mA
OSCILLATOR SECTION
Oscillation Frequency f TJ = 25°C 47 52 57 kHz
Frequency Change with
∆f/∆VCC 12V ≤ VCC ≤ 25V - 0.05 1 %
Voltage
Oscillator Amplitude VOSC - - 1.6 - VP-P
ERROR AMPLIFIER SECTION
Input Bias Current IBIAS - - -0.1 -2 µA
Input Voltage VI(E>A) Vpin1 = 2.5V 2.42 2.50 2.58 V
Open Loop Voltage Gain GVO 2V ≤ VO ≤ 4V (Note3) 65 90 - dB
Power Supply Rejection Ratio PSRR 12V ≤ VCC ≤ 25V (Note3) 60 70 - dB
Output Sink Current ISINK Vpin2 = 2.7V, Vpin1 = 1.1V 2 7 - mA
Output Source Current ISOURCE Vpin2 = 2.3V, Vpin1 = 5V -0.6 -1.0 - mA
High Output Voltage VOH Vpin2 = 2.3V, RL = 15kΩ to GND 5 6 - V
Low Output Voltage VOL Vpin2 = 2.7V, RL = 15kΩ to Pin 8 - 0.8 1.1 V
CURRENT SENSE SECTION
Gain GV (Note 1 & 2) 2.85 3 3.15 V/V
Maximum Input Signal VI(MAX) Vpin1 = 5V(Note 1) 0.9 1 1.1 V
Power Supply Rejection Ratio PSRR 12V ≤ VCC ≤ 25V (Note 1,3) - 70 - dB
Input Bias Current IBIAS - - -3 -10 µA
OUTPUT SECTION
VOL ISINK = 20mA - 0.08 0.4 V
Low Output Voltage
ISINK = 200mA - 1.4 2.2 V
High Output Voltage ISOURCE = 20mA 13 13.5 - V
VOH
ISOURCE = 200mA 12 13.0 - V
Rise Time tR TJ = 25°C, CL= 1nF (Note 3) - 45 150 ns
Fall Time tF TJ = 25°C, CL= 1nF (Note 3) - 35 150 ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold UC3842/UC3844 14.5 16.0 17.5 V
VTH(ST)
UC3843/UC3845 7.8 8.4 9.0 V
Min. Operating Voltage UC3842/UC3844 8.5 10.0 11.5 V
VOPR(MIN)
(After Turn On) UC3843/UC3844 7.0 7.6 8.2 V

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UC3842/UC3843/UC3844/UC3845

Electrical Characteristics (Continued)

(VCC=15V, RT=10kΩ, CT=3.3nF, TA= 0°C to +70°C, unless otherwise specified)

Parameter Symbol Conditions Min. Typ. Max. Unit

PWM SECTION
D(Max) UC3842/UC3843 95 97 100 %
Max. Duty Cycle
D(Max) UC3844/UC3845 47 48 50 %
Min. Duty Cycle D(MIN) - - - 0 %
TOTAL STANDBY CURRENT
Start-Up Current IST - - 0.45 1 mA
Operating Supply Current ICC(OPR) Vpin3=Vpin2=ON - 14 17 mA
Zener Voltage VZ ICC = 25mA 30 38 - V

Adjust VCC above the start threshould before setting at 15V

Note:
1. Parameter measured at trip point of latch
2. Gain defined as:
∆V pin1
- ,0 ≤ Vpin3 ≤ 0.8V
A = -----------------
∆V pin3
3. These parameters, although guaranteed, are not 100 tested in production.

UC3842

Figure 1. Open Loop Test Circuit

High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors
should be connected close to pin 5 in a single point ground. The transistor and 5kΩ potentiometer are used to sample the
oscillator waveform and apply an adjustable ramp to pin 3.

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 UC3842/UC3843/UC3844/UC3845

UC3842/44 UC3843/45

Figure 2. Under Voltage Lockout

During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with
a bleeder resistor to prevent activating the power switch with output leakage current.

Figure 3. Error Amp Configuration

Figure 4. Current Sense Circuit

Peak current (IS) is determined by the formula:

1.0V
I S ( MAX ) = ------------
RS

A small RC filter may be required to suppress switch transients.

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UC3842/UC3843/UC3844/UC3845

Figure 5. Oscillator Waveforms and Maximum Duty Cycle

Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the
discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both
oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:
tc = 0.55 RT CT
0.0063RT – 2.7
t D = R T C T I n  ----------------------------------------
0.0063R T – 4

Frequency, then, is: f=(tc + td)-1

1.8
ForRT > 5KΩ ,f = ---------------
RT CT

Figure 6. Oscillator Dead Time & Frequency Figure 7. Timing Resistance vs Frequency

(Deadtime vs CT RT > 5kΩ)

Figure 8. Shutdown Techniques

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 UC3842/UC3843/UC3844/UC3845

Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two
diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The
PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins
1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be
reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.

UC3842/UC3843

Figure 9. Slope Compensation

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, CT, forms a filter with R2 to suppress the leading edge switch
spikes.

Temperature (°C) Temperature (°C)

Figure 10. Temperature Drift (Vref) Figure 11. Temperature Drift (Ist)

Temperature (°C)
Figure 12. Temperature Drift (Icc)

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UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions
Package

8-DIP

)
6.40 ±0.20

0.031
0.79
0.252 ±0.008

1.524 ±0.10
0.060 ±0.004
0.018 ±0.004
0.46 ±0.10
(
#1 #8

0.362 ±0.008
MAX

9.20 ±0.20
0.378
9.60

#4 #5

0.100
2.54
5.08 3.30 ±0.30
MAX 0.130 ±0.012
0.200
7.62
0.300 3.40 ±0.20 0.33
MIN
0.134 ±0.008 0.013

+0.10
0.25 –0.05
+0.004
0.010 –0.002
0~15°

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 UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions (Continued)

Package

8-SOP
0.1~0.25
MIN
0.004~0.001
1.55 ±0.20
0.061 ±0.008

)
0.022
0.56
(
#1 #8

0.194 ±0.008
MAX

4.92 ±0.20
0.202
5.13

0.016 ±0.004
0.41 ±0.10
#4 #5

0.050
1.27
6.00 ±0.30 1.80
0.236 ±0.012 MAX
0.071
0.006 -0.002

0.15 -0.05

MAX0.004
MAX0.10

3.95 ±0.20
+0.004

+0.10

0.156 ±0.008
8°

5.72
0~

0.225
0.50 ±0.20
0.020 ±0.008

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UC3842/UC3843/UC3844/UC3845

Mechanical Dimensions (Continued)

Package

14-SOP
0.05
MIN
0.002
1.55 ±0.10

)
0.061 ±0.004

0.019
0.47
(
#1 #14

MAX

0.337 ±0.008

+0.004
8.56 ±0.20

+0.10

0.016 -0.002
0.406 -0.05
0.343
8.70

#7 #8

0.050
1.27
6.00 ±0.30 1.80
0.236 ±0.012 MAX
0.071
+0.004
+0.10

0.008 -0.002
0.20 -0.05

MAX0.004
MAX0.10

3.95 ±0.20
0.156 ±0.008

5.72
8°
0~

0.225
0.60 ±0.20
0.024 ±0.008

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 UC3842/UC3843/UC3844/UC3845

Ordering Information
Product Number Package Operating Temperature
UC3842N
UC3843N
8-DIP
UC3844N
UC3845N
UC3842D1
UC3843D1
8-SOP 0 ~ + 70°C
UC3844D1
UC3845D1
UC3842D
UC3843D
14-SOP
UC3844D
UC3845D

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UC3842/UC3843/UC3844/UC3845

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support
perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

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 2002 Fairchild Semiconductor Corporation