Chap1,2,3 Imp QsnAns
Chap1,2,3 Imp QsnAns
Chap1,2,3 Imp QsnAns
Boolean rules
Properties of 0 and 1 1). 0+X=X 2). 1+X=1
3). 0.X=0 4). 1.X=X
Idempotence Law 5). X+X=X 6). X.X=X
Involution Law 7. (X’)’ =X (i.e., X double complement is X only)
Complementarity Law 8. X+ X = 1 (or X+X’ = 1)
9. X . X = 0 (or X.X’ = 0)
Commutative Law 10. X+Y=Y+X or A+B+C = B+A+C = C+B+A =A+C+B
11. X.Y=Y.X or A.B.C = B.A.C = C.B.A =A.C.B
Associative Law 12. X+(Y+Z) = (X+Y)+Z
13. X.(Y.Z) = (X.Y).Z
Distributive Law 14. X.(Y+Z) = X.Y+X.Z
15. X+Y.Z = (X+Y).(X+Z)
Absorption Law 16). X+X.Y = X 17) X.(X+Y) = X
Other theorem 18). X+X’.Y = X+Y
X X+Y X Y F=(X+Y)’
0 0 1
Y 0 1 0
1 0 0
1 1 0
2. Write the Logic symbol and truth table of NAND gate.
Ans.:
X Y F=(X.Y)’
0 0 1
X.Y 0 1 1
1 0 1
1 1 0
3. Write the Logic symbol and truth table of XOR gate. (***)
Ans.: The output of XOR gate is 1when the odd number of i/ps are 1;O/p is 0 otherwise.
A B F=(A B)
0 0 0
0 1 1
1 0 1
1 1 0
5. Design the basic gates using NAND gates only. ( Show that NAND gate is a universal gate)
(***)
Ans.: All other gates can be designed using only NAND gates. It is depicted as:
i) Designing NOT gate from NAND.
X
X’
X.Y
6. Design the basic gates using NOR gates only. / Design NOT, OR, AND gates using NOR gates
only. / Realize the basic gates using only NOR gates. ***
Ans.: i). Designing NOT gate from NOR gate
A’
A+B
A.B