Counter:

`timescale 1ns / 1ps

module counter( Clock, Reset, Count);

input Clock;
input Reset;
output [3:0] Count;

reg [3:0] Count;

always@(posedge Reset or negedge Clock)

begin
if (Reset)
Count <= 4'd0;
else
Count <= Count + 1;
end
endmodule

Counter_tb:
`timescale 1ns / 1ps

module counter_tb;

// Inputs
reg Clock;
reg Reset;

// Outputs
wire [3:0] Count;

// Instantiate the Unit Under Test (UUT)

counter uut (
.Clock(Clock),
.Reset(Reset),
.Count(Count)
);

initial begin
// Initialize Inputs
Clock = 0;
Reset = 0;

#30 Reset = 1;
#40 Reset = 0;
#450 Reset = 1;
#480 Reset = 0;
end

// Wait 100 ns for global reset to finish

always

#10 Clock = !Clock;

// Add stimulus here

endmodule
D-FF:
`timescale 1ns / 1ps
module dff(d,clk,reset,q);
input d;
input clk;
input reset;
output q;
// output qbar;
reg q;
// reg qbar;
always @(posedge reset or negedge clk)
begin
if (reset)
q <= 0'b0;
else
q <= d;
// qbar <= !q;
end

endmodule

D-FF_TB:
`timescale 1ns / 1ps
module dff_tb;

// Inputs
reg d;
reg clk;
reg reset;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

dff uut (
.d(d),
.clk(clk),
.reset(reset),
.q(q)
);

initial begin
// Initialize Inputs
d = 0;
clk = 0;
reset = 0;

#20 reset = 1;
#70 reset = 0;
#100 d = 1;
#170 d = 0;
#270 d = 1;
#300 reset = 1;
#320 reset = 0;
end

always
#10 clk = !clk;
endmodule

JKMS:
`timescale 1ns / 1ps

module jk_ff(j,k,clk,q,qbar);

input j,k,clk;
output q,qbar;

wire clkbar,a,b,c,d,e,f;

not_gate n1 (clk,clkbar);

nand_gate g1 (qbar,a,q);
nand_gate g2 (q,b,qbar);

nand_gate g3 (c,clkbar,a);
nand_gate g4 (d,clkbar,b);

nand_gate g5 (e,d,c);
nand_gate g6 (f,c,d);

assign e = ~(j & clk & qbar);

assign f = ~ (k & clk & q);

endmodule

JKMDFF_tb:
`timescale 1ns / 1ps

module jkms_tb;

// Inputs
reg j;
reg k;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

jk_ff uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
 j = 0;
k = 0;
clk = 0;

#100 j = 1;
#200 j = 0;
#250 k = 1;
#400 j = 1;

end
always
#20 clk = ~clk;

endmodule

NAND:
`timescale 1ns / 1ps

module nand_gate(a,b,c);

input a;
input b;
output c;

assign c = ~(a & b);

endmodule

NAND_TB:
`timescale 1ns / 1ps

module nand_tb;

// Inputs
reg a;
reg b;

// Outputs
wire c;

// Instantiate the Unit Under Test (UUT)

nand_gate uut (
.a(a),
.b(b),
.c(c)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
end
 always
begin
#20 a = !a;
#40 b = !b;
end
endmodule

TRANSCRIPT:
# Reading C:/Modeltech_6.1f/tcl/vsim/pref.tcl
# // ModelSim SE 6.1f May 12 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# OpenFile "C:/IMS/verilog/Nand Gate/Source Code/nand_tb.v"

NOT GATE:
`timescale 1ns / 1ps
module not_gate(
input a,
output b
);

assign b = !a;
endmodule

NOT_tb:
`timescale 1ns / 1ps

module not_tb;

// Inputs
reg a;

// Outputs
wire b;

// Instantiate the Unit Under Test (UUT)

not_gate uut (
.a(a),
.b(b)
);

initial begin
// Initialize Inputs
a = 0;
#50 a = 1;
#150 a = 0;
#250 a = 1;
 end

endmodule

NOR:
`timescale 1ns / 1ps
module nor_gate(
input a,
input b,
output c
);

assign c = ~(a | b);

endmodule

NOR_tb:
`timescale 1ns / 1ps

module nor_tb;

// Inputs
reg a;
reg b;

// Outputs
wire c;

// Instantiate the Unit Under Test (UUT)

nor_gate uut (
.a(a),
.b(b),
.c(c)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
end

always
begin
#20 a = !a;
#40 b = !b;
end

endmodule

PARALLEL_ADDER:
`timescale 1ns / 1ps
module parallel_adder(a,b,cin,sum,cout);
input [3:0] a;
input [3:0] b;
 input cin;
output cout;
output [3:0] sum;

assign {cout,sum} = a + b + cin;

endmodule

PARALLEL_ADDER_TB:
`timescale 1ns / 1ps

module parallel_adder_tb;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)

parallel_adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
end
always
begin
#10 a = a + 1'b1;
#20 b = b+1'b1;
#320 cin = !cin;

end

endmodule

SERIAL_ADDER:
`timescale 1ns / 1ps
// serial adder module with no latency

module serial_adder(clk,rst,a,b,out);
input wire clk,rst,a,b;
//output reg out;
output wire out;
reg carry_reg, a_reg, b_reg;
wire carry, out_wire;

// full adder with registered carry that cycles back in

fulladder fa1(.a(a),.b(b),.cin(carry_reg),.sum(out),.cout(carry));

always @(posedge clk or posedge rst)

begin
if(rst)
begin
carry_reg <= 0;
end
else
begin
carry_reg <= carry;
end
end

endmodule

SERIAL_ADDER_TB:
`timescale 1ns / 1ps

module serialadder_tb;

// Inputs
reg clk;
reg rst;
reg a;
reg b;

// Outputs
wire out;

// Instantiate the Unit Under Test (UUT)

serial_adder uut (
.clk(clk),
.rst(rst),
.a(a),
.b(b),
.out(out)
);

initial begin
// Initialize Inputs
clk = 0;
rst = 0;
a = 0;
b = 0;

#50 rst = 1;
#70 rst = 0;
#100 a = 1;
#200 b = 1;
 end
always
#10 clk = ~clk;
endmodule

SRFF:
`timescale 1ns / 1ps
module sr_ff(
input s,
input r,
output q,
output qbar
);

wire sbar,rbar;

not_gate g3 (s,sbar);
not_gate g4 (r,rbar);

nand_gate g1 (sbar,qbar,q);
nand_gate g2 (rbar,q,qbar);

endmodule

SRFF_TB:
`timescale 1ns / 1ps

module srff_tb;

// Inputs
reg s;
reg r;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)

sr_ff uut (
.s(s),
.r(r),
.q(q),
.qbar(qbar)
);

initial begin
// Initialize Inputs
s = 0;
r = 0;

#50 s = 1;
#100 s = 0;
#200 r = 1;
#400 s = 1;
 end

endmodule

T_FF:
`timescale 1ns / 1ps
module T_FF(
input clk,
input reset,
input tin,
output q
);

wire t;

dff c1(t,clk,reset,q);
not_gate c2(q,t);

endmodule

T_FF_TB:
`timescale 1ns / 1ps

module tff_tb;

// Inputs
reg clk;
reg reset;
reg tin;

// Outputs
wire q;

// Instantiate the Unit Under Test (UUT)

T_FF uut (
.clk(clk),
.reset(reset),
.tin(tin),
.q(q)
);

initial begin
// Initialize Inputs
clk = 0;
reset = 0;
tin = 0;

#20 reset = 1;
#70 reset = 0;
#100 tin = 1;
#170 tin = 0;
#270 tin = 1;
#300 reset = 1;
#320 reset = 0;
end
 always
#10 clk = !clk;

endmodule