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    MAC

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    MAC

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    2 views2 pages

    MAC

    Uploaded by

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    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    module mac (

    input wire clk,


    input wire reset,
    input wire [3:0] a,
    input wire [3:0] b,
    output reg [7:0] acc_out
    );

    // Multiply and accumulate on positive clock edge


    always @(posedge clk or posedge reset) begin
    if (reset) begin
    acc_out <= 8'b0; // Reset accumulator to 0
    end else begin
    acc_out <= acc_out + a * b; // Perform MAC operation
    end
    end
    endmodule

    `timescale 1ns / 1ps

    module tb_mac;
    reg clk;
    reg reset;
    reg [3:0] a;
    reg [3:0] b;
    wire [7:0] acc_out;

    // Instantiate the MAC unit


    mac uut (
    .clk(clk),
    .reset(reset),
    .a(a),
    .b(b),
    .acc_out(acc_out)
    );

    // Clock generation with 10ns period


    always begin
    #5 clk = ~clk;
    end

    initial begin
    // Initialize inputs
    clk = 0;
    reset = 1;
    a = 4'd1;
    b = 4'd2;

    // Apply reset pulse


    #10 reset = 0;
    // Test Case 1
    a = 4'd3; b = 4'd4; #10;
    $display("At time=%t, a=%d, b=%d, acc_out=%d", $time, a, b, acc_out);

    // Test Case 2
    a = 4'd5; b = 4'd6; #10;
    $display("At time=%t, a=%d, b=%d, acc_out=%d", $time, a, b, acc_out);

    // Test Case 3
    a = 4'd7; b = 4'd8; #10;
    $display("At time=%t, a=%d, b=%d, acc_out=%d", $time, a, b, acc_out);

    // Finish simulation
    $finish;
    end

    // Monitor changes in acc_out for debugging


    initial begin
    $monitor("Time=%t | a=%d | b=%d | acc_out=%d", $time, a, b, acc_out);
    end
    endmodule

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