UNIVERSITY OF CALIFORNIA

Los Angeles

Low-Power Low-Jitter On-Chip Clock Generation

A dissertation submitted in partial satisfaction of the

requirements for the degree Doctor of Philosophy

in Electrical Engineering

by

Mozhgan Mansuri

2003
The dissertation of Mozhgan Mansuri is approved.

_________________________________________
Majid Sarrafzadeh

_________________________________________
Mau-Chung Frank Chang

_________________________________________
Behzad Razavi

_________________________________________
Chih-Kong Ken Yang, Committee Chair

University of California, Los Angeles

2003

ii
Dedication

To my parents

iii
Table of Contents

Dedication ......................................................................................................................... iii

Table of Contents ............................................................................................................. iv

List of Figures.................................................................................................................. vii

List of Tables .................................................................................................................... xi

Acknowledgments ........................................................................................................... xii

1. Introduction..................................................................................................................1
1.1 Motivation...............................................................................................................2
1.2 Organization............................................................................................................6

2. Phase-Locked Loop Fundamentals ............................................................................9

2.1 PLL Definition ......................................................................................................10
2.2 PLL Components ..................................................................................................11
2.2.1 Voltage-Controlled Oscillator (VCO) ........................................................12
2.2.2 Frequency Divider ......................................................................................12
2.2.3 Phase Detector or Phase-Frequency Detector.............................................13
2.2.4 Charge-Pump and Loop Filter ....................................................................14
2.3 Delay-locked Loops ..............................................................................................15
2.4 Loop Characteristics .............................................................................................17
2.5 Noise and Power Considerations ..........................................................................21

iv
 2.5.1 Device Electronic Noise .............................................................................22
2.5.2 Supply or Substrate Noise...........................................................................23
2.5.3 Noise Sensitivity Metric .............................................................................23
2.6 Summary ...............................................................................................................24

3. Jitter Optimization Based on PLL Design Loop Parameters ................................26

3.1 Definitions of Jitter ...............................................................................................27
3.2 Previous Work ......................................................................................................28
3.3 Noise Sources in a PLL ........................................................................................29
3.4 Jitter Calculation Model........................................................................................31
3.4.1 PLL Noise Transfer Function (NTF) ..........................................................32
3.5 Output Jitter of PLL ..............................................................................................34
3.5.1 Jitter due to VCO Noise..............................................................................35
3.5.2 Jitter due to Clock Buffer Noise .................................................................40
3.5.3 Jitter due to Input Clock Noise ...................................................................41
3.6 PLL Design with Adjustable Loop Parameters ....................................................44
3.7 Experimental Methods and Results ......................................................................46
3.7.1 Verification of Jitter Analysis due to VCO Noise ......................................46
3.7.2 Verification of Jitter Analysis due to Input Clock Noise............................52
3.8 Summary ...............................................................................................................53

4. Methodology for On-Chip Adaptive Jitter Minimization in PLLs .......................55

4.1 Overview...............................................................................................................56
4.2 Jitter Detection Circuits and Architectures ...........................................................63
4.2.1 PLL Design with Adjustable Loop Parameters ..........................................63
4.2.2 On-chip Jitter Measurement Architectures .................................................65
4.3 Jitter Minimization Algorithms and Measurements .............................................68
4.3.1 Measurement Setup.....................................................................................68
4.3.2 Measurement Uncertainty...........................................................................70
4.3.3 Jitter Minimization Algorithms ..................................................................72
4.4 Design Considerations ..........................................................................................78
4.5 Summary ...............................................................................................................80

5. Design of PLL Components ......................................................................................82

5.1 Proposed PLL Block Diagram ..............................................................................83
5.2 Design of a Voltage-Controlled Oscillator ...........................................................84
5.2.1 Previous State-of-the-Art VCO Designs.....................................................85
5.2.2 Proposed VCO Design................................................................................87

v
 5.3 Loop Filter ............................................................................................................92
5.3.1 Proposed Loop Filter Design ......................................................................94
5.4 Phase-Frequency Detector ....................................................................................97
5.4.1 Conventional PFD Design ..........................................................................97
5.4.2 Pass-Transistor PFD Design .....................................................................100
5.4.3 Latch-Based PFD Design..........................................................................101
5.4.4 Simulated Transfer Curve of PFDs...........................................................104
5.5 Measurement Results ..........................................................................................106
5.6 PLL Performance Comparison ...........................................................................112
5.7 Summary .............................................................................................................114

6. Design of Clock Buffer ............................................................................................116

6.1 Concept of Noise Compensation ........................................................................117
6.2 Design Implications ............................................................................................119
6.2.1 Design of the Compensator Circuit ..........................................................120
6.2.2 Bias Circuit for Vgap ................................................................................123
6.2.3 Performance Sensitivity to PVT ...............................................................125
6.3 Measurement Results ..........................................................................................127
6.4 Summary .............................................................................................................129

7. Conclusion ................................................................................................................130

Appendices......................................................................................................................135

Bibliography ...................................................................................................................144

vi
List of Figures

Figure 1.1 Clock frequency versus technology generation ...........................................2

Figure 1.2 The block diagram of high-speed parallel link ............................................4
Figure 1.3 Clock distribution networks: (a) trees, (b) grids ..........................................5
Figure 1.4 Distributed synchronous clocking with multiple PLLs ...............................5
Figure 2.1: Basic block diagram of a PLL ...................................................................10
Figure 2.2: Individual blocks in a PLL.........................................................................11
Figure 2.3: A five-stage ring oscillator ........................................................................12
Figure 2.4: Operation of a PFD: (a) fref=fCK, fref#fCk and (b) fref>fCK .................14
Figure 2.5: Block diagram of a DLL ............................................................................15
Figure 2.6: Representation of PLL individual blocks in s-domain ..............................17
Figure 2.7: Magnitude and phase of the open-loop transfer function for (a) a second-or-
der PLL, (b) a third-order PLL ..................................................................18
Figure 2.8: Closed-loop frequency response of: (a) an ideal second-order PLL, (b) a
sampling third-order PLL ..........................................................................21
Figure 3.1: Timing jitter ...............................................................................................27
Figure 3.2: Tracking jitter at PLL output clock............................................................28
Figure 3.3: Noise sources in a PLL ..............................................................................30
Figure 3.4: Timing jitter as a function of noise psd, Sf(f)............................................31
Figure 3.5: Block diagram of a second-order PLL.......................................................32
Figure 3.6: Loop transfer function from each noise source to PLL output ..................34
Figure 3.7: Short-term jitter behavior with different f-3dB and z due to (a) VCO and (b)
clock buffering noise. ((1) f-3dB = 5.5% fref, z = 0.2 (2) f-3dB = 6.4% fref,

vii
 z = 0.65 (3) f-3dB = 11.4%fref, z = 1.63)..................................................36
Figure 3.8: Long-term jitter (due to VCO noise) as a function of: (a) loop bandwidth,
(b) loop damping factor .............................................................................37
Figure 3.9: Comparison of long-term jitter (due to VCO noise) in: (a) 2nd, 3rd order
loop (b) without loop delay and c) with loop delay ...................................39
Figure 3.10: PLL bandwidth (at minimum jitter) as a function of 3rd pole frequency and
PLL loop delay...........................................................................................40
Figure 3.11: Output clock jitter (due to input clock noise) behavior vs. input clock jitter
behavior .....................................................................................................42
Figure 3.12: Output to input jitter ratio behavior of a 2nd-order loop as a function of: (a)
loop bandwidth, (b) loop damping factor ..................................................43
Figure 3.13: Comparison of long-term jitter (due to white noise at PLL input) in: (a) 2nd,
3rd order loop (b) without loop delay and (c) with loop delay..................44
Figure 3.14: An adaptive bandwidth PLL with tunable loop parameters ......................45
Figure 3.15: Die photograph of the PLL ........................................................................46
Figure 3.16: Measurement technique in time domain, referenced to reference clock ...47
Figure 3.17: Measured and calculated tracking jitter as wz is reduced in constant KLoop
....................................................................................................................48
Figure 3.18: Measurement technique for calculating PLL loop transfer function .........50
Figure 3.19: Measured PLL loop transfer function (@ 700MHz reference clock) at a con-
stant ICPintegral (constant KLoop) ...........................................................50
Figure 3.20: Measurement technique in time domain, referenced to output clock ........51
Figure 3.21: Measured and calculated short-term jitter (@ 700MHz reference clock) for
four different loop parameters ...................................................................51
Figure 3.22: Output jitter (due to input clock noise) behavior for three different PLL loop
parameters: (a) measurement results, (b) analytical results ((1) Input jitter
(2) z = 0.2, f-3dB = 39MHz (3) z = 0.65, f-3dB = 45MHz (4) z = 1.63, f-3dB
= 80MHz)...................................................................................................52
Figure 4.1: The PLL block diagram with VCO and input noise ..................................56
Figure 4.2: Loop transfer functions from VCO and input clock noise to the PLL output
....................................................................................................................57
Figure 4.3: Behavior of output clock jitter due to VCO noise for various loop parame-
ters: (a) 3-D, (b) contour ............................................................................59
Figure 4.4: Behavior of output clock jitter due to input noise for various loop parame-
ters: (a) 3-D, (b) contour ............................................................................60
Figure 4.5: Behavior of output clock jitter due to both VCO and input noise for various
loop parameters: (a) 3-D, (b) contour ........................................................62
Figure 4.6: A PLL architecture with adjustable loop parameters using adjustable R and

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 ICP .............................................................................................................64
Figure 4.7: Jitter measurement with a flash TDC architecture.....................................65
Figure 4.8: Jitter measurement with a dead-zone window establishment ....................66
Figure 4.9: PLL die photograph ...................................................................................69
Figure 4.10: Test setup for the jitter measurement and optimization.............................70
Figure 4.11: (a) Measured percentage hits distribution for one set of PLL loop parameters
for N=500 and N=5000, (b) standard deviation of measured percentage hits
....................................................................................................................71
Figure 4.12: Jitter measurement contours (due to VCO noise) for all loop parameters
with (a) constant dead-zone width and measuring hits (percentage), (b) con-
stant 4% measured hits and measuring dead-zone width ..........................73
Figure 4.13: Jitter measurement contours (due to input noise) for all loop parameters with
constant 4% measured hits and measuring dead-zone width.....................75
Figure 4.14: Flow chart of jitter minimization algorithm ..............................................77
Figure 4.15: Measured minimum jitter due to the sum of VCO and input noise for (a)
3000hits, (b) 300hits ..................................................................................78
Figure 5.1: The proposed PLL architecture..................................................................84
Figure 5.2: Power-supply regulated VCO ....................................................................85
Figure 5.3: VCO with a feedback cascode using OTA ................................................86
Figure 5.4: Voltage-controlled oscillator with a noise-canceling circuit .....................87
Figure 5.5: Quadrature pseudo-differential current-controlled oscillator (CCO) ........88
Figure 5.6: Simulated V-I converter gain characteristic across process corners..........89
Figure 5.7: VCCO response of V-I converter to -10% VDD step inserted at t=2ns ....91
Figure 5.8: Conventional loop filter .............................................................................93
Figure 5.9: Implementing the PLL stabilizing zero with two charge-pump currents and
a regulator ..................................................................................................94
Figure 5.10: Proposed loop filter architecture................................................................94
Figure 5.11: Charge-pump current circuit ......................................................................95
Figure 5.12: Loop stabilizing zero with a 4-bit controller (n=4)....................................95
Figure 5.13: (a) Linear PFD architecture, (b) PFD state diagram ..................................97
Figure 5.14: (a) Ideal PFD characteristic. (b) Nonideal linear PFD characteristic. (c) PFD
nonideal behavior due to nonzero reset delay............................................99
Figure 5.15: Pass-transistor DFF PFD architecture......................................................101
Figure 5.16: (a) Behavior of a latch-based PFD, including the description of the nonideal
behavior origin. (b) characteristic of a latch-based PFD .........................102
Figure 5.17: Latch-based PFD architecture..................................................................103
Figure 5.18: Characteristics of three PFDs at 435MHz ...............................................105
Figure 5.19: Simulated frequency acquisition..............................................................105

ix
Figure 5.20: PLL and clock buffer die photograph ......................................................106
Figure 5.21: Measured and simulated VCO gain .........................................................107
Figure 5.22: PLL output jitter histogram at 1GHz .......................................................107
Figure 5.23: Measured sensitivity of VCO output clock frequency to static and dynamic
supply noise .............................................................................................109
Figure 5.24: Die photograph of three different PFDs implemented in a PLL..............110
Figure 5.25: Measured frequency acquisition ..............................................................111
Figure 6.1 (a) Ideal compensation of supply-induced inverter delay variation, (b) pro-
posed compensator inverter .....................................................................118
Figure 6.2 (a) Delay variation of compensated inverter due to VSG variation, (b) delay
sensitivity of compensator circuit, normalized to delay sensitivity of an in-
verter ........................................................................................................120
Figure 6.3 Behavior of normalized delay sensitivity of compensator circuit due to VSG
(VDD) variation as a function of: (a) PMOS capacitor, (b) PMOS resistor..
..................................................................................................................121
Figure 6.4 Supply-induced delay variation of: (1) uncompensated inverter, (2) com-
pensated inverter with inverter’s VDD held constant and (3) compensated
inverter .....................................................................................................122
Figure 6.5 Bias circuit generating Vgap....................................................................123
Figure 6.6 Sensitivity of supply-induced delay variation of compensated inverter due
to Vgap offset...........................................................................................124
Figure 6.7 Delay variation of compensated clock buffer over temperature as VDD var-
ies £ ±10% ...............................................................................................125
Figure 6.8 Delay variation of compensated clock buffer across the corners as VDD var-
ies £ ±10% ...............................................................................................126
Figure 6.9 Five stages of fanout of four (FO-4) compensated inverters (n=5) .........127
Figure 6.10 Measured supply-induced delay variation of uncompensated (--) and com-
pensated clock buffer ...............................................................................128

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List of Tables

Table 3.1: Tracking jitter (in ps) for different loop parameters (fref = 700MHz) ......48
Table 5.1: PFDs performance summary ...................................................................105
Table 5.2: PLL performance summary (1)................................................................106
Table 5.3: PLL performance summary (2)................................................................107
Table A.1: Comparison of estimated tracking jitter (by 2nd-order analysis) with mea-
sured tracking jitter (fref = 700MHz) ......................................................131

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Acknowledgments

During my study and research at UCLA, I have been extremely blessed by God to
meet and collaborate with so many people that were so supportive and helpful in this
research.

I would like to deeply thank my advisor, professor Ken Yang, for his continuos
support, encouragement and help. He has been my best research advisor and it has been a
privilege collaborating and working with him these past four years. He has been source of
ideas and knowledge, yet, his wisdom allowed me to direct my research successfully.

I would also like to thank professor Behzad Razavi for his support and useful
technical discussions. I would like to extend my appreciation to him, professor Frank
Chang and professor Majid Sarrafzadeh for serving on my committee and providing me
with their fruitful comments.

I would like to express my deepest appreciation to my family. In particular, I am

always indebted to my parents for their constant support, love and patience. Without their
continued support, I would have not accomplished this effort. I would like to thank my
two brothers for being so supportive and encouraging throughout years of my study.

xii
 It has been a pleasure to work with so many talented people in UCLA. I wish to
thank, in particular, Siamak Modjtahedi, who generously provided me with his help and
useful discussions, Jackie Wong and Hamid Hatamkhani, with whom I collaborated in the
design of low-power links, and Ali Hadiashar, who helped me with the development of
run-time algorithm for jitter optimization. I would also like to thank Dean Liu for his
collaboration and great help on the design of phase-frequency detectors.

Also, I am greatly thankful to my friends for their constant support and friendship.
I would like to thank, in particular, Hamid Rafati, Esmaeil Heidari, Rahim Bagheri, Ali
Karimi, Omid Oliaei, Alireza Razzaghi, Vladimir Stojanovic, Saeed Chehrazi and Pejman
Kalkhoran for countless discussions.

I wish to thank National semiconductor, Intel corporation and UCMicro 02-102 for
fabrication and their support. Also I would like to thank Makoto Murata for his great help
in wire bonding and Dorothy Tarkington for her wonderful help in purchasing the lab
equipment and components.

xiii
 VITA

1972 Born, Tehran, Iran

1995 B.Sc., Electrical Engineering
Sharif University of Technology
Tehran, Iran
1997 M.Sc., Electrical Engineering
Sharif University of Technology
Tehran, Iran
1997-1999 Design Engineer
KCR company
Tehran, Iran
1999-2003 Graduate Researcher
Department of Electrical Engineering
University of California, Los Angeles

PUBLICATIONS AND PRESENTATIONS

M. Mansuri and CK.K. Yang, “A Low-Power Low-Jitter Adaptive Bandwidth PLL and
Clock Buffer,” Submitted for publication, IEEE, Journal of Solid-State Circuits, Novem-
ber 2003

M. Mansuri, A. Hadiashar, and CK.K. Yang, “Methodology for On-chip Adaptive Jitter
Minimization in Phase-Locked Loops,” Submitted for publication, IEEE, Journal of
Transactions on Circuits and Systems II, November 2003

xiv
KL.J. Wong, M. Mansuri, H. Hatamkhani and CK.K. Yang, “A 27-mW 3.6-Gb/s I/O
Transceiver,” Proceedings of Symposium on VLSI Circuits, pp. 99-102, Japan, June 2003

M. Mansuri and CK.K. Yang, “A Low-Power Low-Jitter Adaptive Bandwidth PLL and
Clock Buffer,” ISSCC Digest of Technical Papers, pp. 430-431, San Francisco, CA, Feb-
ruary 2003

M. Mansuri and CK.K. Yang, “Jitter Optimization Based on Phase-Locked Loop Design
Parameters,” IEEE, Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1375-1382,
November 2002

M. Mansuri, D. Liu and CK.K. Yang, “Fast Frequency Acquisition Phase-Frequency

Detectors for GSa/s Phase-Locked Loops,” IEEE, Journal of Solid-State Circuits, vol. 37,
no. 10, pp. 1331-1334, October 2002

M. Mansuri and CK.K. Yang, “Jitter Optimization Based on Phase-Locked Loop Design
Parameters,” ISSCC Digest of Technical Papers, pp. 138-139, San Francisco, CA, Febru-
ary 2002

M. Mansuri, D. Liu and CK.K. Yang, “Fast Frequency Acquisition Phase-Frequency

Detectors for GSa/s Phase-Locked Loops,” Proceedings of the European Solid-State Cir-
cuits Conference, Vienna, September 2001

xv
 ABSTRACT OF THE DISSERTATION

Low-Power Low-Jitter On-Chip Clock Generation

by

Mozhgan Mansuri

Doctor of Philosophy in Electrical Engineering

University of California, Los Angeles, 2003

Professor Chih-Kong Ken Yang, Chair

Phase locked-loops (PLLs) are widely used to generate well-timed on-chip clocks

in high-performance digital systems. Any timing jitter or phase noise significantly

degrades the performance of these systems, especially as operating frequency increases.

Switching activity in large digital systems introduces power supply or substrate noise

which perturb the more sensitive blocks in a PLL, in particular, voltage-controlled

oscillators (VCOs) and clock buffers.

xvi
 Power dissipated by PLLs is often a small fraction of total active power. However,

during sleep modes where the PLL must remain in lock, it can be a significant fraction of

dissipated power. Also, for some applications such as high speed parallel links and

distributed synchronous clocking, multiple PLLs are employed to minimize the timing

uncertainty. Therefore, demand for low-power PLLs has been increasing. The low-power

requirement makes the design of a low-jitter PLL even more challenging.

This research describes the design of a fully-integrated low-jitter PLL for low-

power applications. To achieve the low-jitter performance, this work proposes jitter

minimization methods at both system and circuit levels.

At the system level, this work investigates the effects of PLL design parameters,

such as bandwidth and peaking in the frequency response, on timing jitter of PLL output

clock. The analysis includes several common noise sources in a PLL and develops an

intuition for selecting design parameters to obtain minimum output jitter based on the

dominant noise source. The proposed PLL is equipped with digitally-controllable loop

parameters that independently adjusts the loop parameters. Based on jitter analysis, a

methodology for on-chip adaptive jitter minimization in PLLs is developed. The proposed

method measures the output jitter and adjusts the PLL loop parameters toward minimizing

the jitter by a closed loop control system. The experimental results verify the success of

the proposed method in minimizing jitter to within 5ps of the minimum long-term peak-

to-peak jitter.

xvii
 At the circuit level, two new supply rejection techniques for VCOs and clock

buffers are developed. Both methods demonstrate the delay sensitivity of ≤0.1%-delay/%-

VDD due to both static and dynamic supply noise. While the jitter performance is

comparable with prior state-of-art work, the proposed VCO and clock buffer consume less

power with smaller area than previous designs. The VCO is designed to operate over a

wide frequency range and has a linear voltage-to-frequency gain. The PLL is designed

with scaling loop parameters that track over a 10x frequency range of the VCO and allow

the adaptive loop bandwidth. The PLL is implemented in 0.25-µm CMOS technology and

consumes 10mW from a 2.5-V supply.

xviii
Chapter 1

Introduction

High-performance digital systems use clocks to sequence operations and

synchronize between functional units and between ICs. Clock frequencies and data rates

have been increasing with each generation of processing technology and processor

architecture. Figure 1.1 shows the clock frequency versus technology generation

according to 2002 ITRS1. Within these digital systems, well-timed clocks are generated

with phase-locked loops (PLLs) and then distributed on-chip with clock buffers. The rapid

increase of the systems’ clock frequency poses challenges in generating and distributing

the clock with low uncertainty and low power. This research presents innovative

techniques at both system and circuit levels that minimize the clock timing uncertainty

with minimum power and area overhead.

1. International technology roadmap for semiconductors

1
 7

Clock frequency (GHz)

5

1
130 120 110 100 90 80 70
Technology (nm)

Figure 1.1 Clock frequency versus technology generation

1.1 Motivation
A PLL is essentially a feedback loop that locks the on-chip clock phase to that of

an input clock or signal. Because the on-chip clock toggles a large capacitive load, a series

of clock buffers efficiently increases the drive strength of the PLL output to drive the load.

High-performance PLLs and clock buffers are widely used within a digital system for two

purposes: clock generation, and timing recovery.

For clock generation, since off-chip reference frequencies are limited by the

maximum frequency of a crystal frequency reference1, a PLL receives the reference clock

and multiplies the frequency to the multi-gigahertz operating frequency. The high-

1. Typically from tens of MHz to a few hundred of MHz

2
frequency clock is then driven to all parts of the chip. Timing recovery pertains to the data

communication between chips. As data rates increase to satisfy the increase in on-chip

processing rate, the phase relationship between the input data and the on-chip clock is not

fixed. To reliably receive the high-speed data, a PLL locks the clock phase that samples

the data to the phase of the input data.

Timing uncertainty impacts the performance of both applications. In order to

maintain proper synchronization, large timing uncertainty would result in lower frequency

of operation. Jitter is due to both intrinsic random noise (i.e. thermal noise and flicker

noise), and systematic supply/substrate noise. Particularly in large digital systems,

switching activity introduces power-supply or substrate noise which perturbs the PLL

elements and clock buffers. Supply or substrate noise is the dominant source of jitter in

these systems. This research focusses on the design of the most sensitive blocks in a PLL

and clock buffer with high immunity to supply/substrate noise. The research also

represents a powerful noise-filtering technique that minimizes jitter through adjusting the

key loop parameters of a PLL based on the dominant noise source in the PLL.

The power performance of a PLL is a growing concern for many applications.

Power dissipated by PLLs is often a small fraction of the total active power. However, it

can be a significant fraction of the power dissipated in the sleep mode where the PLL must

remain in lock. Also, as operating clock frequency of digital systems is increasing, the

systems become less tolerable to clock skew. There is an increasing demand for using

distributed phase-locking systems such as PLLs for applications such as high-speed

parallel links [8]-[10] and distributed synchronous clocking [1]-[7]. In both applications,

3
multiple PLLs are employed to reduce the timing uncertainty across the entire system with

the cost of power and area overhead due to each PLL.

The block diagram of a high-speed parallel link is shown in Figure 1.2. To

CKref PLL0
data0

PLL1
data1

dataN

PLLM
ref

Figure 1.2 The block diagram of high-speed parallel link

increase the bandwidth, the architecture utilizes a set of parallel data signals. The

synchronization is achieved through transmitting a reference clock with the parallel data

signals. In the receiver, the on-chip clock is locally generated by multiple PLLs from the

transmitted clock to recover the data. Locally distributed PLLs reduces the timing

uncertainty and minimizes bit-error-rate (BER).

In conventional clock distribution networks, a well-aligned generated on-chip

clock is distributed to many locations on the chip over a tree-like or grid-like network

(Figure 1.3-(a) or (b)) with repeaters at necessary intervals. These networks are passive

because it does nothing to reduce the uncertainty of the clock delivered to the sequential

elements. As the clock frequency goes up, the number of required repeaters increases and

shielding the interconnect segments becomes more difficult; thus, the timing uncertainty

inevitably increases. Skew compensation [13]-[14] is used to reduce the delay mismatches

4
introduced during fabrication. However, this technique does not suppress jitter. A possible

solution to the jitter accumulation problem is distributed synchronous clocking [1]-[7].

Driver

Root

Leaf

(a) (b)
Figure 1.3 Clock distribution networks: (a) trees, (b) grids

In the distributed synchronous clocking, independent PLLs generate the clock

signal at multiple nodes across the chip (Figure 1.4). Phase detectors (PDs) at boundaries

produce error signals to adjust frequency of the node PLL. Within the tree, the clocks will

be driven as sinusoidal signals without intermediate buffering; thus, the clocks at each

terminal have a small swing due to resistive losses. With locally generated clocks, there

are no full swing clock lines to couple in jitter. Also, since the clock is generated at each

node, jitter does not accumulate with distance from the clock source.

Master Local
PLL
PLL Clock
Region PD

Figure 1.4 Distributed synchronous clocking with multiple PLLs

5
 Since many of these phase-locking systems are required to be integrated within a

single chip, the overall power and area overhead of a single phase-locking circuit are key

constraints. A phase-locking system is not necessarily a PLL, however, it composes of

similar components as a PLL. The power and area constraints make the design of a low-

jitter PLL even more challenging due to the trade-off between low-jitter and low-power

(and low-area) design techniques. This research presents new filtering techniques in the

design of PLL components and loop parameters to overcome the low-power and low-area

constraints. The proposed filtering techniques minimize the clock timing uncertainty

while introducing minimum power and area overhead.

1.2 Organization
This thesis is composed of seven chapters. The functioning and components of a

phase-locked loop (PLL) are described in Chapter 2. Then, the two common PLL

architectures, delay-line based PLL (DLL) and oscillator-based PLL (PLL), are discussed

and compared. The noise and power constraints associated with the design of a PLL are

the next subject of the chapter. Noise minimization techniques at both system and circuit

levels are the main subjects of the next four chapters.

At the system level, the timing jitter of the PLL output clock is minimized by

proper design of PLL loop parameters, such as bandwidth and peaking in the frequency

response. The jitter minimization relies on the fact that a PLL is a closed-loop system and

filters each noise source in the PLL based on the transfer function from the correspondent

noise source to the PLL output. For instance, a high-bandwidth PLL can track the phase of

6
a low-noise input clock and filter out voltage-controlled oscillator (VCO) noise.

Conversely, a low-bandwidth PLL filters a noisy input clock. The goal is to explore an

intuition for selecting design parameters to obtain the minimum output jitter based on the

dominant noise source. Chapter 3 reviews jitter definitions and major timing jitter sources

in a PLL. The relationship between the jitter, the power spectral density of each noise

source and the correspondent PLL noise transfer function is extracted next. Based on the

extracted equations, the sensitivity of jitter to PLL bandwidth and peaking in loop

frequency response is derived. Finally, a PLL with tunable loop parameters is used to

experimentally minimize jitter and verify the jitter analysis.

The proper design of PLL loop parameters for minimum output jitter performance

requires knowledge of the dominant noise source in the PLL. For many systems, the

magnitude of the noise sources are not well known which makes the design of loop

parameters complicated. Chapter 4 develops a methodology for on-chip adaptive jitter

minimization in PLLs. The algorithm functions during system operation and minimizes

jitter as noise source conditions vary. The chapter shows that since the total jitter has only

one minimum that is global, a gradient-descent algorithm suffices to converge to the

minimum. The chapter, then, describes the circuit components necessary that dynamically

measure and minimize jitter.

In addition to jitter minimization technique at the system level, this research

explores designs of low-noise PLL components. Although both device noise and supply/

substrate noise are present, supply/substrate noise is the dominant noise source in digital

systems which perturbs the most sensitive blocks such as voltage-controlled oscillators

7
(VCOs) and clock buffers. To achieve a high-noise performance requires design of VCOs

and clock buffers with high immunity to supply/substrate noise.

Design of the PLL components are discussed in Chapter 5, starting with the design

of a VCO. The new noise filtering technique is presented that achieves similar noise

performance with improved power and area performance comparing with state-of-the-art

designs. The chapter presents a self-biased charge-pump current and loop filter, next, that

allows the PLL to operate over a wide frequency range with an adaptive bandwidth in a

constant phase margin. The design of a high-performance phase-frequency detector is

introduced next that has lower power consumption and larger lock-in range than

conventional PFDs.

Clock buffers with improved supply sensitivity of buffer elements are introduced

in Chapter 6. The design goal is to compensate the supply-induced delay variation with an

improved dynamic behavior while introducing minimum power, area and delay overhead.

The noise performance of the compensated buffer is verified with experimental results.

8
Chapter 2

Phase-Locked Loop Fundamentals

Phase-locked loops (PLLs) generate well-timed on-chip clocks for various

applications such as clock-and-data recovery, microprocessor clock generation and

frequency synthesizer. The basic concept of phase locking has remained the same since its

invention in the 1930s [20]. However, design and implementation of PLLs continue to be

challenging as design requirements of a PLL such as clock timing uncertainty, power

consumption and area become more stringent. A large part of this research focuses on the

design of a PLL for high-performance digital systems. In order to understand the

challenges and trade-off behind the design of such a PLL, this chapter provides a brief

study of phase-locked loops.

Section 2.1 provides an overview of a PLL system and briefly discusses the basic

concept of phase locking. PLL components for charge-pump PLLs are discussed in

Section 2.2. Section 2.3 discusses and compares the two possible PLL architectures: (1)

delay-line based PLL and (2) oscillator-based PLL. Study of loop characteristics and loop

9
parameters is the subject of Section 2.4. This section provides a simple analysis of the

PLL loop dynamics as a function of the loop parameters.

The noise sources present in digital systems are discussed in Section 2.5. The

chapter concludes with a summary of design goals and issues involved in the design of

PLLs for high-performance digital systems.

2.1 PLL Definition

The basic block diagram of a PLL is shown in Figure 2.1. A PLL is a closed-loop

feedback system that sets fixed phase relationship between its output clock phase and the

phase of a reference clock. A PLL tracks the phase changes that are within the bandwidth

of the PLL. A PLL also multiplies a low-frequency reference clock, CKref, to produce a

high-frequency clock, CKout.

φref, CKref
φout, CKout
Phase error Low-Pass Filter Oscillator
Detector

φfeedback, CKfeedback
Frequency Divider
:N

Figure 2.1: Basic block diagram of a PLL

The basic operation of a PLL is as follows. The phase detector (comparator)

produces an error output signal based on the phase difference between the phase of the

feedback clock and the phase of the reference clock. Over time, small frequency

differences accumulate as an increasing phase error. The difference or error signal is low-

10
pass filtered and drives the oscillator. The filtered error signal acts as a control signal

(voltage or current) of the oscillator and adjusts the frequency of oscillation to align

φfeedback with φref. The frequency of oscillation is divided down to the feedback clock by a

frequency divider. The phase is locked when the feedback clock has a constant phase error

and the same frequency as the reference clock. Because the feedback clock is a divided

version of the oscillator’s clock frequency, the frequency of oscillation is N times the

reference clock.

2.2 PLL Components

The block diagram of a charge-pump PLL is shown in Figure 2.2. A PLL

comprises of several components: (1) phase or phase-frequency detector, (2) charge-pump

current, (3) loop filter, (4) voltage-controlled oscillator, and (5) frequency divider. The

functioning of each block is briefly described below.

Divider
:N
UP ICP
Reference PD/PFD Output
VCO
Clock DN Clock
ICP R
CCP C1
Charge-Pump
Loop Filter

Figure 2.2: Individual blocks in a PLL

11
2.2.1 Voltage-Controlled Oscillator (VCO)
An oscillator is an autonomous system that generates a periodic output without any

input. A CMOS ring oscillator shown in Figure 2.3 is an example of an oscillator. So that
Vctrl (or Ictrl)

CKout

Figure 2.3: A five-stage ring oscillator

the phase of a PLL is adjustable, the frequency of oscillation must be tunable. In the

example of an inverter ring oscillator, the frequency could easily be adjusted with

controlling the supply (voltage or current) of inverters. The slope of frequency versus

control signal curve at the oscillation frequency is called voltage-to-frequency (or current-

to-frequency) conversion gain, KVCO; KVCO=dfVCO/dVctrl evaluated at fVCO. Since phase

is the integral of frequency, the output phase of the oscillator is equal to

φ VCO = ∫ KVCO ⋅ Vctrl ⋅ dt . In other words, the VCO in the frequency domain (s-domain),
φ VCO K VCO
is modeled as ------------ ( s ) = ------------- . Ideally, for the linear analysis to apply over a large
V ctrl s
frequency range, KVCO, needs to be relatively constant.

2.2.2 Frequency Divider

The PLL reference clock is generated from a crystal. The crystals typically operate

from tens to a few hundreds of MHz. On the other hand, VCOs for clocking and parallel

link applications operate at a few GHz or even ten GHz. For proper functioning of the

12
phase detector or phase-frequency detector, discussed in the next section, a frequency

divider divides down the VCO frequency to the frequency of the reference clock.

2.2.3 Phase Detector or Phase-Frequency Detector

The phase detector (PD) compares the phase difference between two input signals

and produces an error signal that is proportional to the phase difference. In the presence of

a large frequency difference, a pure phase detector does not always generate the correct

direction of phase error. Phase error accumulates rapidly and can oscillate between phase

error of >180oand <180o from cycle to cycle. The average phase detector output contains

little frequency information and no valuable phase information. Since the phase detector is

insensitive to frequency difference at the input, upon start-up when the oscillator’s

frequency divided by N1 is far from the reference frequency, the PLL may fail to lock. The

problem is known as an inadequate acquisition range of the PLL. To remedy the problem,

a phase-frequency detector (PFD) is used that can detect both phase and frequency

differences. Figure 2.4 conceptually demonstrates the operation of a PFD for two cases:

(a) the two input signals have the same frequency, and (b) one input has higher frequency

than another input. In both cases, the DC contents of PFD’s outputs, UP and DN, provide

information about phase or frequency difference.

1. Loop divide ratio

13
 Ref Ref
Ref UP CK CK
PFD
CK DN UP UP
DN DN
(a) (b)

Figure 2.4: Operation of a PFD: (a) fref=fCK, φref#φCk and (b) fref>fCK

2.2.4 Charge-Pump and Loop Filter

The charge-pump circuit comprises of two switches that are driven with UP and

DN outputs of PFD as shown in Figure 2.2. The charge-pump injects the charge into or out

of the loop filter capacitor (CCP). The combination of charge-pump and CCP is an

integrator that generates the average of UP (or DN) pulses. This average voltage adjusts

the frequency of the subsequent oscillator circuit. Since the VCO introduces another

integrator, the loop gain of a charge-pump PLL has two poles at origin; thus, the closed-

loop system is unstable. To stabilize the system, a zero, ωz = 1/RCCP, is introduced in the

loop gain by adding a resistor, R, in series with CCP.

The PFD, charge pump and filter are often modeled with a linear continuous-time

model. In reality, the PFD acts as a pulse modulator system and drives the charge-pump

for the duration of pulse width which is equal to PFD input phase difference, ∆φ. The

actual phase response is not linear because phase is cyclical. Furthermore, the phase

information is discrete, sampled at the clock reference frequency.

14
 However, a linear continuous-time approximation is often used to model the

stability of an operating point. The error due to approximation is negligible if the PLL

bandwidth is 1/10th or smaller than the reference clock frequency [79]. The reference

frequency determines the rate that PFD output is refreshed. With a linear approximation,
V ctrl I CP
Vctrl is equal to: ---------- ( s ) = -------- ⋅ F ( s ) where F(s) is the transfer function of the loop filter
∆φ 2π
1
and is equal to: F ( s ) = ------------ ⋅ ( 1 + RC CP s ) , ignoring C1 in Figure 2.2.
C CP s

2.3 Delay-locked Loops

In the previous section, the PLL components for an oscillator-based PLL

architecture are discussed. An alternative to an oscillator-based PLL is a delay-line-based

PLL or a delay-locked loop (DLL). A DLL is similar to a PLL except that a variable delay

line replaces the oscillator [21]. Thus, phase is the only state variable in a DLL while both

phase and frequency are the state variables in a PLL. The basic DLL building blocks are

shown in Figure 2.5, similar to that of a PLL. A phase detector (PD) measures the phase

Vctrl (or Ictrl)

CKref PD Low-Pass Filter

delay_in
Delay Line delay_out

Figure 2.5: Block diagram of a DLL

difference between the reference clock and the delay-line output. The error signal is low-

15
pass filtered to produce the control signal that adjusts the delay of the delay line. Note that

the delay-line input can be a separate external clock instead of the CKref.

To eliminate the phase offset in a DLL, the filter is an integrator. DLL with only a

single pole is unconditionally stable. Only at loop bandwidths close to the reference

frequency, where the loop delay and the sampling nature of the PD degrade phase margin,

is the stability a concern. In response to a noise perturbation, a PLL accumulates phase

error before correcting the error because the output phase is an integration of the

frequency change. In contrast, a DLL does not accumulate the phase error and corrects the

error by the time constant of the loop.

Although, a simple loop characteristic of a DLL is desirable, a DLL has its own

limitations. First, for clock generation, only one input clock is available so the clock is

used as the input to the delay line as well as the phase detector. Therefore, any high-

frequency jitter at the reference clock directly passes through the delay line to the DLL

output. Low-frequency jitter is tracked. This configuration results in an all-pass response

to any phase variations in a reference clock. Secondly, it is not as easy to multiply the

reference frequency [65]-[66] as a PLL. Third, delay lines usually have a finite delay

range. The limited delay range causes the loop to not lock properly. In contrast, a PLL can

filter out a noisy reference clock by lowering the PLL bandwidth. A PLL can achieve a

wide frequency range, provided that the VCO is designed to operate over a wide range.

The output frequency can be any frequency different from the reference clock frequency.

The advantages of a PLL over a DLL motivates us to focus on a design of a PLL in this

16
research. Nevertheless, the circuits and jitter reduction techniques discussed in following

chapters are applicable to DLLs because PLL and DLL architectures share many similar

components and loop characteristics.

2.4 Loop Characteristics

This section describes the dynamic behavior of the entire PLL. The s-domain

presentation of each loop element, discussed in Section 2.2, is depicted within each block

in Figure 2.6. The open-loop transfer function can be written as

:N
UP ICP
Vctrl VCO
PD/PFD φout
φref KVCO /s
KPD DN
ICP R
CCP C1

ICP/2π F(s)

Figure 2.6: Representation of PLL individual blocks in s-domain

H open ( s ) = K PFD ⋅ I CP ⁄ 2π ⋅ F ( s ) ⋅ K VCO ⁄ s where KPFD is phase-frequency detector

gain, F(s) is the loop filter transfer function and KVCO is the conversion gain of the VCO.

The open-loop transfer function for a second-order PLL (ignoring C1 in the loop filter) is

equal to:

I CP K VCO
H open ( s ) = K PFD ⋅ --------------------- ⋅ ( 1 + RC CP s ) ⋅ ------------
- ‹2.1›
2π ⋅ C CP s
2

17
This transfer function has two poles at origin and one compensating zero that guarantees

the closed-loop stability. Including the third pole, the open-loop transfer function is equal

to:

I CP K VCO
H open ( s ) = K PFD ⋅ --------------------------------------- ⋅ ( 1 + RC CP s ) ⋅ -------------------------------------------------------
- ‹2.2›
2π ⋅ ( C CP + C 1 ) 2
s ⋅ [1 + R(C C )s ]
CP 1

The magnitude and phase of the open-loop transfer functions for a second and
1 1
third-order PLL are shown in Figure 2.7. ω z = -------------- and ω p3 = ------------------------------ indicate
RC CP R ( C CP C 1 )
|Hopen(s)|.1/N

|Hopen(s)|.1/N
40dB/dec 40dB/dec

20dB/dec 20dB/dec
ωp3
0dB
ωz ω 0dB ω
ωc ωz ωc
40dB/dec
Hopen(s) Hopen(s)
ω ω

-90O -90O

-180O -180O

(a) (b)

Figure 2.7: Magnitude and phase of the open-loop transfer function for (a) a second-
order PLL, (b) a third-order PLL

the zero and third pole frequency, respectively. ωc is the open-loop unity gain frequency.

Without a compensating zero, neither a closed-loop second-order nor a closed-loop third-

18
order PLL is stable. The zero locus for an ideal second-order loop is not critical for

stability, in contrast to a third-order (or higher order) PLL.

To understand the effect of the zero and other PLL parameters on the closed-loop

behavior of the PLL, the closed-loop transfer function of a PLL from input phase to output

phase is calculated:

φ out H open ( s )
--------- ( s ) = H closed ( s ) = ---------------------------------------------
- ‹2.3›
φ in 1 + H open ( s ) ⋅ 1 ⁄ N

For a second-order PLL, the closed-loop transfer function is equal to:

φ out K Loop ⋅ ( 1 + RC CP s )
--------- ( s ) = -----------------------------------------------------------------------------------
- ‹2.4›
φ in 2
s + ( K Loop ⁄ N )RC CP s + K Loop ⁄ N

KLoop is the loop gain and is equal to:

K Loop = K PFD ⋅ K VCO ⋅ I CP ⁄ ( 2πC CP ) ‹2.5›

The closed-loop transfer function from the input phase to the output phase (Equation 2.4)

is a low-pass filter. This low-pass behavior of a PLL is desirable because it rejects input

noise frequencies higher than the PLL bandwidth. Similarly, the closed-loop transfer

function from the VCO control voltage, Vctrl, to the output phase is calculated:

φ out K VCO ⋅ s
---------- ( s ) = -----------------------------------------------------------------------------------
- ‹2.6›
V ctrl 2
s + ( K Loop ⁄ N )RC CP s + K Loop ⁄ N

This closed-loop transfer function is a band-pass filter. This band-pass filter rejects

internal noise coupled into Vctrl within the PLL bandwidth.

Filtering out noise sources by the closed-loop behavior of the PLL forms the

baseline for jitter analysis discussed in Chapter 3. Noise of the PLL’s output clock can be

19
optimally filtered by adjusting the loop bandwidth and peaking in frequency response

based on the dominant noise source. The loop bandwidth and peaking are adjustable by

varying loop parameters.

K Loop
The natural frequency, ωn, and damping factor, ζ1, are equal to ω n = -------------
- and
N
ωn
ζ = ------------- , respectively. Natural frequency is proportional to square-root of the loop gain.
2 ⋅ ωz
Since KPFD, KVCO and CCP are typically design constant parameters, the natural

frequency is proportional to square-root of the charge-pump current (Equation 2.5).

Damping factor is inversely proportional to zero frequency. By adjusting the zero

frequency (typically through the loop filter resistor, R) and charge-pump current, ζ and ωn

can be adjusted. In other words, the bandwidth and peaking in frequency response are

adjustable by varying ωz and ICP. The closed-loop frequency response for different values

of ωz in constant ICP are shown in Figure 2.8-(a). As ωz decreases the loop bandwidth

increases while the peaking in frequency response decreases.

For a third-order PLL with sampling/feedback delay, decreasing the zero frequency

increases the bandwidth. However, the peaking in frequency response increases because

of the phase margin degradation due to the third pole and delay. The phase margin (PM)

for a third-order PLL with loop delay of tdelay can be approximated with [79]:

ωc ωc 360
o
PM = atan  ------ – atan  --------- – ----------- ⋅ ω c ⋅ t delay ‹2.7›
 ω z  ω p3 2π

1. ωn and ζ (for a second-order PLL) are calculated from

2 2 2 K Loop K Loop
s + 2ζω n s + ω n ≡ s + -------------- RCs + --------------
N N
‹2.8›

20
The closed-loop frequency response of a third-order PLL for different values of ωz in

constant ICP are shown in Figure 2.8-(b).

Magnitude (dB) 0
10
(a)
ωz

−2
10 −4 −2 0
10 10 10
Magnitude (dB)

0
10
(b) ωz

−2
10 −4 −2 0
10 10 10
Frequency/fref

Figure 2.8: Closed-loop frequency response of: (a) an ideal second-order PLL, (b) a
sampling third-order PLL

2.5 Noise and Power Considerations

The primary goal to design a PLL for high-performance digital systems is to

generate an output clock with minimum timing uncertainty. The timing uncertainty arises

from mismatches in devices and noise sources present in the system.

Device mismatches causes a static phase shift (or skew) in the PLL output clock

from its desired phase. Skew can be minimized with a careful layout and increasing the

device size [11]-[12]. Skew is generally less critical than jitter because, due to its static

21
nature, the system can compensate for the static errors [13]-[14]. Dynamic noise causes a

random phase shift (or jitter) in the PLL output clock. The noise sources in a PLL are (1)

device electronic noise such as thermal noise or flicker noise and (2) power-supply or

substrate noise.

2.5.1 Device Electronic Noise

The device electronic noise at any individual blocks in a PLL perturbs the output

clock timing. Numerous studies provide models that predict the jitter due to device noise.

Most of these studies ([22]-[33]) focus on the modeling and prediction of jitter (or phase

noise) due to VCOs. A few studies discuss the effect of noise in other PLL blocks such as

PDs ([34]-[35]) and frequency dividers ([36]-[38]) on the PLL output jitter.

The previous studies also provide some guidance to reduce jitter. Some

architectures demonstrate an improved jitter performance over the others. For example,

resonant circuit-based VCOs (or harmonic oscillators) exhibit less jitter than relaxation

oscillators (such as ring oscillators) [24]-[25]. The jitter due to device electronic noise

generally demonstrates an inverse dependence upon power consumptions of PLL

components ([22], [26] and [30]-[32]). Therefore, there is a trade-off between power

consumption and jitter performance. For instance, Hajimiri in [26] demonstrates that the

jitter of a ring oscillator with a constant frequency decreases as the number of stages and

power increase.

22
2.5.2 Supply or Substrate Noise
Switching activities in digital systems introduces supply or substrate noise. The

supply or substrate noise perturbs the sensitive blocks in a PLL such as VCO and clock

buffer and leads to increased jitter.

Variation in supply or substrate voltage is coupled into the control voltage of a

VCO which changes the VCO operating frequency. The change in the oscillation

frequency of a VCO appears as a phase step in the input of the phase detector. The phase

error accumulates jitter until it is corrected by the PLL. Therefore, supply or substrate

noise causes jitter in a VCO which is persistent for the time duration equal to the time

constant of the PLL.

For a clock buffer1, supply or substrate noise varies the delay and introduces a

phase shift at the output clock of the buffer. The impact of the supply voltage step for a

clock buffer is considerably shorter lived. However, clock buffers are designed for power

and area efficient capacitance driving and not supply rejection. The long chain of buffers

needed in modern processors causes a significant transient phase shift at the output.

2.5.3 Noise Sensitivity Metric

The noise performance of VCOs and clock buffers are traditionally characterized

with noise sensitivity metric. Noise sensitivity for a VCO is defined as a percentage of

VCO clock frequency (or period) variation per percentage of supply voltage (or substrate)

1. Conventional clock buffers are composed of chain of CMOS inverters

23
variation; %-fVCO/%-VDD. Similarly, noise sensitivity for a clock buffer is defined as a

percentage of the inverter’s delay variation per percentage of supply voltage (or substrate)

variation; %-delay/%-VDD. One of the primary considerations in design of VCO and

clock buffer is to minimize the noise sensitivity of these circuits to supply or substrate

noise. For most digital systems, the supply or substrate noise does not exceed ±10-15%

[49].

2.6 Summary
This chapter discussed the basic concept behind phase locking and in particular, a

PLL. The operation of each PLL component is briefly explained which provides a

framework to understand the design of a PLL as discussed in the following chapters. Two

main architectures to design a PLL were discussed. A DLL has a simpler loop

characteristic than a PLL and does not suffer from jitter accumulation presented in a PLL.

However, a DLL passes input clock noise while a PLL low-pass filters the input noise.

The frequency multiplication is easier in a PLL than a DLL. These two reasons motivate

us to focus on the design of a PLL in this research.

The primary goal to design a PLL is to generate a low-jitter clock due to noise and

mismatches. This chapter discussed sources of noise. It also showed that there is a trade-

off between jitter, power consumption, and area.

To reduce noise, this research first studies the effect of loop parameters in filtering

out noise sources in a PLL. Chapter 3 develops a simple yet accurate model that predicts

the output jitter and provides an intuition toward optimum loop parameter design for

24
minimum jitter. To further adaptively minimize the jitter, Chapter 4 discusses a

methodology for on-chip adaptive jitter optimization.

Supply or substrate noise is a dominant noise source in large digital systems. This

research presents innovative filtering techniques at circuit level that achieve the noise

performance comparable to prior work but with lower power and area. The design of such

a high-performance PLL components is the subject of Chapter 5. The design of low-jitter

clock buffer with minimum power, area and delay overhead is discussed in Chapter 6.

25
Chapter 3

Jitter Optimization Based on PLL Design

Loop Parameters

Timing jitter has been the subject of numerous studies ([22]-[39]) which provide

many models to predict the jitter of individual blocks in a PLL, in particular, different

types of voltage controlled oscillators (VCOs) due to device noise and supply/substrate

noise. While most of previous work focuses on jitter study of individual blocks, there has

been done less work on modeling the overal jitter at PLL output clock ([22] and [43]-

[46]). This research extends the previous work by investigating the effect of PLL

parameters such as bandwidth and damping factor toward minimizing output clock jitter

for various noise sources.

The common design practice for systems with low-noise input clock is to

critically-damp or overdamp a PLL to minimize peaking in jitter transfer function and to

design the loop with the highest possible bandwidth to eliminate the effects of noise

26
sources at the output. Very low bandwidth and high damping factor are commonly used to

filter a noisy input clock with a clean oscillator within the PLL. By understanding the

sensitivity of jitter to loop parameters, we can refine these common practices in designing

low-jitter PLLs. Section 3.1 reviews the definitions of timing jitter. The brief study of the

previous work on jitter optimization is discussed in Section 3.2. The noise sources in a

PLL are the subject of the next section. Section 3.4 extracts the relationship between the

overall rms jitter at the PLL output clock, the power spectral density of each noise source

and the correspondent PLL noise transfer function. In Section 3.5, the sensitivity of jitter

to PLL damping factor and bandwidth is first derived for second-order loops and then

extended to third-order loops. The sensitivity of jitter to loop parameters is studied for all

primary noise sources in a PLL. Section 3.6 describes the design of a tunable PLL that is

used to minimize jitter and to verify our analysis. Finally, the experimental methods and

results that verify the jitter analysis are given in Section 3.7.

3.1 Definitions of Jitter

Phase jitter is defined as the standard deviation, σ∆φ, of the phase difference

between the first cycle and mth cycle of the clock (Figure 3.1). Timing jitter can be

T
∆T = m.T 1
σ ∆T = ⋅ σ ∆φ
ω0

Figure 3.1: Timing jitter

27
expressed in terms of phase jitter by σ ∆T = ( T ⁄ 2π ) ⋅ σ ∆φ = ( 1 ⁄ ω 0 )σ ∆φ where the

clock period, T, is 2π/ω0. Timing jitter is called short-term jitter for small ∆T and long-

term jitter as ∆T goes to infinity. The tracking jitter, σtr, is a commonly used metric for a

PLL output clock. It is measured as the phase difference between a clean reference clock

and the PLL output clock as shown in Figure 3.2. The tracking jitter is related to timing
σ ∆T → ∞
jitter by σ tr = ------------------- at very large ∆T as shown in [22].
2

PLL CKref

PLL CKout
σtr

Figure 3.2: Tracking jitter at PLL output clock

Before starting with our jitter analysis in a PLL, a background on jitter

optimization is discussed in the next section.

3.2 Previous Work

Prior research in [22] has shown that for an open loop VCO, jitter from random

noise sources is proportional to the square root of measurement interval (∆T),

σ ∆T ≈ κ ∆T , where the proportionality constant, κ, is a time-domain figure of merit

which depends on the VCO design. For the case of a first-order PLL with bandwidth of f-

3dB, the long-term jitter of the output clock due to VCO noise is calculated in [22] as
1
σ ∆T → ∞ = σ T = κ ------------------- . The first-order loop roughly approximates an overdamped
2πf – 3 dB

28
second-order PLL. The short-term jitter of the first-order PLL is calculated in [40].

Although, [40] conceptually discusses jitter in higher-order loops and for different noise

sources, it does not elaborate the impact of loop parameters on the output jitter. The

previous work in [42] investigates the effect of only loop bandwidth on jitter due to VCO

noise. Recently, the impact of the loop parameters on long-term jitter in an ideal second-

order PLL is studied [41]. While this con-current work achieves similar closed-form

equations for jitter as our analysis, it does not include higher-order effects of a PLL on

jitter.

In this work, we extend the jitter analysis to different noise sources and to any

second-order and third-order PLL loop parameters by including the delay and sampling

nature of the loop in the analysis. The main goal of this analysis is to provide a simple, yet

accurate model, to predict the short-term jitter as well as long-term jitter. The model

should also provide designers with some guidance for proper design of the loop

parameters for minimum jitter performance. First, we explain the primary noise sources in

a PLL and then, we discuss the jitter analysis.

3.3 Noise Sources in a PLL

This research includes the three primary noise sources in a PLL: input clock noise

(Vnin), VCO noise (VnVCO), and clock buffer noise (Vnbuf) as shown in Figure 3.3. Open
2
N Clk – in 2 en
loop noise psd of a clock source is equal to S φnin ( f ) = ------------------
- . Nin-CLK is K 0 ⋅ ------- [22]
f
2 2
where K0 ( Hz ⁄ V ) represents the gain of the clock source oscillator and en (V ⁄ Hz) is a
N Clk – in
white noise source. NClk-in is related to κ with κ = ----------------------- [22]. Being a clock source
ω in ⁄ 2π

29
as well, the VCO has a similar noise that can be characterized using Nvco to represent the

noise sources in the VCO1. For the buffer, open-loop noise psd is calculated by
N buf
S φn Buf ( f ) = ---------------------------
2 2
- where fBuf is the buffer 3-dB bandwidth (typically much larger
f ⁄ f buf + 1 2
2 en
than PLL loop bandwidth) and N buf = ( K delay ⋅ 2π ⋅ f VCO ) ⋅ ------- . Kdelay ( s ⁄ V ) represents
2
buffer delay variation to voltage noise. Multiplying Kdelay by clock frequency (fVCO)

converts delay to phase variation due to noise.

Vnin VnVCO Vnbuf

Input Filter VCO Clock φout

PD
Clock Buffer
φin + φnin φnVCO φnbuf

Figure 3.3: Noise sources in a PLL

The transfer functions from each noise source to the output of the PLL shape the

noise. For example, the loop transfer function from the input phase to the output phase is a

low-pass filter as seen from Equation 2.2. The lower the PLL loop bandwidth, the more

strongly the PLL rejects the input clock noise. Next section discusses and extracts the

relationship between the timing jitter at PLL output, each noise source and PLL loop

parameters.

1. VCO noise spectrum falls as 1/f2 for a bounded frequency range. At lower frequencies, it falls as 1/
3
f , and at higher frequencies, it flattens out. Since low-frequency noise is suppressed by the PLL, and high-
frequency noise is inconsequential to jitter (because it is so small), the 1/f2 approximation is a reasonable
assumption.

30
3.4 Jitter Calculation Model
The goal is to relate the timing jitter at the PLL output clock to each noise source.

As shown in Appendex A.1, the relationship between the timing jitter, σ∆T and noise

power spectral density (psd), Sφ(f), is:

2 8 ∞ 2
σ ∆T = --------2- ∫ S φ ( f ) sin ( πf∆T ) df ‹3.1›
ω0 0

At long delays ( ∆T → ∞ ), the expression is simplified as:

2 2 4 ∞
σ T = --------2- R φ ( 0 ) = --------2- ∫ S φ ( f ) df ‹3.2›
ω0 ω0 0

Figure 3.4 graphically depicts Equation 3.1 and as shown, reducing the area under the

phase noise psd lowers jitter at the output. The phase noise psd associated with each noise

source is shaped as each noise is filtered out by the loop transfer function of the PLL from

the correspondent noise source to the output.

sin2(πf∆T) Sφ(f)

1/ ∆T
f

Figure 3.4: Timing jitter as a function of noise psd, Sφ(f)

The filtering of the PLL on each input noise is included in the timing jitter by

replacing the noise psd in Equation 3.1 (or Equation 3.2) with closed-loop noise psd.

Under closed-loop condition, the total noise psd is calculated by

31
 2
S φ ( f ) = S φn –c losed ( f ) = ∑ Sφn –o pen ( f ) ⋅
i
Hn i ( j2πf ) ‹3.3›
i
2
Hn i ( j2πf ) is the square magnitude of noise transfer function (NTF) from each input
φ out
phase noise to PLL output phase, i.e. --------- ( f ) = Hn i ( j2πf ) . Sφni−open(f) indicates the open-
φn i
loop phase noise of each noise source as calculated in Section 3.3.

Replacing the open-loop phase noise of each noise source, the total noise psd at the output

is given by:

N in – CLK 2 N VCO 2 N buf 2

S φclosed ( s ) = ------------------------- ⋅ Hn in ( j2πf ) + --------------- ⋅ Hn VCO ( j2πf ) + ------------------------------ ⋅ Hn buf ( j2πf )
2 2 2 2
f f f ⁄ f buf + 1
‹3.4›

Note that this analysis assumes white noise sources. The same analysis can be done for
2
en
colored noise sources (such as supply and substrate noise) by replacing ------- by
2 2
en 1
------- ⋅ -------------------------------
- where fnoise is the 3-dB bandwidth of the noise.
2 f 2 ⁄ f 2 noise + 1

3.4.1 PLL Noise Transfer Function (NTF)

The second-order block diagram of a charge-pump PLL is shown in Figure 3.5.

The loop transfer function from the input phase to the output phase was calculated in

:N
VnVCO Vnbuf
Vnin
ICP
Input PD VCO Clock
KPD φout
Clock φnin KVCO /s φn Buffer φn
ICP R VCO buf

Figure 3.5: Block diagram of a second-order PLL

32
Section 2.4 (Equation 2.4). Similarly, the noise transfer functions from VCO1 and clock

buffer phase noise are calculated. The NTFs for three noise sources are2:

2
φ out K Loop RCs + K Loop 2ζω n s + ω n
Hn In ( s ) = ----------- = ------------------------------------------------------------- = --------------------------------------------
φn In 2 2 2
s + K Loop RCs + K Loop s + 2ζω n s + ω n
‹3.5›
φ out 2 2
s s
Hn VCO ( s ) = Hn buf ( s ) = ---------------------------- = ------------------------------------------------------------- = --------------------------------------------
φn VCO, buf 2 2 2
s + K Loop RCs + K Loop s + 2ζω n s + ω n

I CP
where K Loop = ----------- K PD K VCO , ω n = K loop , and ζ = K loop RC ⁄ 2 .
2πC

The NTFs for VCO and clock buffer noise are high-pass filters while the NTF for

input clock noise is a low-pass filter. Multiplying each noise source’s NTF with the

transfer function of the correspondent block provides the overall transfer function from

any voltage (or current) noise to the PLL output:

φ out RCs + 1
Tn In ( s ) = ----------- = ( K 0 ⋅ K Loop ) ⋅ --------------------------------------------------------------------
Vn In s ⋅ (s + K
2
RCs + K )
Loop Loop
φ out s
Tn VCO ( s ) = ---------------- = K VCO ⋅ --------------------------------------------------------
- ‹3.6›
Vn VCO 2
s +K RCs + K Loop Loop

φ out 1 s
2
Tn buf ( s ) = ------------- = -------------------------- ⋅ --------------------------------------------------------
-
Vn buf s ⁄ ω buf + 1 s + K 2
RCs + K Loop Loop

As seen from Equation 3.6, the overal loop transfer functions are low-pass filter,

band-pass filter and high-pass filter for input clock noise, VCO noise and clock buffer

noise, respectively. The overall transfer function for a clock buffer can be approximated as

1. For the VCO control voltage noise, the gain from the noise source to the VCO output phase is KVCO.
For power-supply noise, KVCO is substituted with the gain from supply noise to VCO output phase.
2. The loop multiplication factor is one.

33
 ω buf
a high-pass filter because the buffer 3-dB bandwidth, f buf = ---------- , is typically much
2π
larger than the PLL bandwidth. Figure 3.6 demonstrates the overall transfer functions for

three noise sources:

20

10
Noise transfer function (dB)

Input clock noise

0
(a)

−10

−20
VCO noise
−30 (b)

−40 Clock buffer noise

(c)

−50 4 6 8 10
10 10
frequency (Hz)10 10

Figure 3.6: Loop transfer function from each noise source to PLL output

3.5 Output Jitter of PLL

The total jitter at the PLL output clock is calculated by substituting Equation 3.4 in

Equation 3.1. The noise transfer functions in Equation 3.4 are substituted from Equation

3.5.

34
 3.5.1 Jitter due to VCO Noise
To study the effect of each noise source on jitter, we first consider the VCO noise

term in overal jitter equation:

2 8 ∞  N VCO 2 2
σ ∆T = --------2- ∫  ------------
2
- ⋅ Hn VCO ( j2πf )  sin ( πf∆T ) df ‹3.7›
ω0 0  f 

We first study the jitter due to VCO noise in an ideal second-order PLL.

Jitter due to VCO Noise in an Ideal Second-Order PLL

By substituting the VCO NTF from Equation 3.5 into Equation 3.7:

4N VCO ∞ 2 2 2
2 s sin ( πf∆T )
2 ∫
σ ∆T = ----------------
- ---------------------------------------- ---------------------------
2
- df ‹3.8›
ω0 – ∞ s 2 + 2ζω s + ω 2 f
n n s = jω

The equation is simplified as follows (Appendex A.2):

2
4π N VCO ∞ ∆T ∆T 2
x  t + ------- – x  t – -------
2
σ ∆T -∫
= ---------------------- dt ‹3.9›
2  2   2
ω0 –∞

s
where x(t) is inverse Fourier transform of --------------------------------------- . For damping factors
2
-
2
s + 2ζω n s + ω n s = jω
smaller and larger than one, the jitter expression is as follows (Appendex A.3):

 – ζω n ∆T
 1 e  sin ( ω d ∆T + θ ) cos ( ω d ∆T )
2 ------------
 2ζω - + ----------------------- ⋅  ------------------------------------- – ---------------------------- ζ<1
4π N VCO  n 2(1 – ζ ) 
2 ωn ζω n 
2
σ ∆T = ------------------------- ⋅ 
2
‹3.10›
ω0  2 2
1
 ------------ – a∆T  2αβ α  – b∆T  2αβ β 
-– e ------------ + ------ – e ------------ + ------ ζ≥1
 2ζω n a + b a  a + b b 
κ2 

2 2 2 –a
where ω d = ω n ⋅ 1 – ζ , cos θ = 1 – ζ , a, b = ζω n −
+ ω n ⋅ ζ – 1 , α = ------------
b–a
b
and β = ------------ .
b–a

35
 Figure 3.7-(a) shows the short-term jitter behavior for different damping factors.

The details of Figure 3.7-(b) is discussed in the next section. For ∆T of within a few

cycles, jitter accumulates as with an open-loop VCO. As ∆T increases, jitter behaves

similarly to the time-domain step response of the PLL output phase with similar

dependence on the damping factor and bandwidth. The lower damping factor appears as

more peaking in short-term jitter. For small short-term jitter, damping factor should be

designed to be equal to or greater than one to avoid ringing in the jitter response.

(a) Due to VCO noise (b) Due to buffer noise

15 2
10
1 (1)
Output RMS Jitter (ps)

5
0 0
0 50 100 0 50 100
1.5
5 1
(2)
0.5
0 0
0 50 100 0 50 100
5 1.5
1 (3)
0.5
0 0
0 50 0 50

Number of cycles of CKref (∆T/Tref)

Figure 3.7: Short-term jitter behavior with different f-3dB and ζ due to (a) VCO and
(b) clock buffering noise. ((1) f-3dB = 5.5% fref, ζ = 0.2 (2) f-3dB = 6.4% fref, ζ = 0.65 (3)
f-3dB = 11.4%fref, ζ = 1.63)

1
At large ∆T, long-term jitter converges to final value of κ ⋅ ------------- . Note that this
2ζω n
result is similar to the result derived in [41]. The sensitivity of jitter to loop parameters can

be illustrated graphically. Sweeping loop bandwidth (f-3dB) (or equivalently f n = ω n ⁄ 2π )

36
while ζ is constant results in Figure 3.8-(a) in which jitter is reduced proportional to
1
---------------- . Figure 3.8-(b) illustrates the effects of varying ζ (or peaking in the frequency
f –3 dB
response) with constant f-3dB. In the plot, fn is adjusted to maintain the same f-3dB while

sweeping ζ. For ζ less than one (or greater peaking in frequency response), long-term jitter
1
is proportional to ------- , but the sensitivity reduces as ζ increases. For ζ greater than 2 with
ζ
constant loop bandwidth, long-term jitter is relatively constant, independent of ζ value.

4
Constant ζ
Normalized RMS Jitter

2 (a)
1
0
0 5 10 15 20 f-3dB (%fref)
2
0.4 2 4 fn (%fref), ζ=1
Constant f-3dB
1.5
(b)
1

0.5
0 1 2 3 4 5 ζ
2.81.6 1.15 1.05 1.013 1.01 Peak(%)

Figure 3.8: Long-term jitter (due to VCO noise) as a function of: (a) loop bandwidth,
(b) loop damping factor

Jitter due to VCO Noise in a Third-Order Sampled PLL:

So far we investigated the effect of VCO noise using an ideal second-order PLL

without considering the effects of the third-order pole or the inherent loop delay in a

sampled system. In many PLLs, a 3rd-order pole is often included to filter control voltage

ripple. For high loop bandwidths, this pole degrades the phase margin and causes peaking

37
in the frequency response. A similar frequency response peaking occurs when accounting

for the delay in the feedback loop and the sampled-nature of the loop. These non-idealities

can be taken into account using Equation 3.2 with a more accurate NTF.

We included these non-idealities into a MATLAB analysis. Figure 3.9 compares

the output long-term jitter as bandwidth is increased for a second-order loop (curve-a),

third-order loop without loop delay (curve-b), and third-order loop with loop delay (curve-

c). In the plot, the 3rd-order pole is kept constant while the zero frequency is decreased

which simultaneously increases the open-loop cross-over frequency, ωc, and the damping

factor. The plots on the right illustrate the loop frequency responses for a 2nd-order, 3rd-

order PLL without and with loop delay as zero frequency (ωz) is decreased. Curve-a

shows the anticipated decrease in jitter due to the higher bandwidth and damping factor. In

curve-b, as the loop bandwidth nears the 3rd-order pole, the peaking in frequency

response increases due to phase margin degradation. Thus jitter is roughly flattened at

bandwidths higher than 3rd pole due to the opposing effect of peaking and bandwidth on

jitter. Accounting for loop delay (curve-c), the jitter increases at high bandwidth due to the

additional peaking in the NTF from more phase margin degradation1. A minimum exists

and is modestly flat over a significant range of loop parameter variations. This implies that

a loop designed near this minimum has an output jitter that is relatively insensitive to the

parameter variations that may be due to process, voltage and temperature (PVT).

1. To the first order, using the loop delay accounts for the effect of the sampled system. The
measurement results of Section 3.7 matches the simulated results from this model better than that from a z-
domain model using impulse invariant transformation [80].

38
 5 4
2nd-order PLL

Loop Frequency Response

2
ωz

Output RMS Jitter (ps)

4
0 0
10
4
3 (c) 3rd-order 3rd-order PLL
+ delay 2 ωz
(b)
3rd 0
2 (a -or 10
0

)2 de 4
nd r 3rd-order PLL
-o +delay
rd
1 er 2
ωz
3rd pole
0 0
0 0.2 0.4 10

f-3dB / fref frequency / fref

Figure 3.9: Comparison of long-term jitter (due to VCO noise) in: (a) 2nd, 3rd order
loop (b) without loop delay and c) with loop delay

Analysis of the minimum indicates that it depends on all four variables (loop gain,

zero frequency, 3rd-order pole frequency, and loop delay) because each contribute to

phase margin degradation (Equation 2.7). The analytical results show that jitter is

minimum with PM between 30o and 45o. Consequently, the PLL bandwidth at minimum

jitter reduces as 3rd-pole frequency decreases or loop delay increases as shown in Figure

3.10. This result counters common practice of designing with large phase margins and

damping factor of 1 ⁄ 2 .

39
 45

1/3 Tref

f-3dB/fref (%) at min. Jitter

delay =
40

35
/2 Tref
delay = 1
30

25

20 delay = 1.0 Tref

15 1.5 Tref
delay =
10
20 30 40 50 60 70

3rd pole frequency / fref (%)

Figure 3.10: PLL bandwidth (at minimum jitter) as a function of 3rd pole frequency
and PLL loop delay

Noise from the buffering and the input clock can be similarly analyzed using the

corresponding closed-loop noise psds. Similar to the VCO noise, we first analyze the jitter

behavior in an ideal second-order PLL. The final equations are summarized in Appendex

A.3 and Appendex A.4, respectively. Then, the jitter analysis is extended to a third-order

PLL taking into account the delay and sampling nature of the loop.

3.5.2 Jitter due to Clock Buffer Noise

Jitter behavior due to buffer noise over different time intervals has similar behavior

to VCO noise except for small ∆T where jitter is increased sharply due to the high-pass

filtering of the buffer NTF. Figure 3.7-(b) illustrates the output jitter for different ∆T with

different damping factors.

40
 To compare buffer noise magnitude with VCO noise, the jitter values are extracted

from Equation 3.10 and Equation A.8 (Appendex A.4) for ∆T → ∞ . The ratio of the

buffer noise variance with VCO noise variance is:

2 2 2 2 2
σ Buf ( N Buf ⁄ ω 0 ) ⋅ ω Buf m ⋅ K delay ⋅ ω 0 ⋅ ω Buf ⋅ e n buf ⁄ 2
------------
2
- ≈ -----------------------------------------------------------------------
2 2
- = -------------------------------------------------------------------------------
2 2 2
- ‹3.11›
σ VCO ( 4π ⋅ N VCO ⁄ ω 0 ) ⋅ ( 1 ⁄ 2ζω n ) 4π ⋅ K VCO ⋅ ( 1 ⁄ 2ζω n ) ⋅ e n VCO ⁄ 2

where m is the number of buffer stages. For a ring oscillator with the same delay elements
–1
as the buffering, the KVCO can be expressed in terms of Kdelay, K VCO = K delay ⋅ ----------------2-
2n ⋅ t d
where n is the number of stages in ring oscillator VCO and td is the delay of each stage.

This simplifies Equation 3.11 to:

2
σ Buf mζω n
- ≈ --------------
------------ ‹3.12›
σ VCO nf osc
2

With ωn=0.2fosc and ζ=1, in order for the noise contribution of the buffer to be less than

that of the VCO, either m<5n or the VCO element must have 5x lower noise sensitivity

than the buffer elements. With lower loop bandwidths, buffer noise contribution decreases

proportionally.

3.5.3 Jitter due to Input Clock Noise

Jitter due to Input Clock Noise in an Ideal Second-Order PLL:

When accounting for the effect of the PLL filtering on a noisy input clock, the

analytical results1 for a 2nd-order PLL show that the output clock timing jitter is

1. Equation A.18 in Appendex A.5

41
suppressed at small ∆T and asymptotically approaches a value, κ 1 ⁄ ( 2ζω n ) , greater

than the input jitter at large ∆T. The shape and final value depend on the bandwidth and

the damping factor. Figure 3.11 illustrates the behavior of output clock jitter for different

damping factors with constant bandwidth. The figure also includes the behavior of input

−7
x 10
4

ζ=0.5
(Output Clock Jitter/κ)2

3 ζ=1.2

(Input Clock Jitter/κ)2 ζ=3

0
0 50 100 150 200

Number of cycles of CKref (∆T/Tref)

Figure 3.11: Output clock jitter (due to input clock noise) behavior vs. input clock
jitter behavior

clock jitter. The ∆T at which the jitter exceeds the input jitter (the crossover time, ∆Tcr) is

larger for higher damping factors and lower bandwidths. For most clock source PLLs,

jitter of the overall system is suppressed as long as ∆Tcr is longer than the response time of

any subsequent PLLs locking to the output clock. The jitter analysis due to noisy input

clock not only confirms common practice but also elaborates the roles of bandwidth and

damping factor on the output jitter. Figure 3.12-(a) shows how the output jitter (at ∆T=100

cycles) is reduced as bandwidth is decreased. Equation 3.12-(b) demonstrates that the

output jitter (at ∆T=100 cycles) is reduced as damping factor is increased for two different

42
bandwidths. Similar to VCO noise analysis, output jitter is roughly constant for damping

factor greater than 2. For instance, for output jitter to be less than 0.1 input jitter at ∆T>

100 cycles, the PLL should be designed with a damping factor greater than 2 and

bandwidth less than 0.002% of operating frequency.

100
Constant ζ
Output/Input jitter (%)

50 (a)

0 −1
10 f-3dB(%fref)
0 1 2
10 10 10
12 80
Constant f-3dB
10 70
f-3dB = 0.002% fref (b)
8 60
f-3dB = 0.1% fref
6 −1 50
10 10
0
10
1
ζ

Figure 3.12: Output to input jitter ratio behavior of a 2nd-order loop as a function
of: (a) loop bandwidth, (b) loop damping factor

Jitter due to Input Clock Noise in a Third-Order Sampled PLL:

To investigate the effects of the loop non-idealities, the jitter (due to input clock

noise) of an ideal 2nd-order loop is compared to that of a 3rd-order PLL with loop delay.

To better show the comparison, we assume white noise at PLL input phase instead of 1/f2

noise (of a noisy input clock). Figure 3.13 illustrates the output long-term jitter while the

zero frequency is decreased which simultaneously increases the loop cross-over frequency

and the damping factor. Jitter decreases initially for all three curves due to the lower

frequency-response peaking where the bandwidth changes only slightly. As the zero

43
frequency decreases further, the bandwidth increases causing jitter to increase. At

bandwidths close to 3rd pole, the peaking is increased due to phase margin degradation

which results in more jitter increase in curve-b compared with curve-a. When accounting

for loop delay (curve-c), additional peaking in the NTF from more phase margin

degradation manifests the sharp jitter increase.

20
Output RMS Jitter (ps)

15

y
la
de
r+
de
10

or
d-
3r
o rd e r
b ) 3r d-
c)
5 o rd e r
a ) 2n d-
3rd pole
0
0 10 20 30

f-3dB / fref (%)

Figure 3.13: Comparison of long-term jitter (due to white noise at PLL input) in: (a)
2nd, 3rd order loop (b) without loop delay and (c) with loop delay

3.6 PLL Design with Adjustable Loop Parameters

As discussed in the previous section, a trade-off is present between input noise and

the noise from within the loop. A high-bandwidth PLL can track the phase of a low-noise

input clock and filter out VCO and clock buffer noise. Conversely, a low-bandwidth PLL

filters a noisy input clock while it is transparent to VCO and clock buffer noise. We design

a PLL with adjustable loop bandwidth and peaking in frequency response to verify the

44
results in the previous section. The parameters can be adjusted by varying the loop

stabilizing zero and the open loop gain.

One possible architecture [52] is shown in Figure 3.14. This PLL has an adaptive

CPintegral 1/gmReg
Regulator
PFD + Clock
CCP -
VCO Buffer
CKref CKout
C1
d10 d1n

CPproportional

d20 d2n

Figure 3.14: An adaptive bandwidth PLL with tunable loop parameters

bandwidth with tunable loop parameters. The design employs two digitally controllable

charge pump currents in the proportional and integral paths to adjust ωz and Kloop:

 ω = 1 ⁄   --------------
1 I CPproportional 1
 z - ⋅ ---------------------------------- ⋅ C CP + --------------- ⋅ C 2
  gm Reg I CPintegral  gm Reg 
 ‹3.13›
 K VCO ⋅ I CPintegral
 K Loop = ------------------------------------------
 N ⋅ C CP

While the proportional charge-pump current varies the zero locus only, sweeping the

integral charge-pump current changes both the zero and the open loop gain. Varying any

of the two charge-pump currents does not vary the position of the PLL third-order pole.

45
3.7 Experimental Methods and Results
The adaptive bandwidth PLL clock generator with tunable loop parameters (shown

in Figure 3.14) is designed and fabricated in 0.25-µm CMOS technology. The PLL die

photogragh is shown in Figure 3.15 where the area overhead due to digital controller logic

is approximately 15% of PLL core area.

Digital
Controller
Logic
Loop Filter
CP1 Reg
CP2 VCO
PFD CLK
Buf

Figure 3.15: Die photograph of the PLL

3.7.1 Verification of Jitter Analysis due to VCO Noise

To observe only VCO noise, a clean signal generator (with rms jitter of less than 1

ps) produces the reference clock and the design uses only a few buffer stages in the

feedback so that the buffer noise is small compared to VCO noise.

Tracking Jitter due to VCO Noise:

To verify the presence of minimum tracking jitter due to VCO noise, the integral

charge pump current is kept constant (i.e. KLoop = constant) while the proportional charge

46
pump current is swept (i.e. ωz is decreased). For each value of ICPproportional, the rms

tracking jitter of PLL output clock is measured based on the configuration of Figure 3.16.

The same measurement is repeated when ICP1 is varied.

Digital Oscope
Reference Output
clock
clock
PLL Input
Trigger

Figure 3.16: Measurement technique in time domain, referenced to reference clock

Table 3.1 summarizes some of the results at reference clock frequency of 700MHz

where I1 and I2 are constant currents.

Figure 3.17-(a) and (b) show the measured and calculated jitter for one set of

measurements repeated for two reference clock frequencies. As seen in the figure, the

measured jitter corresponds closely with the analytical results and there is a minimum

jitter with a low sensitivity to loop parameter variations. For example, ±20% of bandwidth

variation increases jitter by less than 5%. In each set of measurements, jitter initially

decreases because the peaking decreases (or ζ grows linearly) with ICPproportional and the f-

3dB increases with the decreasing zero frequency (fn is held constant). As ICP2 increases,

the cross-over frequency approaches the third-order pole and degrades the phase margin.

Jitter reaches a relatively flat minimum before increasing due to the loop delay

(approximately 0.47ns).

47
 Increasing reference clock frequency from 700MHz to 1.1GHz in our adaptive

bandwidth PLL, effectively measures the result of changing the loop’s feedback delay

from 1/3 to 1/2 of the reference clock period. The bandwidth at minimum jitter is reduced

from 26% to 12% of reference clock (Figure 3.17-(c)).

Measurement
Analytical results

4 fref = 700 MHz

(a)
Output RMS Jitter (ps)

2
0 5 26% 10 15
3
fref = 1.1 GHz
2 (b)

1
0 5 12% 10 15
5
tdelay1 > tdelay2 t delay
1
tdelay2
(c)

0 26% 10
0 512% 15 ICPproportional/ICPintegral
33 100 180 250 f-3dB (MHz)

Figure 3.17: Measured and calculated tracking jitter as ωz is reduced in constant

48
 Table 3.1: Tracking jitter (in ps) for different loop parameters (fref = 700MHz)

ICPintegral 2.I1 3.I1 4.I1 5.I1 6.I1

ICPproportional rms jitter rms jitter rms jitter rms jitter rms jitter

2.I2 4.49 4.67 5 5.57 6.8

3.I2 3.4 3.41 3.45 3.57 3.76

4.I2 2.8 2.81 2.96 2.87 2.99

5.I2 2.58 2.54 2.6 2.52 2.55

6.I2 2.37 2.35 2.3 2.35 2.37

7.I2 2.24 2.2 2.17 2.23 2.18

8.I2 2.14 2.1 2.08 2.1 2.1

9.I2 2.04 2 2.03 1.99 2.03

10.I2 2.01 1.97 1.9 1.99 1.93

16.I2 1.88 1.87 1.87 1.8 1.85

17.I2 1.9 1.8 1.72 1.73 1.84

18.I2 1.91 1.88 1.73 1.71 1.85

19.I2 1.89 1.89 1.77 1.73 1.88

21.I2 1.94 1.86 1.73 1.72 1.83

24.I2 2.03 1.99 1.8 1.77 2

32.I2 2.4 2.1 2.16 2.21 2.32

Short-Term Jitter due to VCO Noise:

The short-term jitter sensitivity to PLL loop parameters is also verified. The short-

term jitter is calculated with the analytical model. The time domain figure of merit of the

VCO is equal to κ ≈ 5.4e – 8 s at 700MHz oscillating frequency. The 3-dB bandwidth

and peaking used for the model are first calculated through circuit simulations and then

verified with direct measurements. The test setup that measures the loop parameters is

49
shown in Figure 3.18. A radio frequency (RF) signal is added to the input clock. The

Digital Oscope
Pulse Generator
Clock + jitter Output
Ref clock clock
PLL Input
Trigger

RF generator
(jitter source)

Figure 3.18: Measurement technique for calculating PLL loop transfer function

output clock jitter is measured over different RF frequencies. The measured PLL loop

transfer functions with their effective f-3dB and effective peaking (Appendex A.6) are

shown in Figure 3.19 for four different values of ICPproportional with constant ICPintegral.

3 f-3dB
(MHz) Peak ζ ICP2
|H(s)| (Loop Transfer Function)

2.5 39 2.8% 0.2 2.I2

45 1.26% 0.65 4.I2
80 1.07% 1.63 10.I2
2
320 2.4% 0.3 32.I2

1.5

0.5

0 0 2
10 10
Input RF Frequency (MHz)

Figure 3.19: Measured PLL loop transfer function (@ 700MHz reference clock) at a
constant ICPintegral (constant KLoop)

50
 The rms jitter is measured over different time interval (∆T) for each of the four

different settings of loop parameters. The measurement uses a self-referenced technique

shown in Figure 3.20. The dummy delay in the test setup is critical to compensate for the

Digital Oscope
Reference Output Dummy
clock clock Trigger
PLL Input
Delay Trigger
σ∆T
T

∆T

Figure 3.20: Measurement technique in time domain, referenced to output clock

triggering delay of an oscilloscope. Figure 3.21 shows the measured and calculated short-

Measurement
Analytical results
10

5 (a)
f-3dB = 39 MHz, Peak = 2.8% (ζ = 0.2)
0
Output RMS Jitter (ps)

0 20 40 60 80 100 120 140 160

6

4 (b)
f-3dB = 45 MHz, Peak = 1.26% (ζ = 0.65)
2
0 50 100 150
4

3 (c)
f-3dB = 80 MHz, Peak = 1.07% (ζ = 1.63)
2
0 10 20 30 40 50 60 70
5
(d)
f-3dB = 320 MHz, Peak = 2.4% (ζ = 0.3)
0
0 5 10 15 20 25
Number of Cycles of CKref (∆T/Tref)

Figure 3.21: Measured and calculated short-term jitter (@ 700MHz reference clock)
for four different loop parameters

51
term jitter. A slight timing shift between predicted and measured jitter is present because

of time uncertainty due to the delay of input trigger and dummy trigger delay at the input

of oscilloscope.

3.7.2 Verification of Jitter Analysis due to Input Clock Noise

To verify the jitter analysis due to input clock noise, we apply a free running VCO

at 700MHz as a reference clock of the PLL. A white noise source is injected to the control

voltage of the free running VCO so that the input clock noise is the dominant noise source.

(a) (b)
200 200
Output RMS Jitter2 (ps2)

150 150

100 (2) (3) 100 (2) (3)

) (4)
) (1
50 (1 (4) 50

0 0
0 5 0 5
Number of Cycles of CKref (∆T/Tref)

Figure 3.22: Output jitter (due to input clock noise) behavior for three different PLL
loop parameters: (a) measurement results, (b) analytical results ((1) Input jitter (2) ζ
= 0.2, f-3dB = 39MHz (3) ζ = 0.65, f-3dB = 45MHz (4) ζ = 1.63, f-3dB = 80MHz)

As the baseline measurement, we measure the rms jitter of this reference input over

different time interval (∆T) based on the self-referenced technique (Figure 3.20). We also

52
measure the PLL output rms jitter while varying ∆T for three different loop parameters.

The measurement results in Figure 3.22-(a) demonstrate the same behavior to the

analytical results (Figure 3.22-(b)) with approximately the same ∆Tcr.

3.8 Summary
This chapter investigates the role of PLL loop parameters on timing jitter. Several

common noise sources have been included in the analysis. We develop an intuition for

designing low-jitter PLLs both by deriving a closed-form solution for a second-order loop

and by plotting the jitter sensitivity to various loop parameters for higher-order loops. One

possible PLL architecture with digitally-controllable loop parameters is designed that can

optimize jitter performance. Furthermore, the loop serves as a test bench to verify our

analysis.

The analysis shows a simple expression for long-term jitter due to VCO and

buffering noise to the damping factor and natural frequency. We derive an expression that

relates the jitter contribution of clock buffering (in the feedback) and VCO to the same

parameters. We validate the common design practice of using high loop bandwidth to

reduce VCO-induced jitter. However, to minimize jitter, we find that accounting for the

loop delay in the phase margin is critical. Interestingly, this minimum is very insensitive to

PVT and parameter variations making such a design robust. For applications that require

small short-term jitter (i.e. short distance links and block to block interconnect), an

underdamped loop can result in much higher short-term rms jitter. For applications that

filters input jitter, our modeling shows that very low bandwidths (0.002% fosc) are

53
necessary to reduce noise by a factor of 10 while a damping factor greater than 2 is

sufficient.

The result of jitter analysis extracted in this chapter can be applied to the optimum

design of PLL loop parameters to minimize the PLL output jitter. The jitter optimization

requires a well-known knowledge about the noise sources in a PLL. Since the noise

sources are not predetermined, the preliminary design of loop parameters does not

neccessarily result in minimum jitter performance. To further improve the noise

performance, the loop parameters of a PLL should be tuned for a minimum output jitter in

real system noise conditions. The next chapter presents a methodology for on-chip jitter

minimization and verifies the accuracy of the method in converging to the minimum jitter

at PLL output clock.

54
Chapter 4

Methodology for On-Chip Adaptive Jitter

Minimization in PLLs

The previous chapter shows that the output jitter of a PLL depends strongly on the

magnitude and frequency response of the noise sources and the loop parameters. For many

systems, the loop design is complicated because the magnitude of the noise sources is not

well known; a noisier clock reference may be used or larger on-chip switching noise may

be present. Jitter can still be minimized under various noise conditions if jitter can be

dynamically measured with an on-chip noise measuring circuit and the loop parameters

can be adapted with a programmable loop filter. This chapter investigates the

methodology and accuracy of jitter minimization that occurs during system operation and

not just during calibration or system startup.

Section 4.1 reviews the relationship between the minimum jitter and the loop

parameters for two noise sources, input clock noise and internal VCO noise, as extracted

55
in Chapter 3. It is observed that the total jitter due to the two noise sources has only one

minimum that is global for a range of loop parameters that the PLL is stable. This result

leads to the gradient-descent algorithm described in Section 4.3. The circuit components

needed to dynamically minimize jitter is described in Section 4.2. Several of the existing

circuits that can measure jitter both for clocking and for data recovery are discussed.

Section 4.3 discusses the algorithms that converge to the minimum jitter during active

system operation. Because jitter is a stochastic process, any on-chip measurements are

subject to errors depending on the amount of averaging. The section illustrates the

performance of the convergence as related to the amount of jitter information. The chapter

concludes with some guidance on design of on-chip jitter minimization.

4.1 Overview
Previous chapter discussed the relationship between minimum jitter due to each

noise source and PLL loop parameters. The block diagram of a PLL with two primary

noise sources, input clock and internal VCO noise, is shown in Figure 4.1. Although this

:N
VnVCO
Vnin
Lowpass φout
Input PFD Filter VCO
Clock
φVCO + φnVCO
φin + φnin

Figure 4.1: The PLL block diagram with VCO and input noise

56
work only considers these two noise sources, the results can be extended to other noise

sources in a PLL.

Each of the noise sources is shaped by the loop transfer function from the

corresponding noise voltage source to the output phase. Figure 4.2 illustrates the filter

response for each of the noise sources.

10
Noise transfer function (dB)

0
Input clock noise
(Vnin)
−10

−20

−30 VCO noise

(VnVCO)
−40

−50 4 6 8 10
10 10 10 10
frequency (Hz)

Figure 4.2: Loop transfer functions from VCO and input clock noise to the PLL
output

As seen in Figure 4.2, the loop transfer function for the VCO noise (VnVCO) is a

band-pass filter that suppresses the VCO noise within the PLL bandwidth. In a second-

order PLL, the long-term rms jitter due to VCO noise1 is calculated as:

1. VCO phase noise is assumed to fall as 1/f2. The long-term jitter is calculated from Equation 3.10
when ∆T goes to infinity

57
 N VCO 1 -
σ rms = ----------------- ⋅ ------------ ‹4.1›
f0 2ζω n

where f0 is the VCO frequency, ζ is the PLL damping factor and ωn is the PLL natural

frequency. The two loop parameters that can be easily tuned in a charge-pump PLL are the

PLL zero frequency, ωz, and the PLL loop gain, Kloop. Sweeping ωz and Kloop effectively

changes the PLL bandwidth and peaking in the PLL frequency response. Substituting ζ

and ωn with ωz and Kloop in Equation 4.1 results in:

N VCO 1
σ rms = ----------------- ⋅ ------------------------ ‹4.2›
f0 –1
( ω z ) ⋅ K Loop

Based on Equation 4.2, the relationship in a second-order PLL between the VCO-induced

jitter and the loop parameters, (ωz)-1 and Kloop, can be shown to be convex and hence has

only a global minimum without local minima. The jitter behavior as a function of (ωz)-1

and Kloop, in a third-order sampling PLL is graphically shown in Figure 4.3. The plot

includes the higher-order pole and sampling/feedback delay and still maintains the

convexity. The minimum jitter, as shown with the contours in Figure 4.3-(a), occurs at a

high loop bandwidth with low peaking in the PLL frequency response. As the bandwidth

is further increased, the phase margin degrades which increases the peaking and

eventually increases jitter.

58
 25

rms jitter (ps)

20

15
(a)
10

5
15

10
1
K
15
x 10
l oo 5 0.5
p - 1
−7
x 10
0 0 (ω z)

x 10
15 Min jitter
10
9

10
10
8.7

8.4

11
9
11

9
8.7

7
Kloop

9
13

10
10

11
6
(b)
11

5
10
4
11
13

11
3
20

156
18
1

1 2 3 4 5 6 7 8

(ωz)-1
−8
x 10

Figure 4.3: Behavior of output clock jitter due to VCO noise for various loop
parameters: (a) 3-D, (b) contour

In contrast with the VCO noise, the loop transfer function for the input clock noise

is a low-pass filter that suppresses the input noise outside the loop bandwidth. The long-

term jitter due to input clock noise1 in a second-order PLL is equal to:

1. The input clock noise is assumed to be white, i.e. S φn – in ( f ) = N Clk – in . The detail of long-term
jitter calculation is given in Appendix A.5.2.

59
 N Clk – in –1 1
σ rms = ----------------------- ⋅ K loop ⋅ ( ω z ) + --------------- ‹4.3›
2πf 0 (ω )
–1
z

14

12
rms jitter (ps)

10
(a)
8

6 15
4 10
15
0 p
K loo
0.2 5 x 10
0.4 0.6
−7 (ωz ) -1 0.8 1 0
x 10

15
x 10
10
9
8

11

9
12
7

8
10
6

11
9

7
8
Kloop

(b) 6 10
5

7
5.

9
6

5 8

5. 7
4 5
4.9
6
3 7
5.5

4.5 4.9 5.5

6
1 2 3 4 5 6 7 8
Min Jitter −8

(ωz )-1 x 10

Figure 4.4: Behavior of output clock jitter due to input noise for various loop
parameters: (a) 3-D, (b) contour

60
 It can be shown that the relationship in Equation 4.3 is not convex1. Including the

higher-order pole and sampling/feedback delay, Figure 4.4 plots the output jitter due to

only input-clock noise for a third-order sampling PLL. As seen in the figure, no local

minimums exist. The concavity of the surface is not very apparent and only occurs when

the phase margin is small (<30o). Such small phase margin is an unlikely operating point

due to possible loop instability. Similar to VCO noise, a single minimum exists except that

it is at a low loop gain as shown by the contours in Figure 4.4-(b).

The total jitter is the sum of the jitter variances due to both VCO and input noise

sources. Figure 4.5-(a) shows the total jitter when two noise sources are comparable. As

one noise source becomes dominant, the minimum point of the contour shown in Figure

4.5-(b) moves toward the minimum for that particular noise source (Figure 4.3-(b) or

Figure 4.4-(b)).

Although, the jitter function due to the input noise is not entirely convex, it is shown in

Appendix A.8 that the total jitter in a second-order PLL has one global minimum without

any local minima. Simulation results for various ratios of VCO and input noise sources

show that the single minimum holds even when including a higher-order pole and

sampling/feedback delay. This important result motivates the proposed gradient-descent

algorithm of Section 4.3 when the loop parameters are dynamically adjusted to achieve

minimum jitter.

1. Please see Appendix A.7.

61
 30

25
rms jitter (ps)

(a) 20

15
15
10 10
0 15
p x 10
0.5 5 K loo
−7 (ωz ) -1 0
x 10 1

15
x 10
10
20
14.8
14.8

VCO noise
15.5

9
16
15.5
16

22
18

24
7
20
Kloop

22
14.

(b)
14.8.5
18

6
16 5
14.2
1516

18
15
.
14.2

5 20
Input noise

4 18
14

16
15
.8
22

14
20

3
.5
.8
18

16

1 2 3 4 5 6 7 8
(ωz)-1 x 10
−8

Figure 4.5: Behavior of output clock jitter due to both VCO and input noise for
various loop parameters: (a) 3-D, (b) contour

62
4.2 Jitter Detection Circuits and Architectures
To dynamically minimize jitter at the PLL output during system-operation, the

design requires three elements: 1) a PLL that has appropriately adjustable loop

parameters, 2) an on-chip jitter measuring that can compare the jitter between

measurements, and 3) an algorithm that adjusts the loop parameters to minimize jitter

based on the on-chip measurements. The first two are discussed in this section.

4.2.1 PLL Design with Adjustable Loop Parameters

As discussed in the previous chapter, the two loop parameters of a PLL that

significantly impact jitter are the loop bandwidth and peaking in the frequency response.

They can be adjusted by varying the loop stabilizing zero and the open loop gain. One

possible PLL architecture is the one used in Chapter 3 to verify the jitter analysis (Figure

3.14). While the proportional charge-pump current varies the zero locus only, sweeping

the integral charge-pump current changes both the zero and the open loop gain.

In the second configuration shown in Figure 4.6, ωz and Kloop, are independently

adjustable by varying the loop stabilizing resistor (R) and charge pump current (ICP),

respectively:

 ω z = 1 ⁄ ( R ⋅ C CP )
 K VCO ⋅ I CP ‹4.4›
K ≅ -------------------------
-
 loop N ⋅ C CP

63
In this configuration, third-pole does not move as ICP or R are changed.

:N

CP
ICP Vctrl
PFD VCO CKout
CKref ICP
R C1
d0 dm-1 CCP

cn-1
c1
c0
Up

Vctrl 2W0 R0/4 R0/2 2n-3.R0

Vint
W0 R0 2.R0 2n-1.R0
Dn 2W0
4W0

d2 d1 d0
Controller

Figure 4.6: A PLL architecture with adjustable loop parameters using adjustable R
and ICP

The configuration shown in Figure 4.6 is used in both simulations and

measurements. The design permits 4-bits of digital adjustment for resistor that varies the

zero position by more than 10x (from 0.1 to 1.6 rad/sec). In this implementation of the

adjustable resistor, the resistance steps with non-linear digital quantization levels1. The

design also permits 3-bits of digital adjustment for charge-pump current that varies the

loop gain by 5x (from 2e15 to 10e15 (rad/sec)2) with a linear quantization level.

1. [..., 5/7R0, 5/6R0, 5/4 R0,..., 5/2R0, 5R0]

64
4.2.2 On-chip Jitter Measurement Architectures
The on-chip jitter measurement circuit depends on the application. This section

first describes the approach for a data recovery system. Possible approaches for on-chip

clock generation is addressed next.

1) Data-Recovery Applications:
In data-recovery applications, clocks sample not only the center of the data eye to

recover the data pattern but also the data transitions to determine phase information. The

goal of the PLL is to track the data jitter while rejecting the noise from the VCO. By

correlating the sampling clock with the data transitions, the loop minimizes the phase error

between the sampling clock and the data input.

Several previously published techniques demonstrate on-chip jitter measurement.

In [67], a flash time-to-digital converter (TDC) measures the data jitter with the sampling

clock. This technique requires significant number of arbiters and on-chip buffering of the

data and clock as shown in Figure 4.7.

Data
Buffer
Clock

Arbiter

Decoder Logic

Figure 4.7: Jitter measurement with a flash TDC architecture

65
 Another technique demonstrated by [68]-[70] uses a dead-zone phase detector to

measure the jitter. Figure 4.8 illustrates the basic concept of the jitter measurement. A

D1 D2 D3

Histogram DCK

min % < Noutside/Total < max %

WDZ

XCKL XCKR

Figure 4.8: Jitter measurement with a dead-zone window establishment

dead-zone window is constructed by using two data-transition samplers in addition to

sampling the data in the middle of the eye. The transition sampling clocks, XCKL and

XCKR, are programmed to track the left and right edges of the data eye and adjust the

dead-zone width, WDZ, accordingly. The design in [70] uses only one data-transition

sampler to construct the dead-zone window (WDZ) by alternating the edge sampling clock

position. The data transition outside the window is detected when the value of data

sampled by the transition sampling clock is equal to that sampled by the data sampling

clock. The magnitude of jitter is estimated by comparing the number of data transitions

outside the dead-zone for a given total count of data transitions. The window size is

adjusted when the number of transitions (measured hits) outside the zone is greater or less

than predetermined bounds to avoid saturating the counters. A similar method can adjust

66
the width of the dead-zone window until the number of measured hits is roughly a fixed

percentage of the total hits. This effectively directly measures the width of the jitter

histogram. The dead-zone technique is the measuring jitter circuit that is mimicked in the

next section.

2) On-Chip Clock Generation Applications:

The design is considerably different for an application that minimizes the jitter of a

large digital system’s clock. A similar architecture to [67] has been shown in [71] where

an array of phase detectors compares consecutive clock edges and measures the cycle-to-

cycle jitter. However, it is important to note that cycle-to-cycle jitter can not be minimized

through adapting the loop parameters. As shown in Section 3.5, cycle-to-cycle jitter is

primarily determined by the noise characteristics of the VCO alone and not the PLL loop

parameters. Adjusting loop parameters may result in large long-term jitter or an unstable

loop.

In the event that the long-term tracking jitter is important, a circuit that

accumulates phase over multiple cycles is necessary. The design of the accumulation

circuit is very challenging because it must strongly reject supply and substrate noise. A

simple delay line that spans multiple cycles is not adequate because a multi-cycle on-chip

delay line would likely introduce a significant noise floor to the measurement. Integrator

techniques similar to that used by Wavecrest SIA-3000 would suffer similar issues on-

chip. The design of this challenging circuit is left as future work and not addressed in this

work.

67
4.3 Jitter Minimization Algorithms and Measurements
Due to the stochastic nature of jitter, the measurement accuracy is a function of the

number of the samples. In addition, the jitter measurement circuit itself introduces some

noise. After describing the measurement setup, this section discusses the sensitivity of the

measurement to the total number of samples. Next, two jitter minimization algorithms are

described and their effectiveness is verified with measurement results.

4.3.1 Measurement Setup

The PLL in Figure 4.6 with adjustable loop parameters has been fabricated in a

0.25-µm CMOS technology. The chip die photograph is shown in Figure 4.9. To

demonstrate the adaptive jitter minimization, a sub-sampling digital scope is used as a

proxy of the on-chip dead-zone phase detector circuit to measure the jitter of the output

clock. None of the features of the scope such as rms or p2p jitter information is used.

Instead, only the histogram data is downloaded to the computer through the GPIB port. By

counting the number of transitions (measured hits) outside a dead-zone window as a

percentage of the total number of transitions (total hits), the measurement replicates that of

a dead-zone phase detector. The number of measured hits (or percentage) is an indication

of the jitter magnitude1. The dead-zone width is adjusted when the number of measured

hits (outside the dead-zone) exceeds 1-10% of the total hits. The histogram can also model

the behavior of other jitter-measuring circuits. As an example, mentioned in Section 4.3.3,

1. The total jitter for a data-recovery system is the sum of the data jitter and sampling clock jitter.

68
the histogram can directly determine the width of dead-zone window such that the number

of hits outside the window is a fixed percentage, i.e. 4%.

D/A
D/A
PLL controlling
controlling
resistor
CP current

Figure 4.9: PLL die photograph

Figure 4.10 shows the measurement setup. The PLL loop parameters (ICP and R)

are changed by D/A converters controllable by a data-acquisition board. The digital scope

is controlled by a C-program through a GPIB interface with the PC computer.

69
 PLL TestChip 3
D/A (ICP) Data Acquisition
CK D/A (R) Board
in 4 Computer
CKout (1 GHz)
GPIB “C”
Interface program

Digital Scope

Download “Histogram Data”

Input

Trigger
Pulse
Generator 250 MHz

Figure 4.10: Test setup for the jitter measurement and optimization

Before jitter minimization algorithms being discussed, we first discuss the

sensitivity of the measurement to the total number of hits. The inherent randomness of

jitter results in some measurement error that will degrade the performance of the jitter

minimization.

4.3.2 Measurement Uncertainty

With limited number of total hits, the percentage of hits that is outside the dead-

zone window varies between measurements. The percentage forms a distribution where

the standard deviation of the distribution is inversely proportional to the total hits, N, in

the histogram. Figure 4.11-(a) illustrates four distributions of the percentage of hits

outside the dead-zone. The curves represent two values of total hits (N=500 and N=5000)

70
and two dead-zone positions (WDZ=4σ and WDZ=5σ where σ is the jitter standard

deviation). The additional shaded lines illustrate the impact on the measurement when

0.04
N=5000
WDZ=5σ
0.03
N=5000

Distribution
WDZ=4σ
(a) 0.02

N=500
N=500
0.01 WDZ=5σ
WDZ=4σ

0
0.02 0.04 0.06 0.08 0.1
#hits (% total)

2
1.8
Standard deviation (%)

1.5

(b) 1
0.79

0.5

300
0
0 1000 5000 10000 15000
#hits (N)

Figure 4.11: (a) Measured percentage hits distribution for one set of PLL loop
parameters for N=500 and N=5000, (b) standard deviation of measured percentage
hits

there is a ∆WDZ of 0.1σ. Figure 4.11-(b) shows the measured standard deviation of the

measured hits as a function of N. Increasing the number of hits from 300 to 1000 reduces

the standard deviation of the measured percentage from 1.8% to 0.79%. With very large

71
number of hits and at the cost of more hardware and time, the jitter measurement

uncertainty can be reduced such that noise of the jitter measurement circuit dominates the

uncertainty.

4.3.3 Jitter Minimization Algorithms

The simulation results in Section 4.1 shows that the total jitter due to the combined

VCO and input noise has only one global minimum without any local minima for a range

of loop parameters that the PLL is stable. Jitter can be dynamically minimized by an

algorithm that descends the gradient. However, the jitter measurement uncertainty can

degrade the performance of the descent algorithm or cause the algorithm to fail. To

understand how the uncertainty affects the algorithm, a table-lookup method is first

discussed. Then, a descent algorithm with proper initialization is described.

1) Table Comparison Method:

The simplest jitter minimization method is to use a brute force table lookup. By

measuring the jitter for all values of ICP and R during a system calibration, the results in

the table can be compared to find the global minimum. The method adapts to the jitter

environment only during explicit calibration periods. Figure 4.12 shows a table-lookup

measurement only due to VCO noise as input clock is supplied from a clean signal

generator with long-term rms jitter less than 1ps. Figure 4.12-(a) on the left illustrates a

contour of the measured hits (as a percentage of total hits) for each loop parameter setting

with the large total hits, N=30khits. The minimum jitter, shown in the figure, is in

agreement with the absolute minimum from simulation. Reducing the number of total hits

72
results in greater measurement uncertainty. The minimum value, from measuring all table

values once, may deviate from the absolute minimum. The contours, overlaid in the figure

on the right, indicate the range of possible minima for smaller number of hits (N=300 and

N=3000). As expected the contour for N=300 is larger than N=3000. Figure 4.12-(b)

15
Min jitter
x 10
6.5 15
20

15
3 3.5

2.5 x 10
9

60
9
4

15
5

3
2.
6

3.5
9
40

9
N=3000 hits

3
6
4
15

15
6
20

80
5.5 3.5 N=300 hits
64

60

3.5

4
6
15 40 15
5 20 5

Kloop
Kloop

4 4
20

9
9

9
40

4.5
(a)

6
15

15
6

15 4
4
15

6
6

9 9 9
3.5 15
9 3
20 9
3 15 15
60

40

2.5
2 4 6 8
15
-1 −8

1 2 3 4
20
5 6 7 8
(ωz) x 10
-1
(ωz)
−8
x 10

Min jitter
15
x 10
6.5 16.3
23
20

18

17. 15
30

1 40 x 10
40

23
30

18

30

6 17.1
18

30
N=3000 hits
23
20

23
18
6
20

N=300 hits
20
5.5
18

5
18
Kloop
30

5
20

30
Kloop

(b)
23

30

20
23

23
23

4.5
40
30

20

4 4
60

20

23
23 23
3.5 23
23 30
23 3
3 30
80

40 30

2.5 2 4 6 8

1 2 3 4 5
30
6 7 8
(ωz)-1 x 10
−8

(ωz)-1 x 10
−8

Figure 4.12: Jitter measurement contours (due to VCO noise) for all loop
parameters with (a) constant dead-zone width and measuring hits (percentage), (b)
constant 4% measured hits and measuring dead-zone width

73
illustrates the same measurement by finding the width of the dead-zone with 4% of the

hits outside the zone. The contours represent actual measured jitter in picoseconds. The

impact of N is also overlaid in the figure on the right. Notice that the methods yield

essentially the same results. The added uncertainty for using an N>3000hits gives

reasonably small uncertainty of <2ps or <10% of the minimum jitter.

Similar measurements are made to show the impact of the combined input and

VCO noise for all measurements. In the test setup, the VCO noise is mainly due to the

thermal noise whereas the input noise is adjustable. Figure 4.13 illustrates the contours (in

ps) for a large number of hits (N=30khits). The figure illustrates the case that the input

jitter is dominant. As the input noise is reduced, the minimum jitter moves upward toward

the minimum jitter point shown in Figure 4.12, in agreement with the simulation results.

The contours, overlaid in the figure on the right, illustrates the range of possible

minimums for smaller number of hits (N=3000 and N=300). The added uncertainty for

using N=300 is 9ps (20% minimum jitter). For N>3000, the added uncertainty is <5ps

(<10% minimum jitter). It should be noted that the local minimum seen in Figure 4.13 is

due to the errors of measuring dead-zone width. The local minima appears where the long-

term jitter difference between neighboring loop parameters is less than the measurement

error. The measured long-term rms jitter does not show any local minima.

74
 15
x 10
6.5
84 Flat range of jitter x 10
15

66

84
6

90

66
84
66 6
5.5
66

84
5
5
Kloop

59

84
4.5 90
84

N=300 hits
59
66

66

84
66

56
84

66
59
56

4 4 59
56
52
56 84 90 N=3000 hits
8
3.5

52
66 4
66 59
59 3 52

59
56
3 Min jitter 56 66

56
84
559

66
52
52 50
N=3000 hits 6
84 0

59
59
66

2.5
56

56 2 4 6 8
9

47 50 52 −8
1 2 3 4 5 6 7 8 x 10
(ωz )-1 x 10
−8

Figure 4.13: Jitter measurement contours (due to input noise) for all loop
parameters with constant 4% measured hits and measuring dead-zone width

It is important to note that the variable range of the loop parameters is bounded.

With excessively large adjustment range, the loop may become unstable and lose lock at

the extreme values. If the loss of lock occurs during calibration, it can be detected by

observing the PLL control voltage and the PLL can be forced to reset. However, the range

must be bounded if a digital step is taken while the system is active.

2) Gradient Descent Method:

Without any local minima, jitter can be dynamically minimized by an algorithm

that descends the gradient. This allows dynamic jitter minimization during run-time with

significantly fewer measurements. However, as shown in Figure 4.13, measurement

uncertainty at relatively flat regions of the jitter surface causes difficulty for the algorithm

75
to converge to the minimum. Proper initialization can improve the performance. One

viable choice is to use the table-lookup results from system calibration as the starting

point. In another option, the algorithm could be initialized with lower loop gains (Kloop =

2.5e15 in Figure 4.13). If the loop is dominated by input noise, the initialized value is

close to the optimum. If instead VCO noise dominates, the steeper slope of the surface at

lower loop gains (as shown in Figure 4.12) allows a rapid descent to the correct minimum

jitter (at a high loop-gain setting).

Figure 4.14 shows the flow chart for a descent jitter minimization algorithm. First,

the PLL is initialized to the starting values of the loop parameters (R[n], ICP[m]) and the

output clock jitter is measured. The width of the dead-zone is also initialized. Based on the

nearest neighbor measurements, the algorithm chooses the direction of descent for the first

loop parameter (R). The first loop parameter (R) is swept until the minimum jitter is found

while keeping the second parameter (ICP) constant. Then the algorithm chooses the

direction of descent for the second loop parameter (ICP) starting from (R[k], ICP[m]). The

minimum jitter for the second parameter is found for a fixed first parameter. The algorithm

repeats alternating between the two loop parameters. Several flags are used to keep track

of the neighbors to check.

Since the loop-parameter adjustments are digitally quantized, the curvature of the

jitter function, in particular as a function (ωz)-1, may be large enough such that the descent

gradient needs to be diagonal. The algorithm is designed to check diagonal neighbors once

76
a minimum is reached. An alternative is to add two more digital bits to reduce the non-

linear quantization levels at larger R values (Figure 4.6).

Initialize PLL

Upload R and ICP

values to PLL

Extract jitter (% hit or

dead-zone width)

Is current jitter no
larger than previous? Store jitter into prev.

no
yes Increment
End of parameter parameter
sweeping?

yes
Set direction flag

Are all flags no

Switch to appropriate
set? direction

yes
Count Min
reset flags

Figure 4.14: Flow chart of jitter minimization algorithm

Similar to the jitter optimization with a table method, the algorithm converges to a

range of possible loop-parameter settings. Figure 4.15 shows the histogram of the

77
movement of the algorithm. The z-axis indicates the number of times the algorithm lands

at each loop setting. For N=3000 hits, the minimum jitter mostly occurs at the global

minimum while for N=1000 the minimum jitter moves over several loop settings as the

algorithm runs. The method converges to the minimum jitter that is higher than the

absolute jitter by <10% for N=3000 (or <20% results for N=300).

(a) N = 3000hits (b) N = 300hits

No. of min jitter occurrence

No. of min jitter occurrence

100 100

50 50

0
0 1
1
0.5 0.5
( (ω 2
x 10 ωz -1 0 8
2 −7 4
6 4 x 10 z ) -1 0 8 6
−7
Kloop 15
x 10 Kloop x 10
15

Figure 4.15: Measured minimum jitter due to the sum of VCO and input noise for
(a) 3000hits, (b) 300hits

4.4 Design Considerations

The two previous sections discussed the algorithms that optimize the operating

parameters of the PLL for minimum jitter. The jitter analysis and measurements reveal

several key considerations when implementing the algorithm. First, for a rapid

convergence, the starting point of the algorithm is important. Calibrating the system upon

startup with a table of measurements would produce a near minimum initial point. As long

as the noise conditions change slowly, the algorithm will safely adapt. Second, the long-

78
term jitter magnitude must be measured and not cycle-to-cycle jitter. Adapting loop

parameters based on short-term jitter may result in an unstable loop. The paper shows that

a dead-zone phase detection circuit suffices as a measuring circuit for data-recovery

applications. However, the measurement uncertainty limits the performance. Due to the

uncertainty, an algorithm would result in an operating point that wanders over a region.

Choosing a total number of hits >3000 produces reasonable results of <5ps of added jitter

from the uncertainty. The implication of a large number of hits is that ≥12-bit accumulator

and long measurement intervals are needed.

A third issue in implementation is that the PLL needs to have adaptable loop

parameters and careful implementation is needed. Varying the loop parameters could

cause static phase offsets which would shift the dead-zone window and cause

measurement errors. In particular, with programmable charge-pump currents, dynamic

current mismatches due to output impedance variation must be accurately compensated.

Switching of digital-parameter settings will inevitably inject charge that is often

proportional to the step-size. The injected charge must be sufficiently small so that the

loop can track and not lose phase lock. To ensure that the jitter measurements circuits

collect steady-state jitter information, a delay is needed between changing the loop

parameters and collecting hits. The waiting period corresponds to the time needed for the

loop to settle well within the measurement uncertainty at the worst-case parameter

settings. Since the tracking depends on the loop bandwidth, an intelligent implementation

would adapt the waiting period based on the digital loop-parameter settings.

79
 An implementation using digitally-programmable loop parameters gives the

greatest flexibility in the design of the algorithm. A fourth issue to consider is the range

and the digital quantization of the loop parameter. The range must be bounded by the

ability of the loop to remain in lock especially if the algorithm operates when the system is

active. The quantization or resolution of the parameter adjustment has a similar constraint.

Typically, large quantization steps results in long waiting period and the risk of losing

lock. The resolution of 4-bits and 3-bits of the design shown in this paper, that provided

10x and 3x range for resistor and charge-pump current, is sufficient. However, the 4-bit

resolution for resistor is not fine enough to avoid being trapped in a false minima.

Although the jitter function is relatively flat over the minimum, the algorithm may become

stuck in the descent. The previously shown algorithm checks diagonals to alleviate the

problem. A more robust and less complex solution is to increase the resolution by two bits.

4.5 Summary
This chapter demonstrated a run-time technique that minimizes jitter at a PLL

output clock. This work addresses the considerations in the design of the PLL and the on-

chip jitter measuring circuit. Based on design considerations and jitter analysis results, an

algorithm is implemented and experimentally verified that optimizes the operating

parameters of the PLL to accommodate a changing noise environment. Without adapting

the loop parameters and not knowing noise conditions a priori, jitter can considerably be

higher than the minimum. This work shows that jitter of a PLL can be minimized to within

10% of the minimum jitter.

80
 This chapter concludes the jitter minimization method based on the PLL loop

parameters. To design a low-jitter PLL, individual blocks in a PLL should also be

designed with high immunity to noise. Due to switching activities in large digital systems,

power-supply or substrate noise, in particular, are of concern. The next two chapters

presents innovative circuit techniques in implementing PLL components and clock buffers

with high-noise performance.

81
Chapter 5

Design of PLL Components

Meeting the jitter requirement in high-performance digital systems requires design

of low-noise PLL components in the presence of power-supply or substrate noise. Supply/

substrate noise perturb the most sensitive blocks in a PLL such as voltage-controlled

oscillators (VCOs) which can significantly degrade the jitter performance of the PLL.

Prior state-of-the-art designs implement VCOs with high immunity to supply or substrate

noise with the cost of power and area. This research focuses on a new filtering technique

in the design of a VCO. The primary goal is to achieve similar noise performance as prior

designs but with less power and area overhead.

To accommodate further power optimization [15]-[16] and testability1, this work

focuses on the design of PLL that operates over a wide frequency range with adaptive

bandwidth. To accomplish the adaptive bandwidth, this research employs self-biased

1. Wide operating frequency range allows to test a microprocessor or implement multi-rate links

82
techniques in the design of the loop filter. The loop filter is also designed with digitally

controllable loop parameters to allow further jitter optimization as discussed in Chapter 3

and Chapter 4. This work also addresses the limitation of the conventional PFD. It

proposes new circuit techniques for design of high-performance PFDs that achieve larger

lock-in range with lower power consumption.

Section 5.1 demonstrates the proposed charge-pump PLL architecture. Section 5.2

discusses the design of a low-power VCO with high immunity to noise. The design of a

self-biased loop filter will be discussed in Section 5.3. The design of high-performance

phase-frequency detectors (PFDs) are introduced in Section 5.4. The measurement results

are discussed in Section 5.5. The chapter concludes with summary performance of the

proposed PLL as it is compared to prior state-of-the-art designs.

5.1 Proposed PLL Block Diagram

Figure 5.1 illustrates the block diagram of the proposed charge-pump PLL. A

three-state phase-frequency detector (PFD) is followed by a charge pump filter which

produces the VCO control voltage. The VCO is composed of a voltage to current (V-I)

converter, a current-controlled oscillator (CCO) and a noise-canceling circuit. The output

signal of the VCO passes through a low-to-full swing (L-F) amplifier and feeds back to

the PFD through a frequency divider.

83
 :N

ICP
Vctrl L-F
PFD V-I CCO
Input ICP Amp Output
Ref. R Noise- C Clock
Clock CCP Canceling
Circuit

Loop Filter VCO

Figure 5.1: The proposed PLL architecture

The primary design goals for the proposed PLL are: 1) to achieve high supply/

substrate noise rejection with adding a noise-canceling circuit to the VCO, 2) low power

and low area, and 3) to operate over a wide frequency range with an adaptive bandwidth.

The design of each PLL component is discussed in the following sections.

5.2 Design of a Voltage-Controlled Oscillator

Among all PLL components, the design of a low-jitter VCO is the most critical one

because any noise coupled into the VCO control voltage is directly translated to the

change in the oscillation frequency. The change in frequency appears as a phase error

which is persistent for the time duration equal to the time constant of the PLL. The jitter

accumulation issue becomes more sever for lower loop bandwidths or higher loop

frequency multiplications. To remedy the problem, design of a VCO with high immunity

to supply/substrate noise is required.

84
 In high-performance digital systems, CMOS delay buffers are typically used to

implement voltage-controlled oscillators (VCOs) due to their wide tuning range, portable

design and relaxed supply headroom requirement. However, they have high noise

sensitivity to their control voltage (or VDD); 1%-delay/1%-VDD. The next two sections

discuss several techniques that improve the noise performance of CMOS buffers. First, the

advantages and drawbacks of prior design techniques are discussed. The design of the

VCO with a new filtering technique will be explained next.

5.2.1 Previous State-of-the-Art VCO Designs

Two common techniques improve supply noise rejection. The first technique is to

filter the supply voltage using either a passive or active filter [51]-[55]. Designs in [51]-

[52] employ voltage regulators to filter out supply noise (Figure 5.2). Filtering a high-

VDD

Vctrl Cfilter
Regulator

Figure 5.2: Power-supply regulated VCO

frequency supply noise requires a supply coupling capacitor (Cfilter) [51] that shunts the

noise. The capacitor can occupy large area. Alternatively, a high-bandwidth regulator [52]

can compensate noise. In addition to regulating supply-voltage, [53] employs a cascode

configuration that boosts the output resistance and rejects noise. Similarly, [54]-[55] use a

85
feedback cascode to boost the output resistance of the V-I converter circuit. Figure 5.3

shows the VCO schematic with a feedback cascode, using an operational

transconductance amplifier (OTA) [54]. Although supply regulation and feedback cascode

techniques rejects the supply noise significantly, they typically consumes significant

amount of power to supply the VCO and clock buffer. A second technique is through

VDD
OTA C

Vctrl Cfilter
R

Figure 5.3: VCO with a feedback cascode using OTA

improving the supply sensitivity of VCO elements. A common design strategy employs

differential topologies. Differential VCOs and clock buffers ([39], [56]-[57]) demonstrate

improved noise performance with respect to single-ended topologies. However, similar to

filtering techniques, the differential elements consume significant power, especially in the

case of clock buffers.

The next section discusses the design of the VCO with a new filtering technique

that reduces supply/substrate noise with less power consumption and area than prior

designs.

86
5.2.2 Proposed VCO Design
The four primary goals in design of the VCO are: 1) high static and dynamic

power-supply noise rejection ratio (PSRR), 2) low power and low area, 3) wide operating

frequency range, and 4) linear gain for the entire range of the control voltage (Vctrl).

Figure 5.4 shows the proposed VCO design. To achieve a wide operating

VDD

Mp1
Mp2 Mp5
Wp Wp Wp
VDD α
VDD
I0 Mp4 α>β>1
Mn3 Rout
φ0
ISF

Mp3
φ90
Vctrl VCCO
Mn1 Mn2 CCO φ180
Icomp ICCO
IDrv Source φ270
follower
Mn4 Mn5 C
Wn β.Wn
Feedback cascode
Noise-canceling circuit
V-I Converter

Figure 5.4: Voltage-controlled oscillator with a noise-canceling circuit

frequency range, the design uses a CMOS inverter ring oscillator with controllable supply.

Figure 5.5 shows the current-controlled oscillator (CCO) circuit composing of four stages

of pseudo-differential CMOS inverters [59]. The design employs negative-skew delay

elements to enable the VCO to run faster at a given Vctrl. The CCO produces quadrature

87
clock phases, making the design suitable for applications such as clock/data recovery

circuits and multi-phase systems.

ICCO

φ270 φ135 φ0 φ225

inp- inp- inp- inp-

φ0 φ225 φ90 φ315
inn+ o- inn+ o- inn+ o- inn+ o-
inn- o+ φ inn- o+ inn- o+ φ inn- o+
180 φ45 270 φ135
inp+ inp+ inp+ inp+
φ90 φ315 φ180 φ45

ICCO

inp+ inp-

o- o+
inn+ inn-

Figure 5.5: Quadrature pseudo-differential current-controlled oscillator (CCO)

The V-I converter circuit, transistors Mn1, Mp1-Mp3, converts the control voltage

to current (IDrv) that drives the CCO and controls the frequency of CCO output signal. To

maintain linear VCO conversion gain (KVCO), Mp1-Mp3 are designed with large widths

for minimum overdrive voltage. The minimum overdrive voltage of PMOS transistors

guarantees the linear KVCO due to the fact that Mn1 stays in saturation for almost the entire

range of control voltage VCO, VTn1 ≤ Vctrl ≤ VDD, where VTn1 is the threshold voltage of

Mn1. However, at a Vctrl that is near VDD, Mn1 enters triode region which reduces the

conversion gain and saturates KVCO. To compensate for the gain drop at high Vctrl, the

88
circuit uses a source follower transistor (Mn3). Source follower is off for Vctrl - VCCO <

VTn3 and gradually turns on at high Vctrl which injects current (ISF) and compensates for

IDrv drop.

Figure 5.6 shows the simulated V-I converter gain characteristics for different

process corners. The proposed V-I converter achieves the linear gain that varies only by a

9
x 10
3.5
FF
3
VCO Clock Frequency (Hz)

2.5 FS
TT
2 SF
SS
1.5

0.5

0
0.5 1 1.5 2

Vctrl (V)

Figure 5.6: Simulated V-I converter gain characteristic across process corners

factor of less than 1.5 for almost the entire range of the control voltage (VTn1 ≤ Vctrl ≤

VDD). For instance, the KVCO varies between 1.15 and 1.7GHz/V at typical corner for

VTn1 ≤ Vctrl ≤ VDD. The slight variation of KVCO modestly impacts the loop dynamics. If

low-VT devices were available in the process technology, using one for the follower

would further improve the gain linearity at high VCO frequencies. The V-I converter in

[60] achieves a linear gain for the entire range of Vctrl (0 ≤ Vctrl ≤ VDD), slightly larger

89
than the range of this proposed V-I converter. However, the V-I converter in [60] suffers

from high power-supply noise sensitivity due to the coupling of Vctrl to both ground and

VDD. The gain linearity improvement technique proposed in this work resolves the

problem by coupling Vctrl only to the ground reference.

Further supply rejection is achieved by capacitively coupling VCCO to ground. The

capacitor and output resistor (Rout) at VCCO forms the third pole of the PLL and filters the

high-frequency noise. The cascode current source that supplies IDrv uses a feedback circuit

(Mp4 and Mn2) to boost the output impedance [55]. The resulting supply noise sensitivity

is 0.2%-VCO frequency/1%-VDD because the finite output resistance of Mn1 causes IDrv

to vary with supply. An auxiliary noise-canceling circuit (Mp5, Mn4 and Mn5) is added to

compensate the residual variation of the output current (IDrv) due to supply noise. This

circuit generates a compensator current, Icomp, by mirroring a fraction of I0. Icomp is then

subtracted from IDrv. The current to the CCO is I CCO = I Drv – I comp for

V ctrl – V CCO < V Tn3 . The ideal supply noise cancellation occurs when IDrv variation is

equal to Icomp variation due to VDD noise, i.e. ∆I Drv = ∆I comp . In other words, when

there is no supply-induced variation in ICCO, ∆I CCO = 0 . The noise-canceling circuit is

designed to have a much worse supply sensitivity than the feedback cascode circuit that

generates IDrv. The noise-canceling circuit uses a single device without the feedback

cascode and with minimum channel length. The simulation result shows that Icomp is 4
∂I comp ⁄ ∂V DD
times more sensitive to VDD variation than IDrv, i.e. ---------------------------------- = 4 . By setting the
∂I Drv ⁄ ∂V DD
β 1
ratio of the mirroring, β/α, to the ratio of the supply sensitivity of the currents ( --- = --- ),
α 4

90
∆IDrv will be equal to ∆Icomp1. The power penalty to source the same ICCO for a given

Vctrl is 40%. The proposed VCO consumes 2mW at 1GHz.

To verify the noise performance of the proposed V/I converter, the dynamic

response of VCCO to supply noise is simulated. The curves (1) and (2) shown in Figure 5.7

demonstrate the VCCO response for the V/I converter without and with the noise-canceling

circuit, when a -10% VDD step with 100ps slew rate inserted at t=2ns. Adding the noise-

canceling circuit to the V-I converter improves the PSRR by 6dB for very high frequency

797

796

795
VCCO (mV)

(4)
794
(3)
w/ noise-canceling circuit:
(2)
793

792

791
(1) w/o noise-canceling circuit
790
2 4 6 8 10
Time (ns)

Figure 5.7: VCCO response of V-I converter to -10% VDD step inserted at t=2ns

noise. Increasing the slew rate of VDD step from 100ps to 1ns and 5ns (curves (3) and (4))

improves the dynamic PSRR of the V-I converter with noise-canceling circuit to 8dB and

1. Adjusting β/α alleviates any output impedance variation over the process corners. The
simulation results indicate that the proposed VCO maintains its noise rejection performance at the
process corners by adjusting the value of β/α, 3/16≤β/α≤1/4.

91
12dB, respectively. Also, the bandwidth of the feedback cascode current source of this

design is sufficiently high to correct the high-frequency supply-induced noise in VCCO.

This bandwidth is larger than 20x the loop bandwidth of the PLL. For DC supply noise,

the PSRR is improved by more than 15dB. Equivalently, the supply sensitivity of VCO

frequency is improved from 0.2%-fVCO/1%-VDD (for the V-I converter without the noise-

canceling circuit) to ≤ 0.035%-fVCO/1%-VDD (for the V-I converter with noise-canceling

circuit).

At very high frequencies, Mn1 enters triode region, which increases ∆IDrv beyond

the available ∆Icomp. Therefore, the supply sensitivity of the VCO degrades at high control

voltages similar to regulated VCOs and differential VCOs. At very low control voltages,

the supply sensitivity also degrades due to greater susceptibility of the CCO to noise.

While the VCO has an operating range of 200-2300MHz, the simulation results indicate

that the VCO achieves the supply noise rejection of ≤ 0.035%-fVCO/%-VDD over a smaller

range of 400-2000MHz in the typical corner.

5.3 Loop Filter

Loop filter for a charge-pump PLL composes of a capacitor, C, that the charge-

pump injects the charge into or out of it. To stabilize the system, as discussed in Chapter 2,

a zero should be introduced by adding a resistor, R, in series with the loop filter capacitor.

Figure 5.8 shows the conventional loop filter, implemented with constant and linear RC.

To guarantee the loop stability under varying process or operating frequency, PLLs with

the conventional loop filter achieve a constant and relatively low bandwidth. The low

92
bandwidth results in a poor tracking jitter performance due to VCO noise as discussed in

Chapter 3.

ICP

From PFD Vctrl

ICP
R
CCP
Charge pump
Zero

Figure 5.8: Conventional loop filter

To maximize the loop bandwidth over the operating frequency range requires that

the loop gain tracks the operating frequency. In order to maintain the loop stability, the

zero should also track the operating frequency such that the loop bandwidth scales with

the operating frequency in a constant phase margin. For a second-order PLL, damping

factor, ζ, and natural frequency, ωn, are calculated from Equation 2.4 and Equation 2.8:

ζ = 0.5 ⋅ R ⋅ K loop ⁄ N
2⋅ζ [4.1]
ω n = ------------------
R ⋅ C CP

where K loop = K PFD ⋅ K VCO ⋅ I CP ⁄ ( 2πC CP ) . Equation 4.1 suggests that R ⋅ I CP

should be kept constant over the operating frequency range for a constant ζ (or
equivalently constant phase margin). With a constant ζ, ωn (or equivalently the loop
bandwidth) varies inversely with R.

Τhe designs proposed in [52], [55] and [57] employ self-biased techniques to

achieve an adaptive bandwidth PLL with a constant phase margin. These designs

93
implement the resistor through active components. Figure 5.9 shows an adaptive loop

filter [52] that uses two charge-pump currents to implement the resistor:
I CP – proportional 1
R = -------------------------------------- ⋅ ---------------
I CP – integral gm Reg

CPintegral 1/gmReg
Regulator
From PFD +
CCP Vctrl
-

CPproportional

Figure 5.9: Implementing the PLL stabilizing zero with two charge-pump currents
and a regulator

5.3.1 Proposed Loop Filter Design

Our proposed loop filter, shown in Figure 5.10, is composed of: 1) charge pump

circuit, 2) loop stabilizing zero and 3) a third pole. The design is similar to [52], [57], and

[55] in that the loop characteristics track the VCO operating frequency such that the loop

bandwidth scales with operating frequency in a constant phase margin.

ICP
Rout
Vctrl
From PFD V-I To CCO
ICP
R C
CCP Vint

Charge pump 3rd pole

Zero

Figure 5.10: Proposed loop filter architecture

94
 The charge pump uses a similar structure as [52] where it is self-biased with the

VCO control voltage (Figure 5.11). Therefore, the charge-pump current scales with the

Up
(from PFD)

Vctrl
(to VCO) Vint
2W0
W0
Dn 2W0
(from PFD)
4W0

d2 d1 d0
Controller

Figure 5.11: Charge-pump current circuit

PLL operating frequency. The series of a resistor and a capacitor forms the loop stabilizing

zero. The design implements the resistor and capacitor with a MOS channel resistance

[62] and a MOS capacitor, respectively, as shown in Figure 5.12. The MOS resistor is

Vctrl Controller
cn-1
c1
c0

Vctrl
R
R0/4 R0/2 2n-3.R0
CCP
R0 2.R0 2n-1.R0

Figure 5.12: Loop stabilizing zero with a 4-bit controller (n=4)

95
biased by the VCO control voltage so that the loop zero scales with the PLL’s operating

frequency. The proposed circuit achieves the scalable zero with a modest improvement in

power and area upon the previous designs ([52] and [57]) that use an additional charge-

pump to inject current in a feed-forward path.

D/A converters in Figure 5.11 and Figure 5.12 adjust the charge-pump current and

MOS resistor to allow further loop-parameter adjustments to optimize jitter at the output

clock as discussed in Chapter 3 and Chapter 4. The area overhead due to a 3-bit controller

for the charge-pump current and a 4-bit controller for the loop filter resistor is negligible in

comparison with the overall charge-pump area and loop filter capacitor. The tunability of

the MOS resistor also provides an additional tuning to adjust the zero position for any

process variation of the MOS capacitor.

The switching activity of PFD produces ripple on the VCO control voltage at the

same rate as the reference clock frequency. The ripple modulates the VCO frequency

resulting in jitter at the output clock. This effect worsens with higher frequency

multiplication by the loop. The loop’s third pole (formed at the CCO input) filters out the

ripple. The third pole also tracks the PLL operating frequency because the output resistor

(Rout) scales with the oscillator’s frequency. With all primary loop parameters adapting to

the oscillator frequency, the loop operates with a wide frequency range with a constant

phase margin.

96
5.4 Phase-Frequency Detector
A common architecture for clock generation uses a phase-frequency detector

(PFD) for simultaneous phase and frequency acquisition. Generating high frequency clock

increases the difficulty of the design of the PFDs particularly for systems with a high input

clock frequency and minimum frequency multiplication. As will be described in Section

5.4.1, the speed of the conventional NAND D-flip-flop phase-frequency detectors (PFDs)

limits the operating frequency and slows the frequency acquisition. This research proposes

two improved PFD designs.

5.4.1 Conventional PFD Design

Figure 5.13 illustrates a common linear PFD architecture using resettable D-flip-

CKref
Up=0
Up Dn=1
D Q CKout CKref
DFF Down State
R
Up=0
Reset Dn=0
CKref CKout
R Initial State
DFF Up State
Dn
D Q Up=1
Dn=0
CKout

(a) (b)

Figure 5.13: (a) Linear PFD architecture, (b) PFD state diagram

flops (DFFs) and its state diagram. This PFD generates an Up and a Dn signal that

97
switches the current of a charge pump. The DFFs are triggered by the inputs to the PFD.

Initially, both outputs are low. When one of the PFD inputs rises, the corresponding output

becomes HIGH. The state of FSM moves from an initial state to an Up or Down state. The

state is held until the second input goes high which in turn resets the circuit and returns the

FSM to the initial state.

The PFD’s characteristic is ideally linear for the entire range of input phase

differences from -2π to 2π (Figure 5.14-(a)). When the inputs differ in frequency, the
( T CK – T CK ) 1
phase difference changes each cycle by - .
2π ⋅ -----------------------------------------------
ref

max ( T CK , T CK )
out
On every clock cycle during
out ref

frequency acquisition, the phase difference steps across the PFD transfer curve from 0 to

+/-2π and repeats as the output clock cycle slips. The control voltage of voltage-controlled

oscillator (VCO) is pumped monotonically toward that of the desired frequency. As the

frequency error decreases, the sweep slows until the frequency difference is within the

lock-in range. Note that because phase roughly sweeps linearly and that the voltage is

integrated, the voltage accumulates quadratically between each slip of the clock cycle.

Once within the lock-in range, the cycle slipping stops and the phase is acquired, behaving

as a linear system.

However due to the delay of the reset path, the linear range is less than 4π (Figure

5.14-(b)). Figure 5.14-(c) illustrates the non-ideal behavior with the reference clock

(CKref) leading the output clock (CKout) causing an Up output. As the input phase

difference nears 2π, the next leading edge (CKref) arrives before the DFFs are reset due to

1.1Phase difference in radians referring to the slower clock frequency

98
the finite reset delay. The reset overrides the new CKref edge and does not activate the Up

signal. The subsequent CKout edge causes a Dn signal. The effect appears as a negative

output for phase differences higher than 2π - ∆ where ∆ = 2π ⋅ t reset ⁄ T cyc which depends on

the reset path delay (treset) and the reference clock period (Tcyc). Note that treset is

determined by the delay of logic gates in the reset path and is not a function of input

frequency.

Vout Vout

-2π -2π
∆φ ∆φ
2π 2π
∆
(a) (b)

Missing Clock Edge

CKref

CKout

Up

Dn

Reset

(c)

Figure 5.14: (a) Ideal PFD characteristic. (b) Nonideal linear PFD characteristic. (c)
PFD nonideal behavior due to nonzero reset delay

During acquisition, the frequency will not monotonically approach lock-in range

because the non-ideal PFD gives the wrong information periodically. The acquisition

slows by how often the wrong information occurs which depends on ∆. At an input

99
frequency ( TCKref = 2 ⋅ t reset ) where ∆ equals π, the PFD outputs the wrong information half

the time and thereby fails to acquire frequency lock unconditionally. The maximum
1
operating frequency can be expressed as f ref ≤ ------------------- .
2 ⋅ t reset

A commonly used PFD design is one used in [72] using NAND-based latches to

build the D-flip-flops. The reset path includes one 2-input NAND, one 4-input NAND and

two 3-input NANDs. We characterize the reset delay by normalizing it with the delay of a

fan-out of 4 inverter to remove process/voltage/temperature dependence. The design

measures a delay of 5.3 FO-4 thereby limiting the maximum clock period to 10.6 FO-4.

The next two sections describe two proposed designs that significantly improve

the maximum operating frequency of the PFD.

5.4.2 Pass-Transistor PFD Design

The first proposed design is shown in Figure 5.15. The PFD is similar to a dynamic

two-phase master-slave pass-transistor flip-flop. Only single-edge clocks are used to

minimize clock skew. As both outputs become HIGH, the slave is reset asynchronously

while the master is reset synchronously i.e., the reset is allowed only when the slave latch

is transparent. Synchronously resetting the master increases the operating range and also

reduces the power consumption. If the master latch is reset while it is transparent, then

there will be significant short-circuit current, resulting in more power. The synchronized

reset transistors (N1 and N4), must be at the bottom of the stack because “RST” is the late

arriving signal when the nodes “out” and “ref” are reset. The reset circuit shown in Figure

3 includes one pass transistor, one inverter and one NAND gate. In order to properly reset

100
the slave, the pass-transistor output should become HIGH before the master becomes

transparent. Hence, the NAND gate delay is counted twice in the delay path. The smaller

gates in the reset path as compared to NAND FF PFD reduces treset to 4.4 FO-4 and Tref by

17% to 8.8 FO-4.

Reset path

CKout P2
out
Up
P1 N3
N2

N1

RST

CKref P4
ref
Dn
P3 N6
N5

N4

Figure 5.15: Pass-transistor DFF PFD architecture

5.4.3 Latch-Based PFD Design

In the second proposed design, pulsed latches [73] are used instead of flip-flops

which fundamentally changes the dependence on the reset delay. This is illustrated in

Figure 5.16-(a) with the same case as before. When CKref arrives during the reset, the

edge information propagates to the output as long as CKref pulse (Pulseref) is still HIGH

(level-sensitive) when the reset period ends. The PFD no longer loses the edge that arrives

101
during reset and does not output the wrong direction. However, since the PFD output

becomes active HIGH at the end of the reset (∆), the output pulse width would be constant

(2π-∆) for phase differences greater than 2π−∆. The characteristic is shown in Figure

5.16-(b). The input clock pulse widths (Win) should be designed to be slightly smaller than

Pulseref Win < treset

CKref
∆φ ≥ 2π−δ
CKout

Up

Dn

Reset
treset
Condition for negative output voltage
(a)

Vout ∆

−2π −π π 2π
∆φ
δ

(b)
Figure 5.16: (a) Behavior of a latch-based PFD, including the description of the
nonideal behavior origin. (b) characteristic of a latch-based PFD

treset, otherwise the PFD would fail to lock at zero input phase difference. The PFD failure

is due to the fact that the input clock pulse that triggers the reset would activate the output

after the reset pulse ends for W in ≥ t reset . This design criteria results in a negative output

102
voltage for ∆φ ≥ 2π – δ as illustrated in Figure 5.16-(a) and (b). Note that this PFD has

faster acquisition rate compared to the first type (with the same operating frequency)

because it outputs less incorrect phase information. However, the PFD has a gain that

saturates when the input difference is larger than 2π−∆.

Figure 5.17 illustrates design of the latch-based PFD [74], using glitch latches. The

Reset path
P2 P1

Dn Up
N4 N1
Pulseref Pulseout
CKref RST CKout
N5 N2
Generates Pulsed Clock
D N6 N3 D

Inverted Delay Inverted Delay

Figure 5.17: Latch-based PFD architecture

delay elements control the pulse width of the clocks. As shown in Figure 5.17, the reset

circuit includes two inverters and one NAND. The reset also traverses the circuit twice

because the reset should return HIGH. Therefore, treset delay is roughly 5.5 FO-4 and

contains three inverters and two NANDs. As the clock period is less than twice the pulse

width, the clock pulses from N2 (N5) and N3 (N6) are no longer constant width but reduce

with the period. Therefore δ is no longer constant and grows with increasing frequency.
1
The PFD fails as frequency approaches ------------
t reset
which is potentially twice that of the

previously proposed PFD for the same treset. Consequently the maximum frequency is

103
higher than the DFF-based designs despite longer treset. The higher performance is at a

cost of 3x the power as compared to the first proposed circuit due to DC current and extra

power consumption in the delay circuit. When the reset node and clock inputs are

simultaneously LOW and HIGH respectively, the DC current flows through N1, N2, N3

and P1 or (N4,N5, N6 and P2).

It should be noted that the first PFD design (Figure 5.15) can also be converted to

latch-based type PFD by adding a delay cell to the gate inputs of P1 and P3 transistors.

The delay allows P1 and N3 (P3 and N6) to both conduct briefly, behaving like a glitch

latch. This new design has the similar functionality as PFD in Figure 5.17 in terms of

frequency acquisition, maximum operating frequency and power.

5.4.4 Simulated Transfer Curve of PFDs

Figure 5.18 illustrates the simulated transfer curve of NAND DFF PFD and two

proposed designs (Figure 5.15 and Figure 5.17) for reference clock of 435 MHz

(= 1 ⁄ ( 10 • FO – 4 ) ). Figure 5.19 compares the simulated frequency acquisition for three

PFDs, starting the VCO at 375 MHz and locking at 800 MHz. As expected, the PLL with

latch-based PFD has the fastest frequency acquisition among the three PFDs.

104
 Vout

∆φ
-2 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2 (× π)

Pass Transistor DFF PFD

Latch-based PFD
NAND DFF PFD

Figure 5.18: Characteristics of three PFDs at 435MHz

1.28

1.24
VCO control voltage (v)

1.2 Latch-based PFD

1.16 Pass Transistor

DFF PFD

NAND DFF PFD

1.12

1.08

1.04

20n 60n 100n 140n 180n 220n 260n

Time (s)
Figure 5.19: Simulated frequency acquisition

105
5.5 Measurement Results
The PLL and clock buffer1 have been designed and fabricated in a 0.25-µm CMOS

technology. As shown in the chip micrograph, Figure 5.20, the PLL core area is 0.028mm2

(120µm x 230µm).

120 µm
PLL

230 µm

Clock Buffer

Figure 5.20: PLL and clock buffer die photograph

The measured VCO operating frequency is 130-1600 MHz. Figure 5.21 depicts

the measured VCO gain indicating that the gain varies only between 0.9-1.35 GHz/V for

the entire range of control voltage.

1. The design of noise-compensated clock buffer is discussed in Chapter 6

106
 9

120 µm
x 10
2.5

VCO Output Clock Frequency (Hz)

er
orn
T Tc
2 @
t io n
u la r
S im n t rne
me o
Sc
1.5
ure S
e as n @
M ti o
1
m u la
S i

0.5

0
0.5 1 1.5 2 2.5
VCO control voltage (V)

Figure 5.21: Measured and simulated VCO gain

The input reference frequency generated by a signal generator is set to 250 MHz

and the loop multiplication factor is four. The long-term jitter performance of the PLL

output at 1 GHz is demonstrated in Figure 5.22. The jitter histogram measures the rms

RMS = 3.28 ps
P2P = 28.89 ps

Figure 5.22: PLL output jitter histogram at 1GHz

107
jitter at 3.28 ps and P2P jitter at 28.89 ps (> 45 Khits) without the supply noise. The

measured power consumption is 10mW at 2.5-V supply and 1-GHz output clock

frequency.

To characterize the sensitivity of the VCO frequency to supply noise, both static

and dynamic VCO supply sensitivity measurements are performed. For static

measurement, the DC value of the supply is varied by ±10% and the frequency variation

of free-running VCO is measured. Figure 5.23 demonstrates the measured sensitivity

results expressed in %-fVCO/%-VDD. The measurement results indicate that the VCO

achieves ≤ 0.03%-fVCO/1%-VDD at low frequency supply noise for 0.8 ≤ Vctrl ≤ 1.7 (in

terms of frequency, 300 MHz ≤ fVCO ≤ 1.4 GHz). At Vctrl greater than 1.7V, where the

noise-canceling circuit becomes less effective, the noise sensitivity increases to 0.25%-

fVCO/1%-VDD. The dynamic sensitivity of the VCO is characterized by measuring the

overall jitter performance of the PLL to high frequency noise. A ±10% supply step with 1-

ns slew rate (the fastest possible on-chip frequency) is injected to the VCO supply and the

P2P jitter at PLL output clock is measured. Figure 5.23 demonstrates the measured long-

term P2P jitter expressed in terms of the percentage of the PLL output clock period, %-

TPLL. The measurement results indicate that the PLL achieves the jitter performance of ≤

0.1%−ΤPLL/1%−VDD step, with the VCO frequency varying from 800 ΜΗz to 1.4 GHz.

The PLL bandwidth is set to roughly 1/40th of VCO frequency1.

1. The loop multiplication factor is four.

108
 8
x 10 0.25 Static (VCO)
16
0.2 Dynamic (PLL)
%-fVCO 0.03
14
%-VDD 0.09
0.03

VCO Frequency (Hz)

12
0.03
0.03
10
0.03 0.07
8
0.02
0.1 %-TPLL
6 %-VDD
0.17
0.02
4
0.3
2

0
0.6 0.8 1 1.2 1.4 1.6 1.8 2
Vctrl (V)

Figure 5.23: Measured sensitivity of VCO output clock frequency to static and
dynamic supply noise

To verify the performance of the proposed PFDs, the three PFDs and PLL

proposed in [52] are fabricated in a 0.25-µm CMOS technology. The die photogragh is

shown in Figure 5.24. The first and second circuits show 18.5% and 41.7% improvements

in maximum locking frequency compared to NAND DFF PFD, respectively. The

measurement results match the simulated FO-4 results.

109
 Loop Filter
Integral CP OPamp
Proportional CP VCO
Latch-based PFD : N
PFD

Loop Filter
Integral CP OPamp
Proportional CP VCO
NAND DFF PFD : N
PFD

Loop Filter
Integral CP OPamp
Proportional CP VCO
Pass Transistor PFD : N
DFF PFD

Figure 5.24: Die photograph of three different PFDs implemented in a PLL

The measured frequency acquisition time of PLLs are depicted in Figure 5.25 for

all three PFDs. To analyze the frequency acquisition, a reference clock of 1 GHz is

supplied while the VCO frequency is initially reset to 200 MHz. Sampling circuits

monitor the VCO control voltage as the PLL’s reset is disabled. The loop acquires lock

with a slightly underdamped behavior. The latch-based PFD has a 1.7x faster acquisition

110
rate than the NAND DFF PFD and is 1.4x faster than the pass transistor DFF PFD. Note

that the PFD with fast acquisition has larger lock-in range.

PLL reset

VCO control voltage

Latch-based PFD
Pass Transistor DFF PFD
NAND DFF PFD

Figure 5.25: Measured frequency acquisition

Table 5.1 summarizes the measured and simulated power consumption and speed

performance of each PFD. The power consumption is calculated for PFDs in the lock

mode for the reference clock of 500 MHz. The pass-transistor DFF PFD consumes the

least power as predicted.

111
 Table 5.1: PFDs performance summary

NAND DFF PFD Pass Transistor DFF Latch-based PFD

(Type I) PFD (Type I) (Type II)

Maximum operating fre- 1.08 GHz 1.28 GHz 1.53 GHz

quency (Measurement)

Maximum operating fre- 0.945 GHz 1.14 GHz 1.5 GHz

quency (Simulation)

Lock-in range @ 1 GHz 133 MHz 160 MHz 200 MHz

(Measurement)

Power 1.65 mW 0.62 mW 1.4 mW

5.6 PLL Performance Comparison

Table 5.2 and Table 5.3 compare the performance of the proposed PLL (and VCO)

with prior state-of-the-art designs. The first two designs by Sidiropoulos [52] and Ingino

[51] are examples of the regulated VCOs whereas the designs by Kaenel [54] and Ahn

[55] are examples of V-I converters with cascode current sources. The design by Maneatis

[57] is an example of the differential VCO and finally, the design by Minami [60] is an

example of a V-I converter with linear gain for the entire range of the VCO control

voltage. For a fair comparison, all designs are normalized to 0.25-µm technology with

2.5V supply by the use of scaling equations for the short-channel and long-channel

devices. The proposed design achieves the lowest power and area among all designs while

achieving comparable noise performance with the regulated VCO proposed in [52]. The

regulated VCO proposed by Ingino achieves an excellent dynamic noise rejection of

0.007%/1% by coupling the VDD to ground with a large capacitor of 1.2nF and with

higher power consumption. While the area and noise rejection performance of the

proposed PLL is comparable with [52], it consumes 43% less power than the design in

112
[52]. With a comparable power consumption, the proposed PLL achieves better dynamic

noise rejection than the VCO in [54].

Table 5.2: PLL performance comparison (1)

S. Sidiropoulos J.M. Ingino V. Kaenel H. Ahn

VLSI ‘00 ISSCC ‘01 JSSC ‘96 JSSC ‘00
0.35µm, 3.3V 0.15µm, 0.35µm, 1.35V 0.25µm, 1.9V
3.3 & 1.5V

Power 21.5mW 132mW 1.2mW 25mW

@ 500MHz @ 4GHz @ 320MHz @ 360MHz

Normalized (f, λ, V)a 17.5mW > 31mW 9.2mW 60mW

power
Area 0.047mm2 1.48mm2 0.21mm2 0.087mm2

Normalized (λ) area 0.024mm2 4.1mm2 0.107mm2 0.087mm2

VCO frequency range 30-650MHz 0.6-4GHz 176-574MHz 17-1320MHz

Jitter (long-term) w/o

VDD noise:
P2P 44ps (@
rms 700MHz)

Normalized (f) Jitter

(long-term):
P2P 30.8ps
rms

Static sensitivity: 0.008%/1% 0.074%/1%

(%-fVCO/%-VDD) (1ps/52mV) (±2.6ps/100mV)

Dynamic sensitivity: 0.06%/1% 0.007%/1% 0.18%/1% 0.32%/1%

(%-fVCO/%-VDD) (PSRR ~ 24dB) (PSRR>43dB) (1ps/2.5mV) (±12ps/100mV)

a. f, λ and V indicates the normalization with frequency, technology and voltage, respectively.

113
 Table 5.3: PLL performance comparison (2)

J. Maneatis K. Minami This work

JSSC ‘96 CICC ‘01 0.25µm,
0.5µm, 2.1V 0.1µm, 2.5V
1.2V

Power 9.24mW 30mW 10mW

@ 250MHz @ 2GHz @ 1GHz

Normalized (f, λ, V)a 26mW 163mW 10mW

power
Area 1.91mm2 0.15mm2 0.028mm2

Normalized (λ) area 0.48mm2 0.94mm2 0.028mm2

VCO frequency range 0.0025-550MHz 0.5-2.35GHz 0.2-2GHz

Jitter (long-term) w/o

VDD noise:
P2P 21ps 28.89ps
rms 2.8ps 3.28ps

Normalized (f) Jitter

(long-term):
P2P 42ps 28.89ps
rms 5.6ps 3.28ps

Static sensitivity: 0.005%/1% 0.03%/1%

(%-fVCO/%-VDD) (0.25%/V)

Dynamic sensitivity: 0.37%/1% 0.07%/1%

(%-fVCO/%-VDD) (704ps/V)

a. f, λ and V indicates the normalization with frequency, technology and

voltage, respectively.

5.7 Summary
To produce low-jitter clocks in noisy supply environments, we demonstrated an

effective supply rejection technique for the VCO. The proposed VCO achieves high

supply noise rejection comparable to that of a regulated supply VCO with lower power

consumption. The VCO operates over a wide operating frequency range and has a linear

114
voltage-to-frequency gain. The PLL design demonstrates scaling loop parameters with the

oscillator’s frequency that tracks over a 10x frequency range. The self-biased design

allows the PLL to operate over a wide frequency range with an adaptive loop bandwidth

and a constant phase margin. The proposed PFDs acquire frequency lock faster and

consume less power than the traditional PFD.

The generated on-chip clock by the PLL should be distributed through clock

buffers to the entire system with small uncertainty. Next chapter discusses the design of a

noise-compensated clock buffer.

115
Chapter 6

Design of Clock Buffer

One of the challenges in digital systems is the distribution of the generated on-chip

clock with a small uncertainty. Static CMOS inverters are traditionally used for clock

buffering due to their simplicity and drive capability with low power consumption.

However, CMOS inverters have poor supply-induced delay sensitivity of approximately

1%-delay/1%-VDD. With long chains, this poor supply noise rejection of the inverter

could result in significant jitter. For example, in IBM S/390 microprocessor [76], the

generated on-chip clock is distributed through clock buffers to all latches in three levels of

H-like tree hierarchy. The total simulated delay is about 750ps. The amount of jitter with

10% supply noise is roughly 75ps which is 3% of clock period of 400MHz. As technology

scales down1 and clock frequency increases, jitter becomes a larger fraction of the clock

period and may cause system to fail. To reduce jitter, the delay sensitivity of the clock

1. The delay of interconnect is not scaling down as fast as technology does [77].

116
buffers should be improved. One method of improving the supply noise rejection is by

filtering, using a regulator or RC filter. These techniques require large capacitors and

hence area. This chapter introduces a compensator circuit added to the inverter that offsets

any supply-induced delay variation. This circuit technique supplements other methods of

reducing supply noise.

6.1 Concept of Noise Compensation

Ideally, the task of the noise compensator circuit is to introduce an inverse and

equal delay sensitivity to the supply noise as an inverter (Figure 6.1-(a)). This noise

compensation can be accomplished by using a variable capacitor at the output of each

inverter such that as VDD drops, the capacitor value decreases to compensate for inverter

delay increase and vice versa. A simple circuit capable of the delay compensation is a

MOS resistor in series with a capacitor. Figure 6.1-(b) shows the clock buffer with the

compensator circuit, where the capacitor and resistor are implemented by PMOS

transistors1. The gate voltage of the PMOS resistor, Vgap, is set to a constant voltage with

respect to ground. As VDD drops, the source-gate voltage (VSG) of the PMOS resistor is

decreased, increasing the resistance, R. Thus, the capacitor, C, appears as a lower

capacitive loading, which compensates for the increase in the inverter’s resistance.

1. If the PMOS resistor and capacitor are switched in the compensator circuit, the circuit is similar to
delay elements commonly used for variable-delay lines [63]. However, this configuration is undesirable for
the noise compensation because the VSG is decoupled from VDD by PMOS capacitor whereas the VSG in
Figure 6.1-(b) experiences the VDD noise directly.

117
 Compensator circuit
VDD
+
VSG
Vgap - R
KT
Inv mp. C
. Co Cfilter
Delay Comp. Inv. C
VDD

CKin CKout
0.9 1 1.1 ×VDD Inv
Compensated inverter
(a) (b)

Figure 6.1 (a) Ideal compensation of supply-induced inverter delay variation, (b)
proposed compensator inverter

One of the main advantages of this compensation technique is the circuit’s

excellent dynamic behavior due to a very small time constant of the compensator circuit.

The compensated inverter can have a high power-supply rejection ratio (PSRR) for both

low and high supply noise frequencies. A regulator in comparison would have a larger

time constant with a large filter capacitor. Also, for most applications, the supply noise

does not exceed ±15% of supply voltage [49]. Thus, the extra capacitive loading

introduced by the compensator circuit would be within 10-15% of the inverter’s load and

does not change the fanout of the inverter significantly. Due to the small loading effect, the

delay and power overhead added by the compensator circuit are a small fraction of the

inverter’s total delay and power.

118
6.2 Design Implications
To achieve the high PSRR in the compensated inverter, the compensator circuit

should provide an inverse and equal delay variation (from VDD noise) as the delay

variation of an uncompensated inverter. While the delay variation of an inverter is roughly

proportional to VDD, the delay variation of the compensator circuit varies non-linearly

with VDD. Figure 6.2-(a) shows the non-linear behavior of the delay variation of the

compensator circuit as a function of VSG. For minimum power, delay and area overhead,

the compensator circuit should be used over the range where it achieves the maximum
∂ V SG
delay sensitivity; Sensitivity =  delay ⋅ -------------- . The maximum delay sensitivity
 ∂ V SG  delay
occurs over the VSG range where the resistance of the PMOS device, R, is the most

sensitive to the VSG variation. V SG in Figure 6.2-(a) indicates the middle of the region
max

with maximum delay sensitivity. Therefore, Vgap should be set to

V gap = V DD – V SG . The delay variation of the inverter is well compensated over

nom max

the range of ∆VDD ( = V DD – V DD ) where the delay sensitivity of the compensator

nom

circuit approximates the delay sensitivity of the inverter. For VDD noise exceeding this

range, the delay compensation performance of the compensator circuit degrades. Figure

6.2-(b) shows the desired delay sensitivity of the compensator circuit (normalized to the

supply-induced delay sensitivity of the uncompensated inverter) for a proper delay

compensation. The voltage range where the normalized sensitivity curve crosses one is

when the compensator circuit compensates for the delay variation of the uncompensated

119
inverter due to VDD noise. The delay sensitivity and the compensating range of the

compensator circuit are adjusted through sizing the devices in the compensator circuit.

−10
x 10

4.5 VSG = 1.1V (or Vgap = 1.4V)

Delay (s)
max
4 (a)

3.5

0 0.5 1 1.5 2 2.5 VSG (V)

Normalized Delay

1
Sensitivity

0.5
Comp. (b)
range

0
0 0.5 1 1.5 2 2.5 VSG (V)

Figure 6.2 (a) Delay variation of compensated inverter due to VSG variation, (b)
delay sensitivity of compensator circuit, normalized to delay sensitivity of an inverter

6.2.1 Design of the Compensator Circuit

Figure 6.3 illustrates the behavior of the delay sensitivity of the compensator

circuit (normalized to the delay sensitivity of the uncompensated inverter) as the PMOS

resistor and capacitor vary. Figure 6.3-(a) shows the delay sensitivity behavior as a

function of the capacitor while keeping the width of PMOS resistor constant. Using a

larger compensating capacitor as a fraction of the total capacitive load of the inverter

increases the delay variation and, hence, the delay sensitivity of the compensator circuit.

However, increasing the capacitor reduces the compensating range. Figure 6.3-(b) shows

similar curves, varying the PMOS resistor value in a constant capacitor value. Decreasing

120
the resistor value increases the delay sensitivity by introducing larger capacitive loading to

the inverter while reducing the compensating range. By proper adjustment of the resistor

and capacitor, both the maximum normalized delay sensitivity and the compensating

range can be set to one and peak-to-peak supply noise, respectively. Curve (2) in Figure

6.3-(a) or (b) is an example of the proper sizing that roughly results in the same delay

sensitivity as an inverter within the operating range of ±10% VDD noise.

Increasing C
(1)
1
Normalized Delay Sensitivity

(2)
C(1)>C(2)>C(3) (a)
(3)
of Compensator Circuit

0.5

Constant WR
0 VSG (V)
0 0.5 1 1.5 2 2.5

Decreasing R
1
(1) R(1)<R(2)<R(3)
(2)
0.5 (3) (b)

0
Constant C
0 0.5 1 1.5 2 2.5 VSG (V)

Figure 6.3 Behavior of normalized delay sensitivity of compensator circuit due to

VSG (VDD) variation as a function of: (a) PMOS capacitor, (b) PMOS resistor

Figure 6.4 illustrates the simulated delay compensation characteristics of the

compensated inverter (with R and C values of curve (2) in Figure 6.3) when VDD varies by

±10%. Curve(1) illustrates the supply-induced delay variation of the compensated inverter

while keeping VDD of the compensator circuit constant. This curve represents the delay

variation of an uncompensated inverter. Curve(2) illustrates the supply-induced delay

variation while keeping VDD of the inverter constant. This curve represents the delay

variation solely due to the compensator circuit. Curve(3) shows the overall delay variation

121
of the compensated inverter to VDD noise. Curve(3) is effectively an average of the first

two curves. The overall delay sensitivity of the compensated inverter is approximately

0.1%-delay/%-VDD for VDD variation of ≤ ±10%.

−10
x 10
4.4

Delay sensitivity of Compensated 4.2

(1) (2)
4
Inverter (s)

3.8 (3)

3.6

3.4

3.2
2.3 2.4 2.5 2.6 2.7
VDD (V)

Figure 6.4 Supply-induced delay variation of: (1) uncompensated inverter, (2)
compensated inverter with inverter’s VDD held constant and (3) compensated

Although the delay sensitivity metric has been traditionally used to illustrate the

circuit noise performance, the overall delay variation of curve(3) in Figure 6.4 suggests

another useful metric. Since the delay may not change linearly with VDD variation, the

alternate metric is defined as the maximum percentage delay variation from its nominal
∆delay max ∆V DD
value ( ------------------------------- ⋅ 100 ) within the VDD noise range ( -------------- ⋅ 100 ). The maximum
delay nominal V DD
delay variation for curve(3) is 1.2% within ±10% VDD noise.

122
6.2.2 Bias Circuit for Vgap

The previous discussion of the delay compensation indicates that the bias circuit

for Vgap must be constant with respect to ground. Also, the optimum biasing point for the

Vgap (the middle of the voltage range with the maximum delay sensitivity) varies across

process corners, as PMOS devices become faster or slower. To maintain the high PSRR

across the corners, the biasing circuit for Vgap should track the variation of the PMOS

threshold such that Vgap is set to the middle of the compensating range. Therefore, the

desired Vgap should compose of a voltage that is independent of supply and PVT (a

bandgap reference) and a voltage that depends on the PMOS threshold voltage. Figure 6.5

shows a realization of the bias circuit. A diode connected PMOS transistor is biased with a

small current such that VSG ~ |VTp|. To generate Vgap, the |VTp| is subtracted from an

amplified bandgap voltage.

Bandgap Vbg
Circuit + (1+R2/R1).Vbg
- +
R1 R ~VTp
-
R2 Vgap = (1+R2/R1).Vbg - VTp

W1 W2
W1>>W2

Figure 6.5 Bias circuit generating Vgap

123
 The generated Vgap bias is distributed to the entire clock buffers. Due to the

coupling noise into Vgap, there is uncertainty in the Vgap voltage from buffer-to-buffer.

The deviation of Vgap from the middle of the compensating range decreases the effective

compensating range. Figure 6.6 shows the simulated delay variation of the compensated

inverter for the optimum Vgap, and ±100mV deviation from the optimum Vgap. The

maximum delay variation increases from 1.2% (within ±10% VDD noise) at the optimum

Vgap to 2% and 2.7% at 50mV and 100mV of the offset in the Vgap value, respectively.

The uncertainty in the Vgap can be reduced by minimizing the coupling capacitors with a

careful layout design. Also, the Vgap uncertainty can be significantly suppressed by

supplying the clock buffers with their own local Vgap bias generator with the cost of power

and area overhead added by each Vgap bias circuit.

400
Vgap = 1.3V
1.35V
380 Vgap = 1.4V (optimum)
1.45V
Delay (ps)

360
1.5V
TT,
Un
340 c om
pen
sat
e d in
320 v er
te r

300
2.3 2.4 2.5 2.6 2.7
VDD (V)

Figure 6.6 Sensitivity of supply-induced delay variation of compensated inverter due

to Vgap offset

124
6.2.3 Performance Sensitivity to PVT1
To characterize the performance of the delay compensating technique, the

compensated clock buffer is simulated over temperature and process variations. As the

temperature increases, the Vgap increases due to the negative sensitivity of VTp to the

temperature (~ -1mV/K). Figure 6.7 demonstrates the supply-induced delay variation of

the compensated clock buffer as the temperature varies between 0o to 125o. Increasing the

temperature from 25o to 125o increases the maximum delay variation from 1.2% to 2.4%

(within ±10% VDD noise).

−10
x 10
4.4
TT, Temp = 125oC (Vgap = 1.5V)
Delay of Clock Buffer (s)

4.2

4
TT, Temp = 25oC (Vgap = 1.4V)
3.8

TT, Temp = 0oC (Vgap = 1.375V)

3.6

TT, U
3.4 nc o mp e
n sa t e
d inv
3.2 e rt e r
at 25 o
3
C
2.3 2.4 2.5 2.6 2.7
VDD (V)

Figure 6.7 Delay variation of compensated clock buffer over temperature as VDD
varies ≤ ±10%

Figure 6.8 shows the supply-induced delay variation across the process corners where

Vgap tracks the PMOS threshold variation. The maximum delay variation increases to

1. Process, voltage or temperature variations

125
2.5% (within ±10% VDD noise) at fast NMOS corners in the worst case. The PSRR

degradation at fast NMOS corners is due to the fact that neither the compensated circuit

nor the Vgap voltage tracks the NMOS corner variation. To further improve the PSRR, a

series of an NMOS capacitor and resistor can be added to the compensator circuit.

−10 (SS: Slow NMOS, Slow PMOS)

x 10
5
SS, Vgap = 1.27V
Delay of Clock Buffer (s)

4.5

SF, Vgap = 1.53V

4
TT, Vgap = 1.4V

TT, U FS, Vgap = 1.27V

nc om
3.5 pe ns a
ted in
verte
r
FF, Vgap = 1.53V
3
2.3 2.4 2.5 2.6 2.7
VDD (V)

Figure 6.8 Delay variation of compensated clock buffer across the corners as VDD
varies ≤ ±10%

Five stages of fanout-4 compensated inverters as shown in Figure 6.9 are used for

simulation. The optimum sizes of the PMOS resistor and capacitor are 0.5x and 3x the

PMOS transistor width size in the preceding inverter stage. The simulated power and

delay increase due to the compensator circuit (Vgap bias circuit is not included) are 25%

and 12% of the conventional clock buffer (uncompensated inverter), respectively.

126
 VDD VDD
Vgap R0 Rn-1
0.5.Wp0 0.5.4n-1.Wp0
Cfilter
C0 3.Wp0 Cn-1 3.4n-1.Wp0
VDD
VDD VDD
Wp0 4.Wp0 4n-1.Wp0
CKin CKout
Wn0=Wp0/2 4.Wn0 4n-1.Wn0
Inv0 Inv1 Invn-1 Cload = 4n.
(Wp0+Wn0)

Figure 6.9 Five stages of fanout of four (FO-4) compensated inverters (n=5)

6.3 Measurement Results

To characterize the delay sensitivity of the clock buffer, both static and dynamic

VDD variations are measured. Five stages of FO-4 inverters and compensated inverters are

fabricated in 0.25-µm CMOS technology1. The compensator inverters includes the PMOS

compensator circuit only. For the measurement purpose, a separate power supply is used

to supply the Vgap instead of the bias generator shown in Figure 6.5. Vgap is held constant

as VDD noise is injected. The measurement results shown in Figure 6.10 indicates that the

compensated clock buffer at optimum Vgap=1.45V has a maximum delay variation of

3.8% within ±10% VDD noise for a slow corner device, which is 5x less than the

uncompensated inverter. The measured maximum delay variation of the compensated

1. Clock buffer die photo is shown in Figure 5.20

127
clock buffer is greater than the simulation results in a typical corner (1.2% within ±10%

VDD) due to not tracking the NMOS process variation and also the parasitic capacitances.

The supply noise rejection performance can be improved by adding an NMOS

compensator circuit.

750
Delay of Clock Buffer (ps)

700

Compensated Inverter, Vgap = 1.45 V V

ga
650 p =0

600
Unc V
omp ga
p= V
ens DD
550 ated
Inve
rter
500

450
0.9 0.95 1 1.05 1.1 × VDD (= 2.5V)

Figure 6.10 Measured supply-induced delay variation of uncompensated (--) and

compensated clock buffer

For comparison, Figure 6.10 also demonstrates the performance of the

compensated clock buffer for Vgap values far from the optimum Vgap=1.45V. The

measured result at Vgap=0 shows an increased maximum delay variation to 5.7% (within

±10% VDD noise) and for Vgap=VDD, where the PMOS resistor is off, the maximum delay

variation becomes 22%, which is roughly the same as that of an inverter. The measured

power and delay overhead are 30% and 18%, slightly greater than simulation results due

to the parasitic capacitances. The area overhead, excluding decoupling capacitors, is 50%

128
as compared to inverters alone. The overhead numbers do not include the overhead due to

the Vgap bias generator.

6.4 Summary
To distribute low-jitter generated on-chip clocks in noisy supply-noise

environments, an effective supply noise compensation technique has been demonstrated

for the clock buffer. The proposed clock buffer achieves high supply-noise rejection with

an excellent dynamic behavior and with small area and power overhead. This technique

can supplement existing supply filtering using decoupling capacitors and supply-voltage

regulation. The design dissipates low power for its jitter performance and has low area

overhead.

129
Chapter 7

Conclusion

This dissertation has shown the generation and distribution of low-jitter on-chip

clocks for low-power applications in noisy supply environment. The major noise sources

in a PLL were discussed: VCO internal noise, clock buffer noise and input (reference)

clock noise. The performance of circuits to supply noise is characterized with noise

sensitivity metric; %-delay/%-VDD. This is a useful metric that reports the delay variation

of buffer element in percentage per percentage of supply variation rather than absolute

value. Therefore, it can conveniently be used to compare the noise performance of various

designs in different technologies.

To generate and distribute a clock with small uncertainty requires to reduce the

noise sensitivity of the most sensitive blocks in a PLL, i.e., VCO and clock buffer. Priors

state-of-the-art designs regulate and filter the supply-voltage or use differential delay

elements to significantly improve the noise performance. However, they typically

consume large power to supply delay elements and occupy large area due to decoupling

130
capacitors. To overcome power and area issues associated with the prior designs, this

research proposes two new filtering techniques that effectively improves the noise

sensitivity of VCO and clock buffer with small power and area overhead. Furthermore,

both techniques demonstrate an excellent dynamic behavior with a faster response time

than the time constant of the PLL. The faster response time enables the VCO (or clock

buffer) to correct for errors introduced by high-frequency noise much faster than the loop

response of the PLL.

While the proposed filtering techniques are proved to reduce the jitter at PLL

output clock significantly, further improvement is achieved through appropriate filtering

of various noise sources with PLL closed-loop feedback system. Investigation to the

impact of PLL loop parameters on output jitter reveals that the loop parameter settings at

which minimum jitter occurs depends on the dominant noise source in a PLL. Therefore,

to achieve the minimum jitter performance based on the loop parameters requires

knowledge of the dominant source.

For most systems, the dominant noise source is not well-known. To minimize jitter

under different noise conditions, a run-time methodology measures the jitter on-chip and

adjusts the PLL loop parameters toward minimum jitter performance based on gradient-

descent algorithm. A dead-zone phase detection circuit suffices as a measuring circuit for

data-recovery applications. However, the measurement uncertainty limits the

performance. The implication of a large number of hits is that ≥12-bit accumulator and

long measurement intervals are needed. The range of loop parameters must be bounded by

131
the ability of the loop to remain in lock especially if the algorithm operates when the

system is active. The quantization or resolution of the parameter adjustment is determined

such that there is no risk of losing lock.

To accommodate testability and further power optimization, a PLL with wide

frequency range and adaptive bandwidth is designed. To accomplish the adaptive

bandwidth, we used self-biased techniques in the design of the loop filter. Also, this

research addresses the drawback of the conventional PFD and proposes new circuit

techniques to design PFDs. The proposed PFDs consume lower power and achieve wider

acquisition range than conventional PFDs.

The PLL and clock buffer were fabricated in 0.25-µm CMOS technology.

Experimental results indicate that both VCO and clock buffer demonstrate the delay

sensitivity of ≤ 0.1%-delay/1%-VDD. VCO consumes only 2mW at 1GHz from 2.5-V

supply. The total power consumption of PLL is 10mW at 1GHz. Using the run-time

adaptive method of minimizing jitter for the PLL minimizes jitter to within 5ps of the

minimum peak-to-peak jitter as noise conditions are changed. The PLL demonstrates

scaling loop parameters with the oscillator’s frequency that tracks over a 10x frequency

range.

This research points to several areas of potential future work. Although the

performance of the circuits proposed in this thesis has continued to scale down with

improving fabrication technology1, it still needs to be validated for deep-submicron

technologies less than 90nm. Understanding and overcoming scaling limitations can be an

132
interesting area for future work. Design of PLL circuits might require innovative design

techniques or architectures to maintain close to desired performance anticipated with

scaling.

In this work, we proposed a new filtering technique that effectively compensates

for noise. We have successfully shown the successfulness of this technique by

implementing a compensated clock buffer. One might benefit form this technique due its

lower overhead and excellent dynamic behavior. Thus, another interesting area of research

is to extend the noise compensation concept to develop new circuit techniques with better

noise performance while introducing lower overhead.

Noise sources in digital systems are not well known and also the noise conditions

could be changed. We developed a run-time algorithm that dynamically minimizes jitter.

However, this algorithm has its own implications such as error in on-chip jitter

measurement, required resolution and range for loop parameters that impacts the

performance of algorithm. Understanding and developing new algorithms with shorter

convergence time are interesting subjects. Although a dead-zone phase detector suffices

for clock/data recovery applications as shown in this work, an appropriate on-chip circuit

to measure the jitter of a clock’s system is a challenge.

Finally, supply or substrate noise are the most dominant noise sources in digital

systems. To achieve a low-jitter performance in such systems requires a good

1. From starting point of this research, the design has been fabricated in three process
technologies: 0.35µm [41], 0.25µm and 0.18µm

133
understanding of these noise sources. There are a few studies ([39] and [48]-[50]) that

focus on understanding and modeling of supply or substrate noise. However, their impact

on jitter distribution is not well understood, because supply or substrate noise are

deterministic rather than probabilistic and they vary from a system to another system.

Proper modeling of supply noise may further enhance jitter performance.

134
Appendices

A.1 Relationship Between Timing Jitter and Noise

Power Spectral Density
Using timing jitter definition given in Section 3.1, the jitter is equal to1:

2 1 2
σ ∆T = -----2- ⋅ E { [ φ ( t + ∆T ) – φ ( t ) ] }
ω0
‹A.1›
1 2 2
= -----2- ⋅ { E [ φ ( t ) ] + E [ φ ( t + ∆T ) ] – 2 ⋅ E [ φ ( t ) ⋅ φ ( t + ∆T ) ] }
ω0

Since E [ φ ( t ) ⋅ φ ( t + ∆T ) ] is equal to autocorrelation of φ(t), Rφ(∆T), the timing jitter in

Equation A.1 can be written as:

2 2
σ ∆T = -----2- [ R φ ( 0 ) – R φ ( ∆T ) ] ‹A.2›
ω0

Replacing autocorrelation with power spectral density (given by Khinchin theorem [82]),
∞
j2πft
Rφ ( t ) = ∫–∞ Sφ ( f )e df in Equation A.2, results in:

1. Equations A.1-A.4 have been extracted from [26]

135
 2 4 ∞ 2
σ ∆T = --------2- ∫ S φ ( f ) sin ( πf∆T ) df ‹A.3›
ω 0 –∞

Equation A.3 describes the relationship between the timing jitter and noise power spectral
density (psd), Sφ(f). As ∆T goes to infinity, timing jitter is calculated from Equation A.2:

2 2
σ ∆T = -----2- R φ ( 0 ) ‹A.4›
ω0

or,

2 2 ∞
σ ∆T → ∞ = --------2- ∫ S φ ( f ) df ‹A.5›
ω 0 –∞

A.2 Relationship Between Jitter and PLL Noise

Transfer Function (NTF)
Noise psd, Sφ(f), in Equation A.3 (or Equation A.5) is calculated by multiplying

the open-loop phase noise of each noise source, Sφni-open(f), with the square magnitude of

of PLL NTF from the correspondent phase noise to the PLL output phase1, Hni(j2πf):

2 4 ∞ 2 2
σ ∆T = -----2- ∫ S φni – open ( f ) Hn i ( j2πf ) sin ( πf∆T ) df ‹A.6›
ω0 –∞

1 ∞ 2
∞
2
To simplify the equation, Parseval’s relation is used, ------ ∫ Z ( ω ) dω = ∫– ∞ z ( t ) dt . To
2π –∞
do so, Z(ω) is expressed as:

∆T
Z ( ω ) = X ( ω ) ⋅ Y ( ω ) = H open ( jω ) ⋅ Hn i ( jω ) ⋅ jω ⋅ sin  ω ------- ⁄ ω ‹A.7›
 2




















X(ω) Y(ω)

1. Please see Equation 3.3

136
 2
where S φni – open ( f ) = H open ( jω ) . z(t) is equal to convolution of x(t) and y(t). Since
1 ∆T 1 ∆T
y ( t ) = --- δ  t + ------- – --- δ  t – ------- where δ(t) represents dirac’s delta function,
2  2 2  2
1 ∆T 1 ∆T
z ( t ) = --- x  t + ------- – --- x  t – ------- where x(t) is the inverse fourier of (Hopen(jω).Hni(jω)).
2  2 2  2

Therefore, timing jitter equation is simplified as:

4 ⋅ 2π ∞ 1  ∆T ∆T 2
2
- ∫ --- x t + ------- – x  t – ------- dt
σ ∆T = ------------- ‹A.8›
 2  2
ω 0 –∞ 4
2

A.3 Relationship Between Output Jitter and VCO

Noise
For the VCO noise, X(ω) is calculated from Equation 3.4 and Equation 3.5:

X ( ω ) = H open ( jω ) ⋅ Hn buf ( jω )

 N VCO 2 
s ‹A.9›
=  ----------------- ⋅ --------------------------------------------------------
-
 s 2
s + K Loop RCs + K Loop
s = jω

x(t) is calculated by taking the inverse fourier of Equation A.12:

– ζω n t
e
x ( t ) = ------------------ ⋅ cos ( ω d t + θ ) ⋅ u ( t ) ‹A.10›
2
1–ζ
2 2
where ω d = ω n ⋅ 1 – ζ and cos θ = 1–ζ .

By substituting x(t) in Equation A.8, timing jitter is calculated:

– ζω n ∆T
 1 e sin ( ω d ∆T + θ ) cos ( ω d ∆T )
- ⋅  -----------------------------------
 ------------- + --------------------- - – ---------------------------- ζ<1
4π N VCO  2ζω n 2 ( 1 – ζ 2 )  
2
2
ωn ζω n
σ ∆T = -----------------------
2
⋅ ‹A.11›
ω0  1 – a∆T  2αβ
2
α - – b∆T  2αβ β 
2
 ------------- – e ------------ + ----- –e ------------ + ----- ζ≥1
 2ζω n a + b a  a + b b 

2 –a b
where a, b = ζω n −
+ ω n ⋅ ζ – 1 , α = ------------ and β = ------------ .
b–a b–a

137
A.4 Relationship Between Output Jitter and Clock
Buffer Noise
For the clock buffer noise, X(ω) is calculated from Equation 3.4 and Equation 3.5:

X ( ω ) = H open ( jω ) ⋅ Hn buf ( jω )

 N buf 2 
s ‹A.12›
=  -------------------------- ⋅ --------------------------------------------------------
-
 s ⁄ ω buf + 1 s + K Loop RCs + K Loop
2
s = jω

x(t) is calculated by taking the inverse fourier of Equation A.12:

2
  –ωn 2ζω n  –ζω t –ω t 
x ( t ) =   --------- ⋅ sin ( ω d t ) – ------------------ ⋅ cos ( ω d t + θ ) ⋅ e n + ω buf ⋅ e buf  ⋅ u ( t ) ‹A.13›
  ωd 1–ζ
2  

2 2
where ω Buf = 2πf Buf , ζ<1, ω d = ω n ⋅ 1 – ζ and cos θ = 1–ζ .

By substituting x(t) in Equation A.8, timing jitter is calculated:

 1 – 12ζ
2
– ω Buf ∆T 
 ω Buf + ω n -------------------- – e ( ω Buf – 4ζω n ) 
 2ζ 
  ζ<1
 – ζω ∆T  ω sin ( ω ∆T + 3θ – π ) ω cos ( ω ∆T ) 2ω sin ( ω ∆T + 2θ )
– e
n
 –
n d
-------------------------------------------------------
- +
n d
----------------------------------
- –
n d
-------------------------------------------------- 
 2 2 
  2(1 – ζ ) 2 ( 1 – ζ )ζ 1–ζ
2  
N Buf  
2
σ ∆T = ----------2- ⋅  
2 
‹A.14›
ω0   2
γ- υ
2 4ω Buf υ 4ω Buf γ – a∆T  2υω
2υγ- υ - 
4υγ- -------------------- Buf
ω
  Buf a + ---- + -----
- + ----------- + + -------------------- – e  -------------------- + ----------- + -----
b a + b a + ω Buf b + ω Buf  a + ω Buf a + b a  
 
  ζ≥1
 – b∆T  2γω Buf 2υγ γ
2  – ω Buf ∆T  2υωBuf 2γω Buf  
  –e  -------------------- + ------------ + ----- – e ω + -------------------- + -------------------- 
  b + ω Buf a + b b   Buf a + ω Buf b + ω Buf 
  
2 2
2ζω n a – ω n – 2 ζω n b + ω n
where υ = -------------------------- and γ = -------------------------------- .
b–a b–a

A.5 Relationship Between Output Jitter and Input

Clock Noise
For the input clock noise, X(ω) is calculated from Equation 3.4 and Equation 3.5:

138
 X ( ω ) = H open ( jω ) ⋅ Hn in ( jω )
2
 2ζω n s + ω n  ‹A.15›
=  H open ( s ) ⋅ --------------------------------------------------------
2
-
 s + K Loop RCs + K Loop
s = jω

In the next two sections, we calculate the timing jitter for two different input noise psd.

N Clk – in
A.5.1 1/f2 noise, i.e. S φn in ( f ) = ------------------
2
-
f
2
Using S φnin ( f ) = H open ( jω ) , X(ω) is calculated:

2
 2π ⋅ N Clk – in 2ζω n s + ω n 
X ( ω ) =  ---------------------------------- ⋅ --------------------------------------------------------
- ‹A.16›
 s 2
s + K Loop RCs + K Loop
s = jω

x(t) is calculated by taking the inverse fourier of Equation A.16:

– ζω n t
 e 
x ( t ) =  1 – ------------------ ⋅ cos ( ω d t + θ ) ⋅ u ( t ) ‹A.17›
 1–ζ
2 

By substituting x(t) in Equation A.8, timing jitter is calculated:

– ζω n ∆T
 1  sin ( ω d ∆T + θ ) cos ( ω d ∆T ) 2 sin ( ω d ∆T )
- + e------------------- ⋅  -----------------------------------
 1 + ------------------------ - – --------------------------------
- – ------------------------------ ζ<1
 2ζω n ⋅ ∆T ∆T  2 ( 1 – ζ )ω n 2
2 ( 1 – ζ )ζω n
2 ωd 
2 2
σ ∆T = κ ⋅ ∆T ⋅  ‹A.18›





– a∆T 2 – b∆T 2
1 e 2α 2αβ α e 2β 2αβ β
 1 + ------------------------- + -------------  ------- – ------------ – ------ + -------------  ------ – ------------ – ----- ζ≥1
 2ζω n ⋅ ∆T ∆T a a + b a ∆T b a + b b

where ωd, θ, a, b, α and β are the same as Equation A.11.

A.5.2 White noise, i.e. S φnin ( f ) = N Clk – in

Similarly, X(ω) is calculated:

2
 2ζω n s + ω n 
X ( ω ) =  N Clk – in ⋅ --------------------------------------------------------
2
- ‹A.19›
 s + K Loop RCs + K Loop
s = jω

139
x(t) is calculated by taking the inverse fourier of Equation A.16:

– ζω t 2 – ζω t
 e n ωn ⋅ e n 
x( t) = N Clk – in ⋅  2ζω n ⋅ -----------------
- ⋅ cos ( ω d t + θ ) + ------------------------- ⋅ sin ( ω d t )  ⋅ u ( t ) ‹A.20›
 2 ωd 
1–ζ

where ωd and θ are the same as Equation 3.10. The long-term timing jitter is calculated:

2 2 ⋅ N Clk – in ∞ 2
σ ∆T → ∞ = --------------------------
ω0
2 ∫ –∞
x ( t ) dt ‹A.21›

Simplifying Equation A.21 results in:

2
2 4ζ + 1
σ ∆T → ∞ = --------2- ⋅ N Clk – in ⋅  ω n ⋅ ------------------
2
‹A.22›
ω0 4ζ

A.6 Jitter Estimation by Applying Effective 2nd-Order

Model to any PLL
Although a complete 3rd-order model of a PLL is needed to understand the jitter

contribution of different loop parameters, our analytical results and measurements have

found that tracking jitter due to VCO noise for a particular design can be easily estimated

by simply using the second-order equations. As shown in the jitter analysis of Section 3.4

and Section 3.5, tracking jitter (σtr) is the integral of the noise shaped by the frequency

response. The critical parameters that determine the jitter are the f-3dB and the peaking in

the NTF.

In a higher-order loop, the parameters such as ζ and fn cannot be directly applied to

the equations for the second-order loop because the resulting frequency response can

differ greatly. To still use the equation, for a given frequency response, we find an

140
effective fn and effective ζ that result in the same bandwidth and peaking. Figure 3.8-(a)

and (b) shows the corresponding f-3dB for each value of fn, and the corresponding peaking

for each value of ζ. This method is verified by measuring the tracking jitter for the

different loop bandwidths and frequency-response peaking. Jitter is calculated for the
κ 1 - . Table A.1 compares the measured and
same parameters using σ tr = ------- ⋅ ------------
2 2ζω n
calculated jitter. By changing only one variable, we express the change in the jitter as a

ratio. The ratio can be directly predicted from Figure 3.8-(a) or (b). The small error

between measurement and predicted result is primarily due to the oscilloscope’s inherent

noise.

Table A.1: Comparison of estimated tracking jitter (by second-order PLL

analysis) with measured tracking jitter at fref = 700MHz

ratio
f-3dB Peak fn estimated rms measured
ζ (Figure 3.8(a),
(MHz) (%) (MHz) jitter (ps) rms jitter (ps)
(b))

39 1.61 22.4 0.42 1 σ = κ/(2.√ζωn) = 3.51 3.67

39 2.73 0.2 1.8/1.38 = 1.3 σ = 1.3 . 3.51 = 4.56 5

45 1.19 19.5 0.9 1 σ = κ/(2.√ζωn) = 2.57 2.83

45 1.31 0.65 1.1/1.02 = 1.07 σ = 1.07 . 2.57 = 2.75 2.94

26 1.66 15.3 0.4 1 σ = κ/(2.√ζωn) = 4.35 4.49

42 1.66 0.4 √26/42 = 0.79 σ = 0.79 . 4.35 = 3.42 3.45

141
A.7 Is Jitter due to Input Clock Noise Convex?
The long-term jitter due to input clock noise is given by Equation 4.4 (or

equivalently Equation A.22). To verify the convexity of jitter, the second derivite of jitter

as a function of Kloop and ωn should be positive.

2 –2
 d σ rms N in ( ωz )
 ---------------- = –-----1- ⋅ ----------- - ⋅ --------------------------------------------------------------- <0
 dK loop
2 4 ω0 3---
 –1 1 2
 ( ω z ) ⋅ K loop + ---------------
–1
 ( ωz )

 2 ‹A.23›
 1 1
K loop – --------------- ---------------
 2 ( ωz )
–2 –3
 d σ rms – 1 N in ( ωz )
- = ------ ⋅ ------------ ⋅ --------------------------------------------------------------- + ---------------------------------------------------------------
 --------------------
 d(ω z) –1 2 4 ω0 3--- 1---
2 2
 –1 1 –1 1
 ( ω z ) ⋅ K loop + ---------------
–1
( ω z ) ⋅ K loop + ---------------
–1
 ( ωz ) ( ωz )

As seen from Equation A.23, the second derivitive of jitter as a function of Kloop is always

negative. Also, the second derivitive as a function of ωn is conditionally positive.

Therefore, the jitter is not a convex function.

A.8 Minima and Maxima of Total Jitter in a Second-

Order PLL
The total jitter due to VCO and input clock noise is the sum of jitter variances:

2 2 2
σ tot = σ in + σ VCO

or,

2 N in –1 1 N VCO 1
σ tot = --------2- ⋅ ( ω z ) ⋅ K loop + ----------
–1
+ ------------- ⋅ ---------------------------
2 –1
- ‹A.24›
ω0 ωz f0 ω z ⋅ K loop

142
We take the first derivative of total jitter as a function of Kloop:

–1
N in ⋅ ω z N VCO
----------------------- – ----------------------------------------- -
2 –1 2 2
dσ tot 1 ω 0 ω z ⋅ K loop ⋅ f 0
---------------- = --- ⋅ -----------------------------------------------------------------------
- ‹A.25›
dK loop 2 σ tot

σtot has only one minimum that occurs at:

2π N VCO
K loop = ----------
–1
⋅ ------------- ‹A.26›
σ tot = min ωz N in

Similarly, we take the first derivative of total jitter as a function of (ωz)-1:

N in 1 - N VCO
- ⋅ K loop – ---------------
-------- ⋅ – ----------------------------------------------
2 –1 2 –1 2 2
dσ tot ω0 ( ωz ) ( ω z ) ⋅ K loop ⋅ f 0
------------------- = ------------------------------------------------------------------------------------------------------------- ‹A.27›
d ( ωz )
–1 σ tot

σtot has only one minimum that occurs at:

N VCO ( 2π ) 2
1 + ------------- ⋅ -------------
–1 N in K loop
ωz = -----------------------------------------
- ‹A.28›
K loop

Neither parameter yields any local minima.

143
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