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    Logic Circuits Lab or Gate

    Uploaded by

    Jeremy Sese

    Copyright:

    © All Rights Reserved
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    Logic Circuits Lab or Gate

    Uploaded by

    Jeremy Sese
    9 views3 pages

    Copyright

    © © All Rights Reserved

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    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    9 views3 pages

    Logic Circuits Lab or Gate

    Uploaded by

    Jeremy Sese

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    Activity No.

    1
    OR GATE
    OBJECTIVES

    1. To examine the characteristics and operations of a TTL 2-Input OR gate

    2. To create an expanded input OR gate using 2-Input TTL OR gates

    Basic Concept
    The OR gate is an electronic circuit that gives a high output (1) if one or more of its
    inputs are high.
    U3A

    7432N
    Symbol, IC part-number and IC label

    7432 IC PIN DIAGRAM

    Materials
    Design and simulation software: tinkercad.com

    Name: Date Started:


    Rating:
    Program: Date Submitted:
    EST 2AL – LOGIC CIRCUITS AND SWITCHING THEORY
    Activity No.1
    OR GATE
    Procedures
    Part 1 2-Input OR gate

    1. Using tinkercad.com Circuit design and simulation platform, setup the test circuit according to
    the schematic diagram shown. Figures 1 and 2 show the input conditions 0,0 and 0,1
    respectively.

    NOTE: 5 V must be applied between the Vcc and GND pins of the IC.

    2. Fill-out the truth table for each of the four gates in the IC. SHOW the wiring design for each
    setup.

    OR Gate A INPUT A INPUT B OUTPUT Y


    (Pin 1) (Pin 2) (Pin 3)
    0 0
    0 1
    1 0
    1 1

    3. Sample Wiring Design

    Input A = 0

    Input B = 1

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    Rating:
    Program: Date Submitted:
    EST 2AL – LOGIC CIRCUITS AND SWITCHING THEORY
    Activity No.1
    OR GATE
    Part 2 Expanded OR gate

    1. Build an expanded OR gate circuit using two gates in the IC package which will allow three
    inputs. Two inputs are applied to the first OR gate and the third input goes to the second
    OR gate along with the output of the first gate.
    2. Determine the output for each set of input conditions.

    INPUT A INPUT B OUTPUT Y1 INPUT C OUTPUT Y2


    (Pin 1) (Pin 2) (Pin 3) (Pin 5) (Pin 6)
    0 0 0
    0 0 1
    0 1 0
    0 1 1
    1 0 0
    1 0 1
    1 1 0
    1 1 1

    3. Repeat the test for the other pair of OR gates. Draw your wiring design for each setup.

    Name: Date Started:


    Rating:
    Program: Date Submitted:
    EST 2AL – LOGIC CIRCUITS AND SWITCHING THEORY

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