VLSI 1-5 Lectures

Class 1
VLSI:
it’s the art, science and technology that allows the construction and interconnection of larger numbers
(millions) of transistors on a single chip (IC: integrated circuit).
Introduction:
There’s no doubt that daily life is significantly affected by electronics engineering technology.
This is true and there’s no doubt that revolutionary changes have taken place in a short time and it’s
also certain that even more dramatic advance will be made in the next decade.
So that the electronics as we know today is characterized by:
1- Reliability.
2- Low Power Dissipation.
3- Extremely Low Volume.
4- Low Weight and Size.
5- Low Cost.
The microelectronics are used for designing and fabrication integrated circuit with a small dimension
electronic device.
There are Four generations of ICs:
1- SSI (Small Scale Integration).
2- MSI (Medium Scale Integration).
3- LSI (Large Scale Integration).
4- VLSI (Very Large Scale Integration).
Class 2
The Electronic and particular the integrated circuit has made possible the design of powerful and
flexible processor that provide highly intelligent and adaptable device for the user.
The Fabrication of ICs is very important up until 1950, The electronic active technology was using
vacuum tube and then got replaced by transistors.
The Invention of the transistor by (William Shockley Walter & John Barden) of telephone laboratories
was followed by developing the IC.
Moore’s First Law Transistors integrated on a single chip “Commercial Products”.
Some Important Definitions:
1- Wafer: A thin slice of semiconductor material on which semiconductor device are made of, also
called slice or substrate.
2- Die: It’s an individual circuit or subsystem that’s one of several identical chips that are
produced after dicing up the wafer.
3- Chip: It is a small piece of semiconductor material upon which miniaturized electronic circuits
can be built.
MOS and its relation with VLSI:
- PMOS (Positive Metal Oxide Semiconductor).

- NMOS (Negative Metal Oxide Semiconductor).
- CMOS (Complementary Metal Oxide Semiconductor).
- BIMOS.
The NMOS have characterized by many reasons in design:

1- For NMOS technology, The Design methodology and the design rules are easily learned
thus providing a simple but excellent introduction to instructed design for VLSI.
2- For NMOS technology all design represents of the background of this structure design.
3- For GaAs (Gallium Arsenide) technology, some arrangement in relation to logic design are
similar to those employed in NMOS technology. Therefor understanding the basics of
NMOS design with assist in the layout of GaAs Circuits.
Basic MOS Transistors:

Having now established some background the basic MOS process and device the NMOS
enhancement and NMOS depletion mode transistors.
Class 3
The NMOS Enhancement Mode:

1- The NMOS devices are formed by p-type substrate of moderate doping level.
2- The source and drain regions are formed by diffusing n-type impurities through suitable mask into
these areas.
3- This becomes to give the desired n-impurity concentration and give arise to depletion region which
regions which extend mainly in the more lightly doped p-region.
4- The source and drain are isolated from one another.
5- VB = VS = Vgs = Zero, The Basic enhancement mode devices in which the channel is not established and
the device is non-conducting.
The NMOS Depletion Mode:

6- The connection to the source and drain are made by a deposited metal layer.
7- If the gate is connected to a suitable positive charge “Voltage” with respect to the source then the
electric field established between the gate and the substrate give rise to a charge and conduction
current flow from source to drain.
For The PMOS Transistor Mode:

1- The PMOS transistor substrate is formed by n-type material.
2- The source and drain diffusion are consequently p-type.
3- The conditions shown are those of negative voltage of a suitable magnitude between gate and source
will give rise to the formation of channel (p-type) between source and drain.
4- The holes are carried.
5- PMOS transistor is inherently slower than NMOS because the hole mobility (MP) is less by a factor of
2.5 than electron mobility (Mn).
Enhancement Mode Transistor Action:
Transistor Circuit Symbols:

Class 4
NMOS Fabrication:
1- Processing is carried out on a thin wager cut from a single crystal of silicon of high purity into which the
required p-impurities are introduced as the crystal is grown, Such wafers are typically ( 75mm to
150mm ) in diameter and ( 0.4mm ) thick and are doped with say boron to an impurity concentration of
[ 1015 /CM3 TO 1016 /CM3 ] giving resistivity in the approximate range [ 25 ohm/CM TO 2 ohm/CM ].
2- A layer of silicon dioxide (SiO2) typically 1 μm thick is grown all over the surface of the wafer to protect
the surface act as a barrier to dopants during the processing and provide a generally isolating substrate
onto which other layers maybe deposited and patterned.
3- The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve
an even distribution of required thickness.
4- The Photo resist layer is then exposed to ultraviolet (uv) light through a mask which defines those
regions into which diffusion is to take place together with transistor channels.
5- These areas are subsequently readily etched away together with the underlying silicon dioxide so that
the wafer surface is exposed int the window defined by mask.
6- The remaining photoresist is removed and a thin layer of (SiO2) [0.1 μm typically] is grown over the
entire chip surface and then the polysilicon is deposited on top of this to form the gate structure. The
polysilicon layer consists of heavily doped polysilicon deposited by chemical vapor deposition (CVD).
In the fabrication of fine patterns devices precise of thickness, impurity concentration and resistivity are
necessary.
7- Further photoresist coating and masking allows the polysilicon to be patterned and then the thin oxide
is removed to expose areas into which n-type impurities are to be diffused to form the source and drain
diffusion, it’s achieved by heating the wafer to a high temperature and passing a gas containing the
desired n-type impurity for example (Phosphors) over the surface.
Class 5
8- Thick oxide (SiO2) is grown over all again and is then masked with photoresist and etched to expose
selected areas of the polysilicon gate and the drain and source areas where connection (contact cuts) is
to be made.
9- The whole chip then has metal (aluminum) deposited over its surface to thickness typically of 1 μm,
This metal layer is then masked and etched to form the required interconnection pattern
COMS Fabrication:
There are number of approaches to CMOS fabrication including the p-well, n-well, twin-tub.
For the P-Well Process:
A- In primitive terms, the structure consists of an n-type substrate in which p-devices may be formed by
suitable masking and diffusion.
B- In order to accommodate n-type devices a deep p-well is diffused into the n-type substrate.

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Class 1

Moore’s First Law Transistors integrated on a single chip “Commercial Products”.

Some Important Definitions:

- PMOS (Positive Metal Oxide Semiconductor).

The NMOS have characterized by many reasons in design:

Basic MOS Transistors:

The NMOS Enhancement Mode:

The NMOS Depletion Mode:

For The PMOS Transistor Mode:

Transistor Circuit Symbols:

For the P-Well Process:

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