10-Bit, 4× Oversampled SDTV

Video Decoder with Deinterlacer

Data Sheet ADV7280
FEATURES APPLICATIONS
Worldwide NTSC/PAL/SECAM color demodulation support Smartphone/multimedia handsets
One 10-bit analog-to-digital converter (ADC), 4× oversampling Automotive infotainment
per channel for CVBS, Y/C, and YPrPb modes DVRs for video security
Analog video input channels with on-chip antialiasing filter Media players
ADV7280: up to 4 input channels
GENERAL DESCRIPTION
ADV7280-M: up to 8 input channels
Video input support for CVBS (composite), Y/C (S-Video), The ADV7280/ADV7280-M are versatile one-chip, multiformat
and YPrPb (component) video decoders. The ADV7280/ADV7280-M automatically detect
NTSC/PAL/SECAM autodetection standard analog baseband video signals compatible with worldwide
Up to 1.47 V common-mode input range solution NTSC, PAL, and SECAM standards in the form of composite,
Excellent common-mode noise rejection capabilities S-Video, and component video.
5-line adaptive 2D comb filter and CTI video enhancement The ADV7280 converts the analog video signals into a YCrCb
Adaptive Digital Line Length Tracking (ADLLT), signal 4:2:2 video data stream that is compatible with the 8-bit ITU-R
processing, and enhanced FIFO management provide BT.656 interface standard. The ADV7280-M converts the analog
mini-time base correction (TBC) functionality video signals into an 8-bit YCrCb 4:2:2 video data stream that is
Integrated automatic gain control (AGC) with adaptive output over a mobile industry processor interface (MIPI®) CSI-2
peak white mode interface.
Fast switching capability
The analog video inputs of the ADV7280/ADV7280-M accept
Integrated interlaced-to-progressive (I2P) video output
converter
single-ended signals. The ADV7280 provides four analog inputs;
Adaptive contrast enhancement (ACE)
the ADV7280-M provides eight analog inputs. The ADV7280
Down dither (8-bit to 6-bit) and ADV7280-M support I2P conversion.
Rovi (Macrovision) copy protection detection The ADV7280/ADV7280-M are programmed via a 2-wire,
MIPI CSI-2 output interface (ADV7280-M) serial bidirectional port (I2C compatible) and are fabricated in a
8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, or field 1.8 V CMOS process. The LFCSP package option makes these
synchronization (ADV7280) decoders ideal for space-constrained portable applications.
Full featured vertical blanking interval (VBI) data slicer
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADV7280 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Power-Down Sequence .............................................................. 15
Applications ....................................................................................... 1 Universal Power Supply (ADV7280 Only) ............................. 15
General Description ......................................................................... 1 Input Network ................................................................................. 16
Revision History ............................................................................... 2 Input Configuration ....................................................................... 17
Functional Block Diagrams ............................................................. 3 Adaptive Contrast Enhancement (ACE) ..................................... 18
Specifications..................................................................................... 4 I2P Function.................................................................................... 19
Electrical Specifications ............................................................... 4 MIPI CSI-2 Output (ADV7280-M Only) ................................... 20
Video Specifications ..................................................................... 5 ITU-R BT.656 Tx Configuration (ADV7280 Only) .................. 21
Analog Specifications ................................................................... 6 I2C Port Description ....................................................................... 22
MIPI Video Output Specifications (ADV7280-M Only) ........ 6 Register Maps .............................................................................. 23
Pixel Port Timing Specifications (ADV7280 Only) ................. 8 PCB Layout Recommendations.................................................... 25
Clock and I C Timing Specifications ......................................... 9
2
Analog Interface Inputs ............................................................. 25
Absolute Maximum Ratings.......................................................... 10 Power Supply Decoupling ......................................................... 25
Thermal Resistance .................................................................... 10 VREFN and VREFP Pins .......................................................... 25
Reflow Solder .............................................................................. 10 Digital Outputs (INTRQ, GPO0 to GPO2) ............................ 25
ESD Caution ................................................................................ 10 Exposed Metal Pad ..................................................................... 25
Pin Configurations and Function Descriptions ......................... 11 Digital Inputs .............................................................................. 25
Theory of Operation ...................................................................... 13 MIPI Outputs for the ADV7280-M (D0P, D0N,
Analog Front End (AFE) ........................................................... 13 CLKP, CLKN) ............................................................................. 25

Standard Definition Processor (SDP) ...................................... 14 Typical Circuit Connections ......................................................... 26

Power Supply Sequencing .............................................................. 15 Outline Dimensions ....................................................................... 28

Optimal Power-Up Sequence.................................................... 15 Ordering Guide .......................................................................... 28

Simplified Power-Up Sequence ................................................ 15 Automotive Products ................................................................. 28

REVISION HISTORY
2/14—Rev. 0 to Rev. A 8/13—Revision 0: Initial Version
Change to Single-Ended CVBS Input Parameter, Analog Supply
Current, Table 1 ................................................................................ 4

Rev. A | Page 2 of 28
Data Sheet ADV7280

FUNCTIONAL BLOCK DIAGRAMS

ADV7280 CLOCK PROCESSING BLOCK

XTALP LLC
PLL ADLLT PROCESSING
XTALN

10-BIT ADC DIGITAL VS/FIELD/SFL

PROCESSING

FIFO
AA HS
AIN1 FILTER BLOCK
AIN2 ACE

MUX BLOCK
2D COMB 8-BIT
AA

OUTPUT BLOCK
FILTER + DOWN PIXEL DATA
ANALOG VIDEO VBI SLICER DITHER P7 TO P0
INPUTS SHA ADC
AA –
FILTER COLOR
DEMOD
AIN3
AA
AIN4 FILTER I2P

REFERENCE I2C/CONTROL INTRQ

11634-001
SCLK SDATA ALSB RESET PWRDWN

Figure 1. ADV7280 Functional Block Diagram

ADV7280-M CLOCK PROCESSING BLOCK CLKP

XTALP MIPI CLKN
PLL ADLLT PROCESSING Tx D0P
XTALN
D0N

10-BIT ADC DIGITAL

PROCESSING

FIFO
AIN1 AA
FILTER BLOCK
AIN2 ACE
MUX BLOCK

2D COMB
AIN3 AA
OUTPUT BLOCK
AIN4 FILTER + DOWN
ANALOG VIDEO SHA ADC VBI SLICER DITHER
INPUTS AIN5 AA –
AIN6 FILTER COLOR
DEMOD GPO0
AIN7
AA GPO1
AIN8 FILTER I2P GPO2

REFERENCE I2C/CONTROL INTRQ

SCLK SDATA ALSB RESET PWRDWN 11634-002

Figure 2. ADV7280-M Functional Block Diagram

Rev. A | Page 3 of 28
ADV7280 Data Sheet

SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
MVDD applies to the ADV7280-M only.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
STATIC PERFORMANCE
ADC Resolution N 10 Bits
Integral Nonlinearity INL CVBS mode 2 LSB
Differential Nonlinearity DNL CVBS mode ±0.6 LSB
DIGITAL INPUTS
Input High Voltage VIH DVDDIO = 3.3 V 2 V
DVDDIO = 1.8 V, ADV7280 only 1.2 V
Input Low Voltage VIL DVDDIO = 3.3 V 0.8 V
DVDDIO = 1.8 V, ADV7280 only 0.4 V
Input Leakage Current IIN RESET pin −10 +10 µA
SDATA, SCLK pins −10 +15 µA
PWRDWN, ALSB pins −10 +50 µA
Input Capacitance CIN 10 pF
CRYSTAL INPUT
Input High Voltage VIH XTALN pin 1.2 V
Input Low Voltage VIL XTALN pin 0.4 V
DIGITAL OUTPUTS
Output High Voltage VOH DVDDIO = 3.3 V, ISOURCE = 0.4 mA 2.4 V
DVDDIO = 1.8 V, ISOURCE = 0.4 mA, 1.4 V
ADV7280 only
Output Low Voltage VOL DVDDIO = 3.3 V, ISINK = 3.2 mA 0.4 V
DVDDIO = 1.8 V, ISINK = 1.6 mA, 0.2 V
ADV7280 only
High Impedance Leakage Current ILEAK 10 µA
Output Capacitance COUT 20 pF
POWER REQUIREMENTS 1, 2, 3
Digital I/O Power Supply DVDDIO ADV7280-M 2.97 3.3 3.63 V
ADV7280 1.62 3.3 3.63 V
PLL Power Supply PVDD 1.71 1.8 1.89 V
Analog Power Supply AVDD 1.71 1.8 1.89 V
Digital Power Supply DVDD 1.71 1.8 1.89 V
MIPI Tx Power Supply MVDD ADV7280-M only 1.71 1.8 1.89 V
Digital I/O Supply Current IDVDDIO ADV7280-M 1.5 mA
ADV7280 5 mA
PLL Supply Current IPVDD 12 mA
MIPI Tx Supply Current IMVDD ADV7280-M only 14 mA
Analog Supply Current IAVDD
Single-Ended CVBS Input 47 mA
Y/C Input 60 mA
YPrPb Input 75 mA
Digital Supply Current IDVDD
Single-Ended CVBS Input 70 mA
Y/C Input 70 mA
YPrPb Input 70 mA

Rev. A | Page 4 of 28
Data Sheet ADV7280
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER-DOWN CURRENTS1
Digital I/O Supply Power-Down Current IDVDDIO_PD DVDDIO = 3.3 V, ADV7280-M 73 µA
DVDDIO = 3.3 V, ADV7280 84 µA
PLL Supply Power-Down Current IPVDD_PD 46 µA
Analog Supply Power-Down Current IAVDD_PD 0.2 µA
Digital Supply Power-Down Current IDVDD_PD 420 µA
MIPI Tx Supply Power-Down Current IMVDD_PD ADV7280-M only 4.5 µA
Total Power Dissipation 1 mW
in Power-Down Mode
1
Guaranteed by characterization.
2
Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern.
3
All specifications apply when the I2P core is activated, unless otherwise stated.

VIDEO SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. MVDD applies to the ADV7280-M only.

Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
NONLINEAR SPECIFICATIONS 1
Differential Phase DP CVBS input, modulated 5-step 0.9 Degrees
Differential Gain DG CVBS input, modulated 5-step 0.5 %
Luma Nonlinearity LNL CVBS input, 5-step 2.0 %
NOISE SPECIFICATIONS
Signal-to-Noise Ratio, Unweighted SNR Luma ramp 57.1 dB
Luma flat field 58 dB
Analog Front-End Crosstalk 60 dB
Common-Mode Rejection Ratio 2 CMRR 73 dB
LOCK TIME SPECIFICATIONS
Horizontal Lock Range −5 +5 %
Vertical Lock Range 40 70 Hz
fSC Subcarrier Lock Range ±1.3 kHz
Color Lock-In Time 60 Lines
Synchronization Depth Range 20 200 %
Color Burst Range 5 200 %
Vertical Lock Time 2 Fields
Autodetection Switch Speed 3 100 Lines
Fast Switch Speed 4 100 ms
LUMA SPECIFICATIONS CVBS, 1 V input
Luma Brightness Accuracy 1 %
Luma Contrast Accuracy 1 %
1
These specifications apply for all CVBS input types (NTSC, PAL, and SECAM).
2
The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Network section). The CMRR measurement
was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
3
Autodetection switch speed is the time required for the ADV7280/ADV7280-M to detect which video format is present at its input, for example, PAL I or NTSC M.
4
Fast switch speed is the time required for the ADV7280/ADV7280-M to switch from one analog input to another, for example, switching from AIN1 to AIN2.

Rev. A | Page 5 of 28
ADV7280 Data Sheet
ANALOG SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. MVDD applies to the ADV7280-M only.

Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 µF
Input Impedance Clamps switched off 10 MΩ
Large Clamp Source Current 0.4 mA
Large Clamp Sink Current 0.4 mA
Fine Clamp Source Current 10 µA
Fine Clamp Sink Current 10 µA

MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7280-M ONLY)

AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
The CSI-2 clock lane of the ADV7280-M remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this
reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed
measurements were performed with the ADV7280-M operating in progressive mode and with a nominal 432 Mbps output data rate.
Specifications guaranteed by characterization.

Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
UNIT INTERVAL UI
Interlaced Output 4.63 ns
Progressive Output 2.31 ns
DATA LANE LP TX DC SPECIFICATIONS 1
Thevenin Output High Level VOH 1.1 1.2 1.3 V
Thevenin Output Low Level VOL −50 0 +50 mV
DATA LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85% 25 ns
Fall Time, 85% to 15% 25 ns
Rise Time, 30% to 85% 35 ns
Data Lane LP Slew Rate vs. CLOAD
Maximum Slew Rate over Entire Rising edge 150 mV/ns
Vertical Edge Region
Falling edge 150 mV/ns
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV Falling edge 30 mV/ns
400 mV ≤ VOUT ≤ 700 mV Rising edge 30 mV/ns
700 mV ≤ VOUT ≤ 930 mV Rising edge >0 mV/ns
Pulse Width of LP Exclusive-OR Clock First clock pulse after stop state 40 ns
or last pulse before stop state
All other clock pulses 20 ns
Period of LP Exclusive-OR Clock 90 ns
CLOCK LANE LP TX DC SPECIFICATIONS1
Thevenin Output High Level VOH 1.1 1.2 1.3 V
Thevenin Output Low Level VOL −50 0 +50 mV
CLOCK LANE LP TX AC SPECIFICATIONS1
Rise Time, 15% to 85% 25 ns
Fall Time, 85% to 15% 25 ns

Rev. A | Page 6 of 28
Data Sheet ADV7280
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Clock Lane LP Slew Rate
Maximum Slew Rate over Entire Rising edge 150 mV/ns
Vertical Edge Region
Falling edge 150 mV/ns
Minimum Slew Rate
400 mV ≤ VOUT ≤ 930 mV Falling edge 30 mV/ns
400 mV ≤ VOUT ≤ 700 mV Rising edge 30 mV/ns
700 mV ≤ VOUT ≤ 930 mV Rising edge >0 mV/ns
DATA LANE HS TX SIGNALING See Figure 3
REQUIREMENTS
Low Power to High Speed Transition t9 Time that the D0P pin is at VOL 50 ns
Stage and the D0N pin is at VOH
t10 Time that the D0P and D0N pins 40 + (4 × UI) 85 + (6 × UI) ns
are at VOL
t11 t10 plus the HS-zero period 145 + (10 × UI) ns
High Speed Differential Voltage Swing |V1| 140 200 270 mV p-p
Differential Voltage Mismatch 10 mV
Single-Ended Output High Voltages 360 mV
Static Common-Mode Voltage Level 150 200 250 mV
Static Common-Mode Voltage 5 mV
Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz 25 mV
Above 450 MHz 15 mV
Rise Time, 20% to 80% 0.15 0.3 × UI ns
Fall Time, 80% to 20% 0.15 0.3 × UI ns
High Speed to Low Power Transition t12 Time that the ADV7280-M drives 60 + (4 × UI) ns
Stage the flipped last data bit after
sending the last payload data bit
of an HS transmission burst
t13 Post-end-of-transmission rise 35 ns
time (30% to 85%)
t14 Time from start of t12 to start of 105 + (12 × UI) ns
low power state following an HS
transmission burst
t15 Time that a low power state is 100 ns
transmitted after an HS trans-
mission burst
CLOCK LANE HS TX SIGNALING See Figure 3
REQUIREMENTS
Low Power to High Speed Transition t9 Time that the CLKP pin is at VOL 50 ns
Stage 2 and the CLKN pin is at VOH
Time that the CLKP and CLKN 38 95 ns
pins are at VOL
Clock HS-zero period 300 500 ns
High Speed Differential Voltage Swing |V2| 140 200 270 mV p-p
Differential Voltage Mismatch 10 mV
Single-Ended Output High Voltages 360 mV
Static Common-Mode Voltage Level 150 200 250 mV
Static Common-Mode Voltage 5 mV
Mismatch
Dynamic Common Level Variations
50 MHz to 450 MHz 25 mV
Above 450 MHz 15 mV
Rise Time, 20% to 80% 0.15 0.3 × UI ns
Fall Time, 80% to 20% 0.15 0.3 × UI ns
Rev. A | Page 7 of 28
ADV7280 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
HS TX CLOCK TO DATA LANE TIMING
REQUIREMENTS
Data to Clock Skew 0.35 × UI 0.65 × UI ns
1
These measurements were performed with CLOAD = 50 pF.
2
The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7280-M during startup.

CLKP/CLKN |V2|

D0P/D0N t9 t10
t11
VOH

|V1|

VOL t13
TRANSMIT FIRST
DATA BIT

t14
t12 t15
LOW POWER HS-ZERO START OF HIGH SPEED DATA
TO TRANSMISSION TRANSMISSION
HIGH SPEED SEQUENCE HS-TRAIL HIGH SPEED

11634-005
TRANSITION TO
LOW POWER
TRANSITION

Figure 3. ADV7280-M Output Timing Diagram (Conforms with MIPI CSI-2 Specification)

PIXEL PORT TIMING SPECIFICATIONS (ADV7280 ONLY)

AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.

Table 5.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CLOCK OUTPUTS
LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transitional Time t11 Negative clock edge to start of valid data 3.8 ns
(tSETUP = t10 − t11)
t12 End of valid data to negative clock edge 6.9 ns
(tHOLD = t9 − t12)

t9 t10

OUTPUT LLC

t11
t12
11634-004

OUTPUTS P0 TO P7, HS,

VS/FIELD/SFL

Figure 4. ADV7280 Pixel Port and Control Output Timing Diagram

Rev. A | Page 8 of 28
Data Sheet ADV7280
CLOCK AND I2C TIMING SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. MVDD applies to the ADV7280-M only.

Table 6.
Parameter Symbol Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency 28.63636 MHz
Frequency Stability ±50 ppm
I2C PORT
SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t1 0.6 µs
SCLK Minimum Pulse Width Low t2 1.3 µs
Hold Time (Start Condition) t3 0.6 µs
Setup Time (Start Condition) t4 0.6 µs
SDATA Setup Time t5 100 ns
SCLK and SDATA Rise Times t6 300 ns
SCLK and SDATA Fall Times t7 300 ns
Setup Time (Stop Condition) t8 0.6 µs
RESET INPUT
RESET Pulse Width 5 ms

t3 t5 t3

SDATA

t6 t1
SCLK

11634-003
t2 t7 t4 t8
2
Figure 5. I C Timing Diagram

Rev. A | Page 9 of 28
ADV7280 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 7. THERMAL RESISTANCE
Parameter Rating The thermal resistance values in Table 8 are specified for the
AVDD to DGND 2.2 V device soldered onto a 4-layer printed circuit board (PCB) with
DVDD to DGND 2.2 V a common ground plane and with the exposed pad of the device
PVDD to DGND 2.2 V connected to DGND. The values in Table 8 are maximum values.
MVDD to DGND1 2.2 V
DVDDIO to DGND 4V Table 8. Thermal Resistance for the 32-Lead LFCSP
PVDD to DVDD −0.9 V to +0.9 V Thermal Characteristic Symbol Value Unit
MVDD to DVDD1 −0.9 V to +0.9 V Junction-to-Ambient Thermal θJA 32.5 °C/W
AVDD to DVDD −0.9 V to +0.9 V Resistance (Still Air)
Digital Inputs Voltage DGND − 0.3 V to DVDDIO + 0.3 V Junction-to-Case Thermal θJC 2.3 °C/W
Resistance
Digital Outputs Voltage DGND − 0.3 V to DVDDIO + 0.3 V
Analog Inputs to Ground Ground − 0.3 V to AVDD + 0.3 V REFLOW SOLDER
Maximum Junction Temperature 140°C
The ADV7280/ADV7280-M are Pb-free, environmentally
(TJ max)
friendly products. They are manufactured using the most up-to-
Storage Temperature Range −65°C to +150°C
date materials and processes. The coating on the leads of each
Infrared Reflow Soldering 260°C
(20 sec) device is 100% pure Sn electroplate. The devices are suitable for
Pb-free applications and can withstand surface-mount soldering
1
MVDD applies to the ADV7280-M only.
at up to 255°C (±5°C).
Stresses above those listed under Absolute Maximum Ratings
In addition, the ADV7280/ADV7280-M are backward-
may cause permanent damage to the device. This is a stress
compatible with conventional SnPb soldering processes. This
rating only; functional operation of the device at these or any
means that the electroplated Sn coating can be soldered with
other conditions above those indicated in the operational
Sn/Pb solder pastes at conventional reflow temperatures of
section of this specification is not implied. Exposure to absolute
220°C to 235°C.
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
These devices are high performance integrated circuits with
an ESD rating of <2 kV, and they are ESD sensitive. Proper
precautions must be taken for handling and assembly.

Rev. A | Page 10 of 28
Data Sheet ADV7280

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VS/FIELD/SFL
PWRDWN

SDATA

RESET
SCLK

ALSB
LLC

HS
32
31
30
29
28
27
26
25
DGND 1 24 INTRQ
DVDDIO 2 23 AIN4
DVDD 3 22 AIN3
DGND 4 ADV7280 21 AVDD
TOP VIEW
P7 5 (Not to Scale) 20 VREFN
P6 6 19 VREFP
P5 7 18 AIN2
P4 8 17 AIN1

P3 9
P2 10
P1 11
P0 12
DVDD 13
XTALP 14
XTALN 15
PVDD 16

11634-006
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.

Figure 6. Pin Configuration, ADV7280

Table 9. Pin Function Descriptions, ADV7280

Pin No. Mnemonic Type Description
1, 4 DGND Ground Ground for Digital Supply.
2 DVDDIO Power Digital I/O Power Supply (1.8 V or 3.3 V).
3, 13 DVDD Power Digital Power Supply (1.8 V).
5 to 12 P7 to P0 Output Video Pixel Output Ports.
14 XTALP Output Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280. The crystal used
with the ADV7280 must be a fundamental crystal.
15 XTALN Input Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280 must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used
to clock the ADV7280, the output of the oscillator is fed into the XTALN pin.
16 PVDD Power PLL Power Supply (1.8 V).
17, 18, AIN1 to AIN4 Input Analog Video Input Channels.
22, 23
19 VREFP Output Internal Voltage Reference Output.
20 VREFN Output Internal Voltage Reference Output.
21 AVDD Power Analog Power Supply (1.8 V).
24 INTRQ Output Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
25 RESET Input System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7280 circuitry.
26 ALSB Input This pin selects the I2C write address for the ADV7280. When ALSB is set to Logic 0, the write
address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
27 SDATA Input/output I2C Port Serial Data Input/Output.
28 SCLK Input I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
29 VS/FIELD/SFL Output Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier
Frequency Lock. When configured for the SFL function, this pin provides a serial output
stream that can be used to lock the subcarrier frequency when the ADV7280 decoder is
connected to any Analog Devices, Inc., digital video encoder.
30 HS Output Horizontal Synchronization Output Signal.
31 PWRDWN Input Power-Down Pin. A logic low on this pin places the ADV7280 in power-down mode.
32 LLC Output Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but
it increases or decreases according to the video line length.
EPAD (EP) Exposed Pad. The exposed pad must be connected to DGND.

Rev. A | Page 11 of 28
ADV7280 Data Sheet

PWRDWN

SDATA

RESET
SCLK

ALSB

AIN8
AIN7
AIN6
32
31
30
29
28
27
26
25
DGND 1 24 AIN5
DVDDIO 2 23 AIN4
DVDD 3 22 AIN3
DGND 4 ADV7280-M 21 AVDD
TOP VIEW
INTRQ 5 (Not to Scale) 20 VREFN
GPO2 6 19 VREFP
GPO1 7 18 AIN2
GPO0 8 17 AIN1

9
10
11
12
13
14
15
16
XTALP
XTALN
CLKP
CLKN
D0P
D0N

MVDD

PVDD

11634-007
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.

Figure 7. Pin Configuration, ADV7280-M

Table 10. Pin Function Descriptions, ADV7280-M

Pin No. Mnemonic Type Description
1, 4 DGND Ground Ground for Digital Supply.
2 DVDDIO Power Digital I/O Power Supply (3.3 V).
3 DVDD Power Digital Power Supply (1.8 V).
5 INTRQ Output Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
6 to 8 GPO2 to Output General-Purpose Outputs. These pins can be configured via I2C to allow control of external
GPO0 devices.
9 D0P Output Positive MIPI Differential Data Output.
10 D0N Output Negative MIPI Differential Data Output.
11 CLKP Output Positive MIPI Differential Clock Output.
12 CLKN Output Negative MIPI Differential Clock Output.
13 MVDD Power MIPI Digital Power Supply (1.8 V).
14 XTALP Output Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280-M. The crystal used
with the ADV7280-M must be a fundamental crystal.
15 XTALN Input Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280-M must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to
clock the ADV7280-M, the output of the oscillator is fed into the XTALN pin.
16 PVDD Power PLL Power Supply (1.8 V).
17, 18, 22, AIN1 to AIN8 Input Analog Video Input Channels.
23, 24, 25,
26, 27
19 VREFP Output Internal Voltage Reference Output.
20 VREFN Output Internal Voltage Reference Output.
21 AVDD Power Analog Power Supply (1.8 V).
28 RESET Input System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7280-M circuitry.
29 ALSB Input This pin selects the I2C write address for the ADV7280-M. When ALSB is set to Logic 0, the
write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
30 SDATA Input/output I2C Port Serial Data Input/Output.
31 SCLK Input I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.
32 PWRDWN Input Power-Down Pin. A logic low on this pin places the ADV7280-M in power-down mode.
EPAD (EP) Exposed Pad. The exposed pad must be connected to DGND.

Rev. A | Page 12 of 28
Data Sheet ADV7280

THEORY OF OPERATION
The ADV7280/ADV7280-M are versatile one-chip, multiformat ANALOG FRONT END (AFE)
video decoders. The ADV7280/ADV7280-M automatically detect The analog front end (AFE) of the ADV7280/ADV7280-M
standard analog baseband video signals compatible with world- comprises a single high speed, 10-bit ADC that digitizes the
wide NTSC, PAL, and SECAM standards in the form of composite, analog video signal before applying it to the standard definition
S-Video, and component video. processor (SDP).
The ADV7280 converts the analog video signals into an 8-bit The AFE also includes an input mux that enables multiple video
YCrCb 4:2:2 component video data stream that is compatible signals to be applied to the ADV7280/ADV7280-M. The input
with the ITU-R BT.656 interface standard. mux allows up to four composite video signals to be applied to
The ADV7280-M converts the analog video signals into an 8-bit the ADV7280 and up to eight composite video signals to be applied
YCrCb 4:2:2 video data stream that is output over a MIPI CSI-2 to the ADV7280-M.
interface. The MIPI CSI-2 output interface connects to a wide Current clamps are positioned in front of the ADC to ensure
range of video processors and FPGAs. that the video signal remains within the range of the converter.
The ADV7280/ADV7280-M accept composite video signals, A resistor divider network is required before each analog input
as well as S-Video and YPbPr video signals, supporting a wide channel to ensure that the input signal is kept within the range of
range of consumer and automotive video sources. The accurate the ADC (see the Input Network section). Fine clamping of the
10-bit analog-to-digital conversion provides professional quality video signal is performed downstream by digital fine clamping
video performance for consumer applications with true 8-bit within the ADV7280/ADV7280-M.
data resolution.
Table 11 lists the three ADC clock rates that are determined by
The advanced interlaced-to-progressive (I2P) function allows the the video input format to be processed. These clock rates ensure
ADV7280/ADV7280-M to convert an interlaced video input into 4× oversampling per channel for CVBS, Y/C, and YPrPb modes.
a progressive video output. This function is performed without the
need for external memory. The ADV7280/ADV7280-M use edge Table 11. ADC Clock Rates
adaptive technology to minimize video defects on low angle lines. Oversampling
Input Format ADC Clock Rate (MHz)1 Rate per Channel
The automatic gain control (AGC) and clamp restore circuitry
allows an input video signal peak-to-peak range of 0 V to 1.0 V CVBS 57.27 4×
at the analog video input pins of the ADV7280/ADV7280-M. Y/C (S-Video) 114 4×
Alternatively, the AGC and clamp restore circuitry can be bypassed YPrPb 172 4×
for manual settings. 1
Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.

The ADV7280/ADV7280-M support a number of other func-

tions, including 8-bit to 6-bit down dither mode and adaptive
contrast enhancement (ACE).
The ADV7280/ADV7280-M are programmed via a 2-wire,
serial bidirectional port (I2C compatible) and are fabricated in
a 1.8 V CMOS process. The monolithic CMOS construction
of the ADV7280/ADV7280-M ensures greater functionality with
lower power dissipation. The LFCSP package option makes these
decoders ideal for space-constrained portable applications.

Rev. A | Page 13 of 28
ADV7280 Data Sheet
STANDARD DEFINITION PROCESSOR (SDP) Adaptive contrast enhancement (ACE) offers improved visual
The ADV7280/ADV7280-M are capable of decoding a large detail using an algorithm that automatically varies contrast levels
selection of baseband video signals in composite, S-Video, and to enhance picture detail. ACE increases the contrast in dark areas
component formats. The video standards supported by the of an image without saturating the bright areas of the image. This
video processor include feature is particularly useful in automotive applications, where
it can be important to discern objects in shaded areas.
• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
Down dithering converts the output of the ADV7280/ADV7280-M
PAL Nc, PAL 60
from an 8-bit to a 6-bit output, enabling ease of design for standard
• NTSC J, NTSC M, NTSC 4.43
LCD panels.
• SECAM B, SECAM D, SECAM G, SECAM K, SECAM L
The I2P block converts the interlaced video input into a progressive
Using the standard definition processor (SDP), the ADV7280/ video output without the need for external memory.
ADV7280-M can automatically detect the video standard and
The SDP can process a variety of VBI data services, such as closed
process it accordingly.
captioning (CCAP), wide screen signaling (WSS), and copy gen-
The ADV7280/ADV7280-M have a five-line adaptive 2D eration management system (CGMS). VBI data is transmitted
comb filter that provides superior chrominance and luminance as ancillary data packets.
separation when decoding a composite video signal. This highly
The ADV7280/ADV7280-M are fully Rovi® (Macrovision®)
adaptive filter automatically adjusts its processing mode according
compliant; detection circuitry enables Type I, Type II, and Type III
to the video standard and signal quality without user intervention.
protection levels to be identified and reported to the user. The
Video user controls such as brightness, contrast, saturation, and
decoders are also fully robust to all Macrovision signal inputs.
hue are also available with the ADV7280/ADV7280-M.
The ADV7280/ADV7280-M implement the patented Adaptive
Digital Line Length Tracking (ADLLT™) algorithm to track vary-
ing video line lengths from sources such as VCRs. ADLLT enables
the ADV7280/ADV7280-M to track and decode poor quality
video sources such as VCRs and noisy sources from tuner outputs
and camcorders. The ADV7280/ADV7280-M contain a chroma
transient improvement (CTI) processor that sharpens the edge
rate of chroma transitions, resulting in sharper vertical transitions.

Rev. A | Page 14 of 28
Data Sheet ADV7280

POWER SUPPLY SEQUENCING

OPTIMAL POWER-UP SEQUENCE While the supplies are being established, care must be taken to
The optimal power-up sequence for the ADV7280/ADV7280-M ensure that a lower rated supply does not go above a higher rated
is to first power up the 3.3 V DVDDIO supply, followed by the 1.8 V supply level. During power-up, all supplies must adhere to the
supplies: DVDD, PVDD, AVDD, and MVDD (for the ADV7280-M). specifications listed in the Absolute Maximum Ratings section.

When powering up the ADV7280/ADV7280-M, follow these steps. POWER-DOWN SEQUENCE

During power-up, all supplies must adhere to the specifications The ADV7280/ADV7280-M supplies can be deasserted
listed in the Absolute Maximum Ratings section. simultaneously as long as DVDDIO does not go below a lower
1. Assert the PWRDWN and RESET pins (pull the pins low). rated supply.
2. Power up the DVDDIO supply. UNIVERSAL POWER SUPPLY (ADV7280 ONLY)
3. After DVDDIO is fully asserted, power up the 1.8 V supplies. The ADV7280-M model requires a DVDDIO supply at a nominal
4. After the 1.8 V supplies are fully asserted, pull the value of 3.3 V. The ADV7280 model, however, can operate with
PWRDWN pin high. a DVDDIO supply at a nominal value of 1.8 V. Therefore, it is possible
5. Wait 5 ms and then pull the RESET pin high. to power up all the supplies for the ADV7280 (DVDD, PVDD, AVDD,
6. After all power supplies and the PWRDWN and RESET and DVDDIO) to 1.8 V.
pins are powered up and stable, wait an additional 5 ms When DVDDIO is at a nominal value of 1.8 V, power up the
before initiating I2C communication with the ADV7280/ ADV7280 as follows:
ADV7280-M.
1. Follow the power-up sequence described in the Optimal
SIMPLIFIED POWER-UP SEQUENCE Power-Up Sequence section, but power up the DVDDIO supply
Alternatively, the ADV7280/ADV7280-M can be powered up to 1.8 V instead of 3.3 V. Also, power up the PWRDWN and
by asserting all supplies and the PWRDWN and RESET pins RESET pins to 1.8 V instead of 3.3 V.
simultaneously. After this operation, perform a software reset, 2. Set the drive strengths of the digital outputs of the ADV7280
then wait 10 ms before initiating I2C communication with the to their maximum setting.
ADV7280/ADV7280-M. 3. Connect any pull-up resistors connected to pins on the
ADV7280 (such as the SCLK and SDATA pins) to 1.8 V
instead of 3.3 V.

3.3V 3.3V SUPPLY PWRDWN PIN RESET PIN

VOLTAGE

1.8V 1.8V SUPPLIES

PWRDWN PIN RESET PIN

POWER-UP POWER-UP
3.3V SUPPLY 1.8V SUPPLIES TIME
11634-008

5ms 5ms
POWER-UP POWER-UP RESET WAIT
OPERATION

Figure 8. Optimal Power-Up Sequence

Rev. A | Page 15 of 28
ADV7280 Data Sheet

INPUT NETWORK
An input network (external resistor and capacitor circuit) The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
is required on the AINx input pins of the decoder. Figure 9 required for the analog video input. These resistors also create a
shows the input network to use on each AINx input pin of resistor divider with a gain of 0.68. The resistor divider attenuates
the ADV7280/ADV7280-M when any of the following video the amplitude of the input analog video and scales the input to
input formats is used: the ADC range of the ADV7280/ADV7280-M. This allows an
input range to the ADV7280/ADV7280-M of up to 1.47 V p-to-p.
• Single-ended CVBS
Note that amplifiers within the ADC restore the amplitude of the
• YC (S-Video)
input signal so that signal-to-noise ratio (SNR) performance is
• YPrPb
maintained.
INPUT
CONNECTOR
24Ω 100nF The 100 nF ac coupling capacitor removes the dc bias of the analog
VIDEO INPUT EXT
FROM SOURCE ESD AIN1 OF ADV7280 input video before it is fed into the AINx pin of the ADV7280/
51Ω
ADV7280-M. The clamping circuitry within the ADV7280/

11634-009
ADV7280-M restores the dc bias of the input signal to the optimal
Figure 9. Input Network level before it is fed into the ADC of the ADV7280/ADV7280-M.

Rev. A | Page 16 of 28
Data Sheet ADV7280

INPUT CONFIGURATION
The input format of the ADV7280/ADV7280-M is specified The INSEL[4:0] bits specify predefined analog input routing
using the INSEL[4:0] bits (see Table 12). These bits also configure schemes, eliminating the need for manual mux programming
the SDP core to process CVBS, Y/C (S-Video), or component and allowing the user to route the various video signal types
(YPrPb) format. The INSEL[4:0] bits are located in the user sub to the decoder. For example, if the CVBS input is selected, the
map of the register space at Address 0x00[4:0]. For more infor- remaining channels are powered down.
mation about the registers, see the Register Maps section.

Table 12. Input Format Specified by the INSEL[4:0] Bits

Analog Inputs
INSEL[4:0] Bit Value Video Format ADV7280 ADV7280-M
00000 CVBS CVBS input on AIN1 CVBS input on AIN1
00001 CVBS CVBS input on AIN2 CVBS input on AIN2
00010 CVBS CVBS input on AIN3 CVBS input on AIN3
00011 CVBS CVBS input on AIN4 CVBS input on AIN4
00100 CVBS Reserved CVBS input on AIN5
00101 CVBS Reserved CVBS input on AIN6
00110 CVBS Reserved CVBS input on AIN7
00111 CVBS Reserved CVBS input on AIN8
01000 Y/C (S-Video) Y input on AIN1; Y input on AIN1;
C input on AIN2 C input on AIN2
01001 Y/C (S-Video) Y input on AIN3; Y input on AIN3;
C input on AIN4 C input on AIN4
01010 Y/C (S-Video) Reserved Y input on AIN5;
C input on AIN6
01011 Y/C (S-Video) Reserved Y input on AIN7;
C input on AIN8
01100 YPrPb Y input on AIN1; Y input on AIN1;
Pb input on AIN2; Pb input on AIN2;
Pr input on AIN3 Pr input on AIN3
01101 YPrPb Reserved Y input on AIN4;
Pb input on AIN5;
Pr input on AIN6
01110 to 11111 Reserved Reserved Reserved

Rev. A | Page 17 of 28
ADV7280 Data Sheet

ADAPTIVE CONTRAST ENHANCEMENT (ACE)

The ADV7280/ADV7280-M can increase the contrast of an The ACE function is disabled by default. To enable the ACE
image depending on the content of the picture, allowing bright function, execute the register writes shown in Table 13. To
areas to be made brighter and dark areas to be made darker. The disable the ACE function, execute the register writes shown
optional ACE feature enables the contrast within dark areas to in Table 14.
be increased without significantly affecting the bright areas. The
ACE feature is particularly useful in automotive applications,
where it can be important to discern objects in shaded areas.

Table 13. Register Writes to Enable the ACE Function

Register Map Register Address Register Write Description
User Sub Map (0x40 or 0x42) 0x0E 0x40 Enter User Sub Map 2
User Sub Map 2 (0x40 or 0x42) 0x80 0x80 Enable ACE
User Sub Map 2 (0x40 or 0x42) 0x0E 0x00 Reenter user sub map

Table 14. Register Writes to Disable the ACE Function

Register Map Register Address Register Write Description
User Sub Map (0x40 or 0x42) 0x0E 0x40 Enter User Sub Map 2
User Sub Map 2 (0x40 or 0x42) 0x80 0x00 Disable ACE
User Sub Map 2 (0x40 or 0x42) 0x0E 0x00 Reenter user sub map

Rev. A | Page 18 of 28
Data Sheet ADV7280

I2P FUNCTION
The advanced interlaced-to-progressive (I2P) function allows The I2P function is disabled by default. To enable the I2P
the ADV7280/ADV7280-M to convert an interlaced video input function, use the recommended scripts from Analog Devices.
into a progressive video output. This function is performed with-
out the need for external memory. The ADV7280/ADV7280-M
use edge adaptive technology to minimize video defects on low
angle lines.

Rev. A | Page 19 of 28
ADV7280 Data Sheet

MIPI CSI-2 OUTPUT (ADV7280-M ONLY)

The decoder in the ADV7280-M outputs an ITU-R BT.656 data The clock lanes are used to clock the output video. After the
stream. The ITU-R BT.656 data stream is connected into a CSI-2 ADV7280-M is programmed, the clock lanes exit low power
Tx module. Data from the CSI-2 Tx module is fed into a D-PHY mode and remain in high speed mode until the part is reset
physical layer and output serially from the device. or powered down.
The output of the ADV7280-M consists of a single data channel The ADV7280-M outputs video data in an 8-bit YCrCb 4:2:2
on the D0P and D0N lanes and a clock channel on the CLKP and format. When the I2P core is disabled, the video data is output in
CLKN lanes. an interlaced format at a nominal data rate of 216 Mbps. When
Video data is output over the data lanes in high speed mode. The the I2P core is enabled, the video data is output in a progressive
data lanes enter low power mode during the horizontal and vertical format at a nominal data rate of 432 Mbps (see the I2P Function
blanking periods. section for more information).

D0P
CSI Tx DATA (1 BIT)
OUTPUT (8 BITS)
D0N
ANALOG ITU-R BT.656 (1 BIT)
VIDEO DATA DATA LANE LP
INPUT VIDEO STREAM CSI-2 SIGNALS (2 BITS) D-PHY
DECODER Tx Tx CLKP
(1 BIT)
CLOCK LANE LP
SIGNALS (2 BITS)
CLKN
(1 BIT)

11634-011
Figure 10. MIPI CSI-2 Output Stage of the ADV7280-M

Rev. A | Page 20 of 28
Data Sheet ADV7280

ITU-R BT.656 Tx CONFIGURATION (ADV7280 ONLY)

The ADV7280 receives analog video and outputs digital video The LLC output is used to clock the output data on the P0 to P7
according to the ITU-R BT.656 specification. The ADV7280 pins at a nominal frequency of 27 MHz.
outputs the ITU-R BT.656 video data stream over the P0 to P7 The two synchronization pins (HS and VS/FIELD/SFL) output a
data pins and has a line-locked clock (LLC) pin and two synchro- variety of synchronization signals such as horizontal sync, vertical
nization pins (HS and VS/FIELD/SFL). sync, field sync, and color subcarrier frequency lock (SFL) sync.
Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format. The majority of these synchronization signals are already embed-
Synchronization signals are automatically embedded in the video ded in the video data. Therefore, the use of the synchronization
data signal in accordance with the ITU-R BT.656 specification. pins is optional.

P0
VIDEO ADV7280 P1
DECODER
P2
P3
P4
ITU-R BT.656
DATA P5
ANALOG STREAM P6
VIDEO ANALOG STANDARD
INPUT FRONT DEFINITION P7
END PROCESSOR
LLC

HS
(OPTIONAL)
VS/FIELD/SFL

11634-018
(OPTIONAL)

Figure 11. ITU-R BT.656 Output Stage of the ADV7280

Rev. A | Page 21 of 28
ADV7280 Data Sheet

I2C PORT DESCRIPTION

The ADV7280/ADV7280-M support a 2-wire, I2C-compatible 4. All other devices withdraw from the bus and maintain an
serial interface. Two inputs, serial data (SDATA) and serial clock idle condition. In the idle condition, the device monitors
(SCLK), carry information between the ADV7280/ADV7280-M the SDATA and SCLK lines for the start condition and the
and the system I2C master controller. The I2C port of the correct transmitted address.
ADV7280/ADV7280-M allows the user to set up and configure The R/W bit determines the direction of the data. Logic 0 on the
the decoder and to read back captured VBI data.
LSB of the first byte means that the master writes information
The ADV7280/ADV7280-M have a number of possible I2C slave to the peripheral. Logic 1 on the LSB of the first byte means that
addresses and subaddresses (see the Register Maps section). The the master reads information from the peripheral.
main map of the ADV7280/ADV7280-M has four possible slave
The ADV7280/ADV7280-M act as standard I2C slave devices on
addresses for read and write operations, depending on the logic
the bus. The data on the SDATA pin is eight bits long, supporting
level of the ALSB pin (see Table 15).
the 7-bit address plus the R/W bit. The device has subaddresses to
Table 15. Main Map I2C Address for the ADV7280/ADV7280-M enable access to the internal registers; therefore, it interprets the
ALSB Pin R/W Bit Slave Address first byte as the device address and the second byte as the starting
0 0 0x40 (write) subaddress. The subaddresses auto-increment, allowing data to be
0 1 0x41 (read) written to or read from the starting subaddress. A data transfer is
1 0 0x42 (write) always terminated by a stop condition. The user can also access
1 1 0x43 (read)
any unique subaddress register individually without updating
all the registers.
The ALSB pin controls Bit 1 of the slave address. By changing
Stop and start conditions can be detected at any stage during the
the logic level of the ALSB pin, it is possible to control two
data transfer. If these conditions are asserted out of sequence with
ADV7280/ADV7280-M devices in an application without using
normal read and write operations, they cause an immediate jump
the same I2C slave address. The LSB (Bit 0) specifies either a read
to the idle condition. During a given SCLK high period, the user
or write operation: Logic 1 corresponds to a read operation, and
should issue only one start condition, one stop condition, or a single
Logic 0 corresponds to a write operation.
stop condition followed by a single start condition. If an invalid
To control the device on the bus, a specific protocol is followed. subaddress is issued by the user, the ADV7280/ADV7280-M do
1. The master initiates a data transfer by establishing a start not issue an acknowledge and return to the idle condition.
condition, which is defined as a high to low transition on If the highest subaddress is exceeded in auto-increment mode,
SDATA while SCLK remains high, and indicates that an one of the following actions is taken:
address/data stream follows.
2. All peripherals respond to the start condition and shift • In read mode, the register contents of the highest sub-
the next eight bits (the 7-bit address plus the R/W bit). address continue to be output until the master device issues
a no acknowledge, which indicates the end of a read. A no
The bits are transferred from MSB to LSB.
acknowledge condition occurs when the SDATA line is not
3. The peripheral that recognizes the transmitted address
pulled low on the ninth pulse.
responds by pulling the data line low during the ninth
clock pulse; this is known as an acknowledge (ACK) bit. • In write mode, the data for the invalid byte is not loaded
into a subaddress register. A no acknowledge is issued by
the ADV7280/ADV7280-M, and the part returns to the
idle condition.

SDATA

SCLK
11634-012

S 1–7 8 9 1–7 8 9 1–7 8 9 P

START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP

Figure 12. Bus Data Transfer

WRITE
SEQUENCE S SLAVE ADDR A(S) SUBADDRESS A(S) DATA A(S) DATA A(S) P

LSB = 0 LSB = 1

READ
SEQUENCE S SLAVE ADDR A(S) SUBADDRESS A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P
11634-013

S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) = NO ACKNOWLEDGE BY SLAVE

P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER A(M) = NO ACKNOWLEDGE BY MASTER

Figure 13. Read and Write Sequence

Rev. A | Page 22 of 28
Data Sheet ADV7280
REGISTER MAPS Interrupt/VDP Sub Map
The ADV7280/ADV7280-M contain three register maps: the The interrupt/VDP sub map contains registers that can be used to
main register map, the VPP register map, and the CSI register program internal interrupts, control the INTRQ pin, and decode
map (ADV7280-M only). vertical blanking interval (VBI) data.
Main Map The interrupt/VDP sub map has the same I2C slave address
The I2C slave address of the main map of the ADV7280/ as the main map. To access the interrupt/VDP sub map, set the
ADV7280-M is set by the ALSB pin (see Table 15). The main SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 01.
map allows the user to program the I2C slave addresses of the User Sub Map 2
VPP and CSI maps. The main map contains three sub maps: the
User Sub Map 2 contains registers that control the ACE, down
user sub map, the interrupt/VDP sub map, and User Sub Map 2.
dither, and fast lock functions. It also contains controls that set the
These three sub maps are accessed by writing to the SUB_USR_EN
acceptable input luma and chroma limits before the ADV7280/
bits (Address 0x0E[6:5]) within the main map (see Figure 14 and
ADV7280-M enter free run and color kill modes.
Table 16).
User Sub Map 2 has the same I2C slave address as the main map.
User Sub Map
To access User Sub Map 2, set the SUB_USR_EN bits in the main
The user sub map contains registers that program the analog map (Address 0x0E[6:5]) to 10.
front end and digital core of the ADV7280/ADV7280-M. The
user sub map has the same I2C slave address as the main map.
To access the user sub map, set the SUB_USR_EN bits in the
main map (Address 0x0E[6:5]) to 00.

MAIN MAP VPP MAP CSI MAP

DEVICE ADDRESS DEVICE ADDRESS DEVICE ADDRESS
ALSB PIN LOW ALSB PIN HIGH WRITE: 0x84 (RECOMMENDED WRITE: 0x88 (RECOMMENDED
WRITE: 0x40 WRITE: 0x42 READ: 0x85 SETTINGS) READ: 0x89 SETTINGS)
READ: 0x41 READ: 0x43 VPP MAP DEVICE ADDRESS IS CSI MAP ADDRESS IS
PROGRAMMABLE AND SET BY PROGRAMMABLE AND SET BY
REGISTER 0xFD IN THE USER REGISTER 0xFE IN THE USER
0x0E[6:5] = 00 0x0E[6:5] = 01 0x0E[6:5] = 10 SUB MAP SUB MAP

USER INTERRUPT/VDP USER SUB

11634-014
SUB MAP SUB MAP MAP 2

Figure 14. Register Map and Sub Map Access

Table 16. I2C Register Map and Sub Map Addresses

SUB_USR_EN Bits
ALSB Pin R/W Bit Slave Address (Address 0x0E[6:5]) Register Map or Sub Map
0 0 (write) 0x40 00 User sub map
0 1 (read) 0x41 00 User sub map
0 0 (write) 0x40 01 Interrupt/VDP sub map
0 1 (read) 0x41 01 Interrupt/VDP sub map
0 0 (write) 0x40 10 User Sub Map 2
0 1 (read) 0x41 10 User Sub Map 2
1 0 (write) 0x42 00 User sub map
1 1 (read) 0x43 00 User sub map
1 0 (write) 0x42 01 Interrupt/VDP sub map
1 1 (read) 0x43 01 Interrupt/VDP sub map
1 0 (write) 0x42 10 User Sub Map 2
1 1 (read) 0x43 10 User Sub Map 2
X1 0 (write) 0x84 XX1 VPP map
X1 1 (read) 0x85 XX1 VPP map
X1 0 (write) 0x88 XX1 CSI map (ADV7280-M only)
X1 1 (read) 0x89 XX1 CSI map (ADV7280-M only)
1
X and XX mean don’t care.

Rev. A | Page 23 of 28
ADV7280 Data Sheet
VPP Map To reset the I2C slave address of the CSI map, write to the
CSI_TX_SLAVE_ADDRESS[7:1] bits in the main register map
The video postprocessor (VPP) map contains registers that
(Address 0xFE[7:1]). Set these bits to a value of 0x88 (I2C write
control the I2P core (interlaced-to-progressive converter).
address; I2C read address is 0x89).
The VPP map has a programmable I2C slave address, which is
SUB_USR_EN Bits, Address 0x0E[6:5]
programmed using Register 0xFD in the user sub map of the
main map. The default value for the VPP map address is 0x00; The ADV7280/ADV7280-M main map contains three sub maps:
however, the VPP map cannot be accessed until the I2C slave the user sub map, the interrupt/VDP sub map, and User Sub Map 2
address is reset. The recommended I2C slave address for the (see Figure 14). The user sub map is available by default. The other
VPP map is 0x84. two sub maps are accessed using the SUB_USR_EN bits. When
programming of the interrupt/VDP map or User Sub Map 2 is
To reset the I2C slave address of the VPP map, write to the
completed, it is necessary to write to the SUB_USR_EN bits to
VPP_SLAVE_ADDRESS[7:1] bits in the main register map
return to the user sub map.
(Address 0xFD[7:1]). Set these bits to a value of 0x84 (I2C
write address; I2C read address is 0x85).
CSI Map (ADV7280-M Only)
The CSI map contains registers that control the MIPI CSI-2
output stream from the ADV7280-M.
The CSI map has a programmable I2C slave address, which is
programmed using Register 0xFE in the user sub map of the
main map. The default value for the CSI map address is 0x00;
however, the CSI map cannot be accessed until the I2C slave
address is reset. The recommended I2C slave address for the
CSI map is 0x88.

Rev. A | Page 24 of 28
Data Sheet ADV7280

PCB LAYOUT RECOMMENDATIONS

The ADV7280/ADV7280-M are high precision, high speed, VREFN AND VREFP PINS
mixed-signal devices. To achieve maximum performance from Place the circuit associated with the VREFN and VREFP pins as
the parts, it is important to use a well-designed PCB. This section close as possible to the ADV7280/ADV7280-M and on the same
provides guidelines for designing a PCB for use with the side of the PCB as the part.
ADV7280/ADV7280-M.
DIGITAL OUTPUTS (INTRQ, GPO0 TO GPO2)
ANALOG INTERFACE INPUTS
Minimize the trace length that the digital outputs must drive.
When routing the analog interface inputs on the PCB, keep
Longer traces have higher capacitance, requiring more current
track lengths to a minimum. Use 75 Ω trace impedances when
and, in turn, causing more internal digital noise. Shorter traces
possible; trace impedances other than 75 Ω increase the chance
reduce the possibility of reflections.
of reflections.
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
POWER SUPPLY DECOUPLING reduce EMI, and reduce current spikes inside the ADV7280/
It is recommended that each power supply pin be decoupled ADV7280-M. If series resistors are used, place them as close as
with 100 nF and 10 nF capacitors. The basic principle is to place possible to the pins of the ADV7280/ADV7280-M. However, try
a decoupling capacitor within approximately 0.5 cm of each power not to add vias or extra length to the output trace in an attempt
pin. Avoid placing the decoupling capacitors on the opposite side to place the resistors closer.
of the PCB from the ADV7280/ADV7280-M because doing so
If possible, limit the capacitance that each digital output must
introduces inductive vias in the path.
drive to less than 15 pF. This recommendation can be easily
Place the decoupling capacitors between the power plane and accommodated by keeping traces short and by connecting the
the power pin. Current should flow from the power plane to the outputs to only one device. Loading the outputs with excessive
capacitor and then to the power pin. Do not apply the power capacitance increases the current transients inside the ADV7280/
connection between the capacitor and the power pin. The best ADV7280-M, creating more digital noise on the power supplies.
approach is to place a via near, or beneath, the decoupling capac-
EXPOSED METAL PAD
itor pads down to the power plane (see Figure 15).
The ADV7280/ADV7280-M have an exposed metal pad on the
SUPPLY VIA TO SUPPLY
bottom of the package. This pad must be soldered to ground. The
10nF 100nF
exposed pad is used for proper heat dissipation, noise suppression,
GROUND VIA TO GND
and mechanical strength.
11634-015

DIGITAL INPUTS
Figure 15. Recommended Power Supply Decoupling The digital inputs of the ADV7280/ADV7280-M are designed to
It is especially important to maintain low noise and good work with 1.8 V signals (3.3 V for DVDDIO) and are not tolerant of
stability for the PVDD pin. Careful attention must be paid to 5 V signals. Extra components are required if 5 V logic signals
regulation, filtering, and decoupling. It is highly desirable to must be applied to the decoder.
provide separate regulated supplies for each circuit group MIPI OUTPUTS FOR THE ADV7280-M (D0P, D0N,
(AVDD, DVDD, DVDDIO, PVDD, and, for the ADV7280-M, MVDD).
CLKP, CLKN)
Some graphic controllers use substantially different levels of It is recommended that the MIPI output traces be kept as short
power when active (during active picture time) and when idle as possible and on the same side of the PCB as the ADV7280-M
(during horizontal and vertical sync periods). This disparity can device. It is also recommended that a solid plane (preferably a
result in a measurable change in the voltage supplied to the analog ground plane) be placed on the layer adjacent to the MIPI traces
supply regulator, which can, in turn, produce changes in the regu- to provide a solid reference plane.
lated analog supply voltage. This problem can be mitigated by
regulating the analog supply, or at least the PVDD supply, from a MIPI transmission operates in both differential and single-
different, cleaner power source, for example, from a 12 V supply. ended modes. During high speed transmission, the pair of
outputs operates in differential mode; in low power mode, the
Using a single ground plane for the entire board is also recom- pair operates as two independent single-ended traces. There-
mended. Experience has shown that the noise performance is fore, it is recommended that each output pair be routed as two
the same or better with a single ground plane. Using multiple loosely coupled 50 Ω single-ended traces to reduce the risk of
ground planes can be detrimental because each separate ground crosstalk between the two traces in low power mode.
plane is smaller, and long ground loops can result.

Rev. A | Page 25 of 28
ADV7280 Data Sheet

TYPICAL CIRCUIT CONNECTIONS

Figure 16 provides an example of how to connect the ADV7280. For detailed schematics of the ADV7280 evaluation board, contact a
local Analog Devices field applications engineer or an Analog Devices distributor.

0.1µF
COMPONENT ANALOG VIDEO INPUT EXAMPLE

Y AIN1
24Ω
51Ω

DVDD _1.8V DVDDIO _3.3V AVDD _1.8V

0.1µF
Pb AIN2
0.1µF 10nF 0.1µF 0.1µF 0.1µF
24Ω
51Ω 10nF 10nF 10nF

0.1µF
Pr AIN3
PVDD _1.8V
24Ω
51Ω DVDDIO _3.3V
DVDD _1.8V
0.1µF
CVBS AVDD _1.8V 10nF
INPUT EXAMPLE 0.1µF
AIN4

13

21

16
24Ω

3
51Ω
P0 TO P7
DVDDIO

DVDD

DVDD

AVDD

PVDD
17
AIN1 AIN1
18
AIN2 AIN2 12 P0
P0
P1 11 P1
22 10 P2 YCrCb
AIN3 AIN3 P2 8-BIT
P3 9 P3
8 P4 ITU-R BT.656 DATA
23 P4
AIN4 AIN4 7 P5
P5
P6 6 P6
LOCATE VREFP AND VREFN CAPACITOR AS ADV7280 P7 5 P7
CLOSE AS POSSIBLE TO THE ADV7280 AND ON
THE SAME SIDE OF THE PCB AS THE ADV7280

19 VREFP

0.1µF
20 VREFN
LLC 32
LLC

LOCATE CLOSE TO, AND ON THE INTRQ 24

INTRQ
SAME SIDE OF THE PCB AS, THE ADV7280

14 XTALP
47pF VS/FIELD/SFL 29
VS/FIELD/SFL

28.63636MHz HS 30
HS

15 XTALN
47pF

DVDDIO
4kΩ
26 ALSB
ALSB TIED HIGH: I2C ADDRESS = 0x42
ALSB TIED LOW: I2C ADDRESS = 0x40

31 PWRDWN
PWRDWN
25 RESET
RESET
28 SCLK
SCLK
DGND

DGND

27 SDATA
SDATA
1

11634-016

Figure 16. Typical Connection Diagram, ADV7280

Rev. A | Page 26 of 28
Data Sheet ADV7280
Figure 17 provides an example of how to connect the ADV7280-M. For detailed schematics of the ADV7280-M evaluation board, contact
a local Analog Devices field applications engineer or an Analog Devices distributor.
0.1µF
Y A IN1
24Ω
51Ω

0.1µF
Pb A IN2
COMPONENT
VIDEO INPUT

24Ω
51Ω

0.1µF
Pr A IN3
24Ω
51Ω
D VDD _1.8V DVDDIO _3.3V AVDD _1.8V MVDD _1.8V

0.1µF 0.1µF 0.1µF 0.1µF

SINGLE- 0.1µF 10nF 10nF 10nF 10nF
ENDED A IN4
CVBS 24Ω
51Ω
INPUT

PVDD _1.8V
D VDDIO _3.3V
DVDD _1.8V M VDD_1.8V
SINGLE- 0.1µF
ENDED A IN5 0.1µF
AVDD _1.8V 10nF
CVBS 24Ω
INPUT

21

13

16
3
2
51Ω
DVDDIO

DVDD

AVDD

MVDD

PVDD
17
AIN1 AIN1
SINGLE- 0.1µF
A IN6 18
ENDED AIN2 AIN2
9
CVBS 24Ω D0P D0P
INPUT 10
D0N D0N
51Ω 22
AIN3 AIN3

0.1µF 23 CLKP 11 CLKP

AIN4 AIN4
A IN7
S-VIDEO INPUT

Y
24Ω AIN5
24
AIN5 CLKN 12 CLKN

51Ω
25 AIN6
AIN6

0.1µF
26
C A IN8 AIN7 AIN7
24Ω 27
AIN8 AIN8
6
51Ω GPO2 GPO2
LOCATE CLOSE TO, ADV7280-M 7
GPO1 GPO1
AND ON THE SAME SIDE OF 8
THE PCB AS, THE ADV7280-M GPO0 GPO0

14
XTALP
47pF

28.63636MHz 5
INTRQ INTRQ
15
XTALN
47pF

LOCATE VREFN AND VREFP CAPACITOR AS CLOSE

DVDDIO AS POSSIBLE TO THE ADV7280-M AND ON THE SAME
SIDE OF THE PCB AS THE ADV7280-M
4kΩ 29
ALSB
19
ALSB TIED HIGH: I2C ADDRESS = 0x42 VREFP
ALSB TIED LOW: I2C ADDRESS = 0x40 0.1µF
20
32 VREFN
PWRDWN PWRDWN
28 RESET
RESET
31
SCLK SCLK
DGND
DGND

30
SDATA SDATA
1
4

11634-017

Figure 17. Typical Connection Diagram, ADV7280-M

Rev. A | Page 27 of 28
ADV7280 Data Sheet

OUTLINE DIMENSIONS
5.10 0.30
5.00 SQ 0.25
PIN 1 4.90 0.18
INDICATOR PIN 1
25 32 INDICATOR
24 1

0.50
BSC *3.75
EXPOSED
PAD 3.60 SQ
3.55

17 8
16 9
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

08-16-2010-B
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.

Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1, 2 Temperature Range Package Description Package Option
ADV7280WBCPZ −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280WBCPZ-RL −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280BCPZ-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280KCPZ −10°C to +70°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280KCPZ-RL −10°C to +70°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280WBCPZ-M −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280WBCPZ-M-RL −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280BCPZ-M −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280BCPZ-M-RL −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280KCPZ-M −10°C to +70°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
ADV7280KCPZ-M-RL −10°C to +70°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-12
EVAL-ADV7280EBZ Evaluation Board for the ADV7280
EVAL-ADV7280MEBZ Evaluation Board for the ADV7280-M
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS
The ADV7280W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should
review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for these models.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D11634-0-2/14(A)

Rev. A | Page 28 of 28