Si4483ADY

Vishay Siliconix

P-Channel 30 V (D-S) MOSFET

FEATURES
PRODUCT SUMMARY
• Halogen-free According to IEC 61249-2-21
VDS (V) RDS(on) () ID (A)d Qg (Typ.)
Definition
0.0088 at VGS = - 10 V - 19.2
- 30 44.8 nC • TrenchFET® Power MOSFET
0.0153 at VGS = - 4.5 V - 14.6 • 100 % Rg Tested
• 100 % UIS Tested
• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS
SO-8 S
• Adaptor Switch
S 1 8 D
S 2 7 D G
S 3 6 D
G 4 5 D

Top View
D

Ordering Information: Si4483ADY-T1-GE3 (Lead (Pb)-free and Halogen-free) P-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 30
V
Gate-Source Voltage VGS ± 25
TC = 25 °C - 19.2
TC = 70 °C - 15.4
Continuous Drain Current (TJ = 150 °C) ID
TA = 25 °C - 13.5a, b
TA = 70 °C - 10.9a, b
A
Pulsed Drain Current IDM - 70
TC = 25 °C - 4.9
Continuous Source-Drain Diode Current IS
TA = 25 °C - 2.4a, b
Avalanche Current IAS 20
L = 0.1 mH
Single-Pulse Avalanche Energy EAS 20 mJ
TC = 25 °C 5.9
TC = 70 °C 3.8
Maximum Power Dissipation PD W
TA = 25 °C 2.9a, b
TA = 70 °C 1.9a, b
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambienta, c t 10 s RthJA 33 42
°C/W
Maximum Junction-to-Foot Steady State RthJF 16 21
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. t = 10 s.
c. Maximum under steady state conditions is 85 °C/W.
d. Based on TC = 25 °C.

Document Number: 68982 www.vishay.com

S10-2543-Rev. B, 08-Nov-10 1
Si4483ADY
Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 30 V
VDS Temperature Coefficient VDS/TJ - 30
ID = - 250 µA mV/°C
VGS(th) Temperature Coefficient VGS(th)/TJ 5.3
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1.2 - 2.1 - 2.6 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 25 V ± 100 nA
VDS = - 30 V, VGS = 0 V -1
Zero Gate Voltage Drain Current IDSS µA
VDS = - 30 V, VGS = 0 V, TJ = 55 °C -5
On-State Drain Currenta ID(on) VDS  - 10 V, VGS = - 10 V - 30 A
VGS = - 10 V, ID = - 10 A 0.0073 0.0088
Drain-Source On-State Resistancea RDS(on) 
VGS = - 4.5 V, ID = - 7 A 0.0127 0.0153
Forward Transconductancea gfs VDS = - 10 V, ID = - 10 A 32 S
b
Dynamic
Input Capacitance Ciss 3900
Output Capacitance Coss VDS = - 15 V, VGS = 0 V, f = 1 MHz 715 pF
Reverse Transfer Capacitance Crss 645
VDS = - 15 V, VGS = - 10 V, ID = - 10 A 90 135
Total Gate Charge Qg
44.8 68
nC
Gate-Source Charge Qgs VDS = - 15 V, VGS = - 4.5 V, ID = - 10 A 12.2
Gate-Drain Charge Qgd 21.7
Gate Resistance Rg f = 1 MHz 0.4 1.8 3.6 
Turn-On Delay Time td(on) 14 28
Rise Time tr VDD = - 15 V, RL = 1.5  13 25
Turn-Off DelayTime td(off) ID  - 10 A, VGEN = - 10 V, Rg = 1  49 90
Fall Time tf 13 25
ns
Turn-On Delay Time td(on) 70 120
Rise Time tr VDD = - 15 V, RL = 1.5  150 280
Turn-Off DelayTime td(off) ID  - 10 A, VGEN = - 4.5 V, Rg = 1  43 80
Fall Time tf 28 55
Drain-Source Body Diode Characteristics
Continous Source-Drain Diode Current IS TC = 25 °C - 4.9
A
Pulse Diode Forward Current ISM - 70
Body Diode Voltage VSD IS = - 3 A, VGS = 0 V - 0.72 - 1.2 V
Body Diode Reverse Recovery Time trr 41 70 ns
Body Diode Reverse Recovery Charge Qrr 41 70 nC
IF = - 10 A, dI/dt = 100 A/µs, TJ = 25 °C
Reverse Recovery Fall Time ta 18
ns
Reverse Recovery Rise Time tb 23
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

www.vishay.com Document Number: 68982

2 S10-2543-Rev. B, 08-Nov-10
 Si4483ADY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
70 10

VGS = 10 V thru 5 V

56 8
I D - Drain Current (A)

I D - Drain Current (A)

42 VGS = 4 V 6

28 4

TC = 25 °C

14 2
TC = 125 °C
TC = - 55 °C
0 0
0.0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.030 6000

0.024 4800
R DS(on) - On-Resistance (Ω)

Ciss
C - Capacitance (pF)

0.018 3600
VGS = 4.5 V

0.012 2400
VGS = 10 V
Coss
0.006 1200
Crss

0 0
0 14 28 42 56 70 0 6 12 18 24 30

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current Capacitance

10 1.8

ID = 10 A
ID = 10 A
VGS - Gate-to-Source Voltage (V)

8
1.5
R DS(on) - On-Resistance

VGS = 10 V
(Normalized)

6 VDS = 10 V
VDS = 15 V
1.2

4 VGS = 4.5 V
VDS = 20 V
0.9
2

0 0.6
0 20 40 60 80 100 - 50 - 25 0 25 50 75 100 125 150

Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

Document Number: 68982 www.vishay.com

S10-2543-Rev. B, 08-Nov-10 3
Si4483ADY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100 0.10

ID = 10 A

10 TJ = 150 °C 0.08

R DS(on) - On-Resistance (Ω)

I S - Source Current (A)

TJ = 25 °C
1 0.06

0.1 0.04
TJ = 125 °C

0.01 0.02
TJ = 25 °C

0.001 0.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6 7 8 9 10

VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

0.8 200

0.6
160
ID = 250 µA
VGS(th) Variance (V)

0.4
Power (W)

120
ID = 1 mA
0.2

80
0.0

40
- 0.2

- 0.4 0
- 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10
TJ - Temperature (°C) Time (s)
Threshold Voltage Single Pulse Power, Junction-to-Ambient

100

Limited by RDS(on)* 1 ms

10
I D - Drain Current (A)

10 ms

1
100 ms

1s
0.1 10 s

TA = 25 °C DC
Single Pulse
BVDSS Limited
0.01
0.01 0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area

www.vishay.com Document Number: 68982

4 S10-2543-Rev. B, 08-Nov-10
 Si4483ADY
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

22.0

17.6

I D - Drain Current (A)

13.2

8.8

4.4

0.0
0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating*

8.0 2.0

6.4 Power (W) 1.6

4.8 1.2
Power (W)

3.2 0.8

1.6 0.4

0.0 0.0
0 25 50 75 100 125 150 0 25 50 75 100 125 150

TC - Case Temperature (°C) TA - Ambient Temperature (°C)

Power, Junction-to-Foot Power Derating, Junction-to-Ambient

* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

Document Number: 68982 www.vishay.com

S10-2543-Rev. B, 08-Nov-10 5
Si4483ADY
Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Duty Cycle = 0.5

Normalized Effective Transient
Thermal Impedance

0.2

0.1 Notes:
0.1
PDM
0.05
t1
t2
t1
1. Duty Cycle, D =
0.02 t2
2. Per Unit Base = RthJA = 85 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4 10 -3 10 -2 10 -1 1 10 100 1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient

1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance

0.2

0.1
0.1
0.05

0.02

Single Pulse
0.01
10 -4 10 -3 10 -2 10 -1 1 10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68982.

www.vishay.com Document Number: 68982

6 S10-2543-Rev. B, 08-Nov-10
 Package Information
Vishay Siliconix

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

8 7 6 5

E H

1 2 3 4

D h x 45
C
0.25 mm (Gage Plane)
A
All Leads

q 0.101 mm
e B A1 L
0.004"

MILLIMETERS INCHES
DIM Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q 0° 8° 0° 8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498

Document Number: 71192 www.vishay.com

11-Sep-06 1
 VISHAY SILICONIX

TrenchFET® Power MOSFETs Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050 0.088
been been modified to provide the heat transfer capabilities 1.27 2.25
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains 0.088
0.027 2.25
the same. 0.69

See Application Note 826, Recommended Minimum Pad 0.078 0.2

1.98 5.07
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the Figure 2. Dual MOSFET SO-8 Pad Pattern
basis of the pad design for a LITTLE FOOT SO-8 power With Copper Spreading
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make The minimum recommended pad patterns for the
two connections: an electrical connection and a thermal
single-MOSFET SO-8 with copper spreading (Figure 1) and
connection, to draw heat away from the package.
dual-MOSFET SO-8 with copper spreading (Figure 2) show
In the case of the SO-8 package, the thermal connections the starting point for utilizing the board area available for the
are very simple. Pins 5, 6, 7, and 8 are the drain of the heat-spreading copper. To create this pattern, a plane of
MOSFET for a single MOSFET package and are connected copper overlies the drain pins. The copper plane connects
together. In a dual package, pins 5 and 6 are one drain, and the drain pins electrically, but more importantly provides
pins 7 and 8 are the other drain. For a small-signal device or planar copper to draw heat from the drain leads and start the
integrated circuit, typical connections would be made with process of spreading the heat so it can be dissipated into the
traces that are 0.020 inches wide. Since the drain pins serve
ambient air. These patterns use all the available area
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The underneath the body for this purpose.
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a Since surface-mounted packages are small, and reflow
large thermal impedance. Also, heat spreads in a circular soldering is the most common way in which these are
fashion from the heat source. In this case the drain pins are affixed to the PC board, “thermal” connections from the
the heat sources when looking at heat spread on the PC planar copper to the pads have not been used. Even if
board. additional planar copper area is used, there should be no
APPLICATION NOTE

problems in the soldering process. The actual solder

0.288
7.3
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
0.050
drain pins, the solder mask generation occurs automatically.
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
0.027
The absolute minimum power trace width must be
0.69 determined by the amount of current it has to carry. For
0.078 0.2
thermal reasons, this minimum width should be at least
1.98 5.07 0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
Figure 1. Single MOSFET SO-8 Pad
from the device.
Pattern With Copper Spreading

Document Number: 70740 www.vishay.com

Revision: 18-Jun-07 1
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172
(4.369)
0.028
(0.711)
(6.248)

(3.861)
0.246

0.152
(1.194)
0.047

0.022 0.050
(0.559) (1.270)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index
Return to Index
APPLICATION NOTE

www.vishay.com Document Number: 72606

22 Revision: 21-Jan-08
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12 1 Document Number: 91000