Society of St.

Francis Xavier, Pilar’s

Fr. Conceicao Rodrigues College of Engineering
Fr. Agnel Technical Education Complex Bandstand
Bandra (West) Mumbai -400 050

Module Unit
Topics Ref. Hrs.
No. No.
4 Finite State Machines 1,2 2
4.1 Verilog code for both Mealy & Moore FSM

Dr. Surendra Singh Rathod

Principal, Fr. Conceicao Rodrigues College of Engineering
principal.crce@fragnel.edu.in

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FSM Finite State Machine

• FSM —to create complex control machines
• General structure CLK RESET

NEXT STATE OUTPUT OUTPUTS

INPUTS STATE REGISTER FUNCTION

Mealy model
• State register: state variable
• Next state function: determines the next state (combinatorial logic)
• Output function: generates outputs
—Moore: based on the state register
—Mealy: based on the state registers and the current inputs
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 Finite State Machine
A Finite State Machine is described by:
l Its states and a description of their physical meaning.
l The way the machine makes the transitions to the next state. These must be based on
the present state and/or the present inputs only. The state is the collective contents of
all Flip-flops; The state memory is a set of n flip-flops that store the current state of
the machine, and it has 2n distinct states.
l The outputs from each state.
Mealy versus Moore FSM
Moore outputs depend only on the state of the machine. Moore machines
are easier to design.
Mealy outputs depend on the present state and the inputs. Mealy machines
usually have fewer states and thus are often smaller.

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Standard form for FSM in VERILOG

Break FSMs into four blocks:
State definitions-Next state calculations (decoder)-Registers or flip-flops calculation-Output
calculations (logic)

//state flip-flops
reg [2:0] state, next_state;

//state definitions
parameter S0=2’b00 S1=2’b 01, S2=2’b 10, S3=2’b11,…
// State machine descriptions
//Next state calculations
always @(state or….)
begin
case (state)
…..
end
//register or flip-flop calculation
always@(posedge clk)
state<=next_state
//Output calculations
Output=f(state, inputs)

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 FSM of a Mealy machine
Module FSM (clk, x, z);
input clk, x;
output z;
//state flip-flops Present Next state Output
reg[2:0] state, next_state; state X=0 X=1 z
// State definition
parameter S0=0, S1=1, S2=2, S3=3, S4=4; S0=000 S0=0 S1=1 0
//State machine description using case
always@ (state or x)
S1=001 S2=2 S3=3 0
begin
case(state)
S0: if (x) next_state=S1; S2=010 S4=4 S0=0 0
else next_state=S0;
S1: if (x) next_state=S3;
else next_state=S2; S3=011 S4=4 S2=2 0
S2: if (x) next_state=S0;
else next_state=S4; S4=100 S0=0 S0=0 1
S3: if (x) next_state=S2;
else next_state=S4;
S4: next_state=S0;
default: next_state=S0; Default S0=0 S0=0 0
endcase
end
//flip-flops calculations
always @ (posedge clk)
begin
state<=next_state;
end
//output calculations
assign z=(state==S4);
endmodule

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Recommendations for FSM

l The state must always be of type reg.

l The states should be given meaningful names rather than numbers. Define state
codes using symbolic constants defined using parameter. Assign the parameter a
size to avoid errors:
parameter [3:0] INIT=4’d0000, SETUP=4’d0001
l Do not mix the next state calculations with the flip-flop definitions.
l For next state calculations, it is very common to use a combination of case and if
for this block.
l Assign a default next state to gracefully handle what happens when the FSM
winds up in an unknown state. (Otherwise latches will be generated.)
l Output calculations: one simple assign statement can be easily used.

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 FSM example
• Traffic light (simple)
—States: red, yellow, green, red-yellow (no blinking yellow)
—Inputs: timers for the Present states
—Output: state

RY

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FSM example-1
always @ (*)
case(state_reg)
module light( Input clk, rst, output reg [2:0] led); RED: begin
if (timer == 0)
next_state <= RY;
parameter RED = 2’b00; else
parameter RY = 2'b01; next_state <= R;
parameter GREEN = 2’b10; end
RY: begin
parameter YELLOW = 2’b11; if (timer == 0)
next_state <= GREEN; else
reg [15:0] timer; next_state <= RY;
end
reg [1:0] state_reg; YELLOW: begin
reg [1:0] next_state; if (timer == 0)
next_state <= RED;
else
always @ (posedge clk) next_state <= YELLOW; end
if (rst) GREEN: begin
state_reg = RED; if (timer == 0)
next_state <= YELLOW;
else else
state_reg = next_state; next_state <= GREEN;
end default:
next_state <= 3'bxxx;
endcase

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 FSM example-2
always @ (posedge clk)
case(state_reg) Timer
RED: begin
if (timer == 0) — Loads a new value when state changes
timer = 500; //next_state = RY;
else — Down-counter
timer = timer - 1;
end
RY: begin
— ==0: state change
if (timer == 0)
timer = 4000; //next_state = GREEN;
else
timer = timer - 1;
end always @ (*)
YELLOW: begin case (state_reg)
if (timer == 0) RY led = 3'b110;
timer = 4500; //next_state = RED; RED: led = 3'b100;
else YELLOW: led = 3'b010;
timer = timer - 1; GREEN: led = 3'b001;
end default: led •= 3’b100;
GREEN: begin endcase
if (timer == 0)
timer = 500; //next_state = YELLOW; endmodule
else
timer = timer - 1;
end
endcase

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A Car Speed Controller

(~Accelerate) & (~ Brake) (~Accelerate) & (~ Brake)

Accelerate

SLOW MEDIUM
Brake
Accelerate
Accelerate
Brake Brake
~Brake

STOP FAST

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 always @(posedge clk or negedge keys)
Car Controller Coding begin
if(!keys)
speed = stop;
else if(accelerate)
case(speed)
stop: speed = slow;
slow: speed = mdium;
mdium: speed = fast;
fast: speed = fast;
endcase
else if(brake)
module fsm_car_speed_1(clk, keys, brake, accelerate, speed); case(speed)
input clk, keys, brake, accelerate; stop: speed = stop;
output [1:0] speed; slow: speed = stop;
reg [1:0] speed; mdium: speed = slow;
fast: speed = mdium;
parameter stop = 2'b00, endcase
slow = 2'b01, else
mdium = 2'b10, speed = speed;
fast = 2'b11; end
endmodule
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A Better Way!
• We keep a separate control part where the next state is calculated.
• The other part generates the output from the next state.
module fsm_car_speed_2(clk, keys, brake, accelerate, speed); fast:
input clk, keys, brake, accelerate;
if(brake)
output [1:0] speed; slow: newspeed = mdium;
reg [1:0] speed; if(brake) else
reg [1:0] newspeed; newspeed = stop; newspeed = fast;
else if(accelerate) default:
parameter stop = 2'b00, newspeed = mdium;
slow = 2'b01, newspeed = stop;
else endcase
mdium = 2'b10,
newspeed = slow; end
fast = 2'b11;
mdium:
always @(keys or brake or accelerate or speed)
if(brake) always @(posedge clk or negedge keys)
begin
case(speed) newspeed = slow; begin
stop: else if(accelerate) if(!keys)
if(accelerate) newspeed = fast; speed = stop;
newspeed = slow; else else
else newspeed = mdium; speed = newspeed;
newspeed = stop; end
endmodule
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 Two Ways!

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1010 non-Overlapping Mealy Sequence Detector Verilog Code

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 1010 Overlapping Mealy Sequence Detector Verilog Code

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