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    Sppu Se (It) End-Sem Exam Feb'2023 - Ldco

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    Sppu Se (It) End-Sem Exam Feb'2023 - Ldco

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    girgaonkar.chaitanya24
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    Sppu Se (It) End-sem Exam Feb'2023 - Ldco

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    Sppu Se (It) End-Sem Exam Feb'2023 - Ldco

    Uploaded by

    girgaonkar.chaitanya24

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    © All Rights Reserved
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    You are on page 1of 2

    Total No.

    of'Questions : 81
    SEAT No..
    PA-1243 [Total No. of Pages : 2
    159251-266
    S.E. (IT)
    LOGIC DESIGN & COMPUTER ORGANIZATION
    (2019 Paitcrn Ä(Scrncster - 111)(214442)
    Time : 2% Hours/ /M(LV..Varks : 70
    Instructionsto the •e
    1) Attempt (209.1 or (00.2, Q.No.3 or Q..V0.4,Q.N0.5 or Q.N0.6, Q.NO.70r Q.No.8.
    2) Neat diagrams mt/st be drawn wherever necessary.
    3) Figures rioht indicatefull marks.
    4) ifnecessary.

    Explai%with a diagram, the conversion ofJ-K flip flop to D flip flop. 191
    b) Diff&entiate between Latch & flip-flop w.r.t. definition, operation, diagram
    oåpplications etc.
    OR
    Design 3-bit synchronous dcvvn- counter using MS JK flip flop
    (IC 7476). (Pin numbers arenbi required) Draw only logic diagram. 191
    b) What is a shift register? St te the types of shift registers with applications
    of each. 191

    Explain in brief, various functional units of a computer systenl with a


    block diagram showing interconnection between them. 191
    b) Write a short note on; PC, MAR, MBR, TR. 181
    OR
    (24) a) What is the function of control unit in a CPU? Dr block diagram of
    Hardwived control unit & explain its operation & cons. 191
    b) Explain and draw basic structure of Harvar rchitecture. State the
    differences between Harvard and Von Neu n apn aytiiitecture. 181

    (25) a) What is meant by addressing 1110de?


    Ey!åiin ali addressing modes with
    examples. 191
    b) Differentiate between RISC & CISC architecture. 191
    OR

    P.T.O.
    (26) a) Explain instruction pipelining w.r.t.operation and speed up formula.
    achieved by pipelining. [91

    b) Explain interntpt w.r.t. its purpose, types. Describe step by step, the
    191
    interrup handling procedure of microprocessors.

    (27) a) Explain with eya:nples the various cache replacement policies. Describe
    various cache WTitepolicies. [91

    b) Explain pi-ogramn-,edcontrolled I/O with the help of flow chaff. [81

    OR
    (28) a) Along witli suitable diagralll, explain set associative cache mapping
    technique
    b) Explaiiimemory read cycle. with the help of suitabTetiming diagram. 181

    159251-266

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