1674 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO.

5, MAY 2009

Design of LCL Filters of Active-Front-End

Two-Level Voltage-Source Converters
Kamran Jalili and Steffen Bernet, Member, IEEE

Abstract—This paper introduces a new iterative design proce- M , M0 , Mn Modulation depth, no load modulation
dure of L and LCL filters for low-voltage active-front-end PWM depth, and nominal load modulation depth
two-level voltage source converters. The analytical expression of (M = reference signal amplitude/carrier
the converter harmonic voltages by Bessel functions is applied to √
design the filter parameters for defined maximum grid current signal amplitude, M0 = 2 2Vg,1 /Vdc ).
harmonics. Different filter designs are derived for various reso- Lf ,RLf Inductance and resistance of the L filter
nance frequencies and inductance split factors of LCL filter. The inductor.
minimum amount of stored energy of passive components is used Lf,max Upper limit of L filter inductance.
to select a final filter design. A voltage-oriented control scheme, Lf,g , RLf,g Inductance and resistance of grid-side in-
including active damping, is applied in the (400 V and 50 kVA) ex-
perimental setup. Both simulation and experimental investigations ductor of LCL filter.
are presented to verify the accuracy of the filter design procedure. Lf,conv , RLf,conv Inductance and resistance of converter-
Finally, the steady state and transient performance of the active side inductor of LCL filter.
front end with different LCL filters are depicted. Cf LCL filter capacitance.
Index Terms—Active damping, active front end, LCL filter. fres LCL filter resonance frequency.
r LCL filter split factor, r = Lf,g /Lf,conv .
Cdc DC-link voltage capacitance.
N OMENCLATURE
Vdc,reserve,% DC-link voltage reserve.
x Instantaneous value of quantity x. Iˆg,(mf −2),desired,% Desired amplitude of the (mf − 2)th grid
X, X̂ RMS value and amplitude of quantity x. current harmonic in percent of rated fun-
X1 , X̂1 RMS value and amplitude of fundamental damental component (e.g., according to
component of quantity x. IEEE-519).
Xh ,X̂h RMS value and amplitude of harmonic Iˆg,(mf −2),0,% Amplitude of the (mf − 2)th grid current
components of quantity x. harmonic at no load condition in percent
x Complex vector in α–β coordinate. of rated fundamental component.
x1 Complex vector of fundamental compo- Iˆg,(mf −2),n,% Amplitude of the (mf − 2)th grid current
nents in α–β coordinate. harmonic in percent of fundamental com-
g, conv Subscripts for grid and converter ponent at rated load condition.
quantities. Iˆripple,max Maximum amplitude of current ripple
ll Subscripts for line-to-line quantities. (Iˆripple,max = max |i(t) − i1 (t)|).
fg ,Lg Grid fundamental frequency and grid
stray inductance.
S-PWM Asymmetrical regular sampled sinus tri- I. I NTRODUCTION
angle pulsewidth modulation [29].
ZSS-PWM Asymmetrical regular sampled sinus tri-
angle pulsewidth modulation with added
third harmonic [29].
E MERGING applications like regenerative energy sources,
increasing energy prices, and strict international grid stan-
dards are the reason, therefore, that pulsewidth-modulation
fC , fs Carrier frequency and sampling (PWM) voltage-source converters (VSCs) are increasingly ap-
frequency. plied as active-front-end converters in low-voltage drives. Si-
mf Modulation index (mf = carrier nusoidal input currents, an adjustable power factor at the point
frequency/reference frequency). of common coupling (PCC), ride-through capability, and an
Vdc , Vdc,min DC-link voltage and minimum required adjustment of the dc-link voltage are further advantages of such
dc-link voltage. a converter topology (see, e.g., [1]–[9]).
An inductance is the most simple filter configuration between
PWM voltage source converter and grid. However, the limited
Manuscript received January 29, 2008; revised November 11, 2008. First
published January 6, 2009; current version published April 29, 2009. maximum dc voltage and dynamic performance of a converter
K. Jalili is with the Converteam GmbH, 12277 Berlin, Germany (e-mail: with common switching frequencies, as well as the substantial
kamran.jalili@converteam.com). costs and size of the inductance, avoid the use of a pure induc-
S. Bernet is with Dresden University of Technology, 01069 Dresden,
Germany (e-mail: steffen.bernet@tu-dresden.de). tive filter for medium- and high-power converters (S > x kVA)
Digital Object Identifier 10.1109/TIE.2008.2011251 [10], [11].
0278-0046/$25.00 © 2009 IEEE
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1675

Fig. 1. Three-phase active rectifier with L and LCL filters.

The application of an LCL filter is an attractive solution to TABLE I

BASIC GRID AND CONVERTER PARAMETERS
overcome these problems. The higher harmonic attenuation of
the LCL filter permits the use of lower switching frequencies
to meet the harmonic limits presented in the standards (e.g.,
IEEE-519-1992 [12]).
The design of the LCL filter components according to given
maximum current harmonics (e.g., IEEE-519-1992) is a com-
plex task. Today, there is no precise design method based on
the limitation of the grid harmonic currents.
Reference [10] presents a design procedure using the try
and error method. In particular, the selection of the initial
values for the converter current ripple and the filter capacitance
absorbed reactive power complicates the design procedure.
Furthermore, the design of the converter-side inductance for
a selected converter current ripple is not addressed. Basic
analytical expressions to calculate the upper limits of the
filter inductance, filter capacitance, and converter current
ripple are presented in [13]–[17]. Reference [18] describes a
design procedure where the maximum converter current ripple
determines the design of the filter inductance and the filter
capacitance is chosen based on the reactive power. Basic criteria
for an LCL filter design on the basis of the filter attenuation
factor for the grid current harmonic at switching frequency
are presented in [19]. However, so far, a precise analytical II. S YSTEM C ONFIGURATION AND S PECIFICATIONS
design procedure considering the control reserve limitation
and the amplitudes of the grid current harmonics was not The structure of the active-front-end converter used to inves-
presented. tigate the filter design procedure and the system performance
In this paper, an iterative procedure to design the L and LCL is shown in Fig. 1. The interface between the grid and the
filter parameters considering the most significant grid current converter is an L filter or an LCL filter to damp the current
harmonic is proposed based on the guidelines presented in [10]. harmonics injected into the grid. The filter components are
The procedure uses the analytical expression of the converter considered to be variable to study system and filter performance
voltage harmonics by Bessel functions. Exemplarily, the stored for various filter designs. A two-level VSC (2L VSC) with a
energy of the filter components as a measure for the expense carrier frequency of 4.05 kHz is used as the power converter.
of passive components is considered to compare different filter The basic system parameters are summarized in Table I.
designs.
An active damping scheme of the current control loop is
III. F ILTER D ESIGN P ROCEDURE
applied to avoid filter resonance. In recent publications, the
active damping function is achieved based on the feedback The input L and LCL filters are designed to meet
of filter state variables [20]–[25] or sensorless methods the harmonic distortion limits according to IEEE-519-1992.
[26]–[28]. In this paper, the filter capacitor voltages are Table II depicts the IEEE-519-1992 definitions for the harmonic
measured and a simple design procedure for the required current limits at the PCC [12]. Considering the capability of the
compensator is presented. Finally, experimental results of the active rectifier to operate at power generation mode, the spectra
system performance during transients and in steady state are content of the grid current harmonics around the switching
shown. frequency and multiples of the switching frequency should be
1676 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

TABLE II the reference vector [Fig. 2(b)], the fundamental component of

CURRENT HARMONIC LIMITS IN PERCENTAGE OF RATED CURRENT
AMPLITUDE ACCORDING TO IEEE-519 [12] the filter inductance voltage drop vector at steady state is

vg,1 − vconv,1 = jωg (Lg + Lf )ig,1 (1)

where
vg,1 = Vg,1 ∠0 vconv,1 = Vconv,1 ∠θvconv,1
ig,1 = Ig,1 ∠0 ωg = 2πfg .

The upper limit filter inductance at rated grid current can

be calculated by substituting the maximum amplitude of the
converter phase voltage for vconv,1 in (1). The real and imag-
√ of (1) for the maximum effective value of Vconv =
inary parts
Vdc /2 2 with S-PWM are
 √
Vg,1 − 42 Vdc cos(θvconv,1 ) = 0
√ (2)
− 42 Vdc sin(θvconv,1 ) = ωg (Lg + Lf )Ig,1 .

By using (2), the upper limit of the filter inductance corre-

sponding to the maximum amplitude of the converter output
voltage and the rated grid current can be derived as
 2
Vdc
8 − Vg,1
2
Lf,max = − Lg . (3)
ωg Ig,1
In the case of sinus-triangle modulation with added third
harmonic zero-sequence signal (ZSS-PWM), the maximum
√ value of converter output voltage increases to Vconv =
effective
Vdc / 6 [22]. By using (2), the upper limit of the filter induc-
tance for ZSS-PWM is
 2
Vdc
6 − Vg,1
2
Lf,max = − Lg . (4)
ωg Ig,1
Lf,max causes the upper limit filter voltage drop at rated
current and unity power factor conditions for a dc-link voltage
Fig. 2. (a) Single-phase representation of an active PWM rectifier with
L filter. (b) Fundamental components of the line voltage vector, the grid current
of Vdc .
vector, and the converter phase voltage vector in the α–β coordinate system for The lower limit of the filter inductance is caused by the
the unity power factor condition. required limitation of the current harmonics around the first
carrier band according to IEEE-519. In the following, the ana-
attenuated to be lower than 0.3%. It should be noted that in the lytical representation of the converter phase voltage harmonics
design procedure of both L and LCL filters, the resistance of is applied in order to design the filter inductance. The harmonic
the filter inductors is assumed to be negligible in comparison to voltage amplitude per harmonic frequency is a measure for the
the inductive reactance at switching frequency. potential of the harmonic voltage to produce a corresponding
harmonic current. The filter inductance is designed based on
the most significant converter phase voltage harmonic with the
A. L Filter highest ratio of voltage and frequency. For an S-PWM, the
A single-phase representation of the active rectifier with amplitude of the converter phase voltage harmonics based on
L filter is shown in Fig. 2(a). There are upper and lower limits the Bessel functions is given as follows [29]:
for the total filter inductance Lg + Lf because of the limited 2Vdc  π  π 
maximum filter voltage drop at a limited dc-link voltage for V̂n,μ = sin (n + μ) Jμ qn,μ M (5)
πqn,μ 2 2
a given power semiconductor voltage class and the limitations
of the grid current harmonics. The converter is considered to where
operate with its maximum output voltage (maximum modu- V̂n,μ amplitude of the phase voltage harmonic;
lation depth in linear range) and rated current at unity power n carrier band number [1, ∞);
factor conditions in order to find the upper limit inductance μ side band number (−∞, ∞);
corresponding to the maximum filter voltage drop. If the fun- J Bessel function;
damental component of the grid voltage vector is considered as qnμ = n + μ(fg /fC ).
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1677

amplitude of the (mf − 2)th grid harmonic current at no load

conditions in percent of rated fundamental component. The
desired amplitude of the (mf − 2)th grid harmonic current in
percent of the fundamental component at rated load conditions
(e.g., according to IEEE-519) is denoted as Iˆg,(mf −2),desired,% .
Finally, the amplitude of the (mf − 2)th grid current har-
monic at nominal load Iˆg,(mf −2),n,% is calculated by applying
the filter inductance and Mn . The initial value of Iˆg,(mf −2),0,%
Fig. 3. (a) First carrier band of the converter output phase voltage har- should be changed in an iterative manner based on the cal-
monic spectra for S-PWM (Vll,conv,1 = 400 V, Vdc = 700 V, mf = 81) and culated Iˆg,(mf −2),n,% to obtain a grid harmonic current of
ZSS-PWM (Vll,conv,1 = 400 V, Vdc = 906 V, mf = 81). (b) Volt per hertz
value of the (mf − 2)th order harmonic to the volt per hertz value of the (mf − 2)th order which is below the IEEE-519 limitations.
(mf + 2)th order harmonic of the converter phase voltage for various values The converter phase harmonic voltage of (mf − 2)th order
of M and fC . at no load condition is given by

The first carrier band of the converter output phase voltage is 2Vdc √ Vg,1 fg
shown in Fig. 3(a). The harmonic voltage of (mf − 2)th order V̂1,−2 = J2 π 2q1,−2 , q1,−2 = 1 − 2 .
πq1,−2 Vdc fC
(n = 1, μ = −2) is the most significant harmonic voltage in (6)
the harmonic spectrum of vconv = vxNg , x = a, b, c (see Fig. 1),
because of its higher volt per hertz ratio compared to the other Therefore, the per unit value of the required inductance to
significant harmonics. The volt per hertz ratio of the harmonic limit the amplitude of the (mf − 2)th grid current harmonic
voltage of (mf + 2)th order is smaller than that of the harmonic to Iˆg,(mf −2),0,% at no load is
voltage of (mf − 2)th order for a regular asymmetric PWM  √ 
V
despite its higher amplitude. The ratio of the volt per hertz value √ J2 π 2q1,−2 Vg,1
dc
of the harmonic voltage of the (mf − 2)th order to the volt Lf,t,pu = 100 2 V
(7)
per hertz value of the harmonic voltage of (mf + 2)th order, πq1,−2 (mf − 2)Iˆg,(mf −2),0,% Vg,1
dc

depending on the modulation depth M and carrier frequency

where
fC , is shown in Fig. 3(b) if an S-PWM is applied.
Fig. 3(a) shows the first carrier band spectrum of the con- Lf,t Vg,1
verter output phase voltage for a frequency ratio of mf = 81 Lf,t = Lf + Lg , Lf,t,pu = , Lb = .
Lb ωg Ig,1
and the dc-link voltages of 700 and 609 V for S-PWM and
ZSS-PWM, respectively. Different dc-link voltage is chosen Variation of the modulation depth at nominal load condition
for both modulations to enable a comparable dc-link volt- should be taken into account in order to calculate the value of
age reserve. Obviously, the application of the ZSS-PWM re- the current harmonic Iˆg,(mf −2),n,% at rated load. By using the
duces the amplitude of the harmonic voltages and results in filter inductance voltage drop (1), the fundamental component
a wider sideband in comparison with the S-PWM [29]. The of the converter phase voltage for the rated grid current and
complex analytical depiction of the harmonic voltages for the unity power factor is
ZSS-PWM is presented in [29]. In order to simplify the filter  
design procedure, the filter inductance is determined based on Vconv,1 = Vg,1 2 + I 2 ω 2 L2 = V 2
g,1 g f,t g,1 1 + Lf,t,pu . (8)
the harmonic voltage amplitude presented in [29] for S-PWM.
According to the aforementioned comparison of the first carrier Therefore, the modulation depth at nominal load for the
band spectrum of the S-PWM and the ZSS-PWM, the filter designed filter inductance with the carrier amplitude of
inductance determined based on (5) will guarantee that the Vdc /2 is
IEEE-519 limits will not be exceeded if, instead of the S-PWM, √
a ZSS-PWM is applied. 2 2Vg,1 
Mn = 1 + L2f,t,pu . (9)
The amplitude of the (mf − 2)th converter phase voltage Vdc
harmonic at nominal load can be used to design the filter
inductance for a desired grid current harmonic requiring the Applying Mn (9) and the amplitude of the (mf − 2)th con-
nominal load modulation depth Mn according to (5). Mn de- verter voltage harmonic (5), the amplitude of the grid current
pends on the filter voltage drop in a closed-loop control system. harmonic of (mf − 2)th order at nominal load is
Thus, the filter inductance is required in the determining of
√ J2 q1,−2 π2 Mn
Mn . Obviously, an iterative procedure is essential to calcu- Iˆg,(mf −2),n,% = 100 2 Vg,1
. (10)
late the filter inductance. Therefore, the no load modulation πq1,−2 (mf − 2)Lf,t,pu Vdc
depth M0 , which is independent of filter inductance, is used
in the proposed design procedure to calculate the amplitude As mentioned, if Iˆg,(mf −2),n,% in (10) exceeds the
of the (mf − 2)th converter phase voltage harmonic in a IEEE-519 limitation, the chosen initial value for the no load
first step. In the next step, the required filter inductance is grid current harmonic Iˆg,(mf −2),0,% in (7) should be reduced
determined considering the grid current harmonic limitations and the filter inductance should be designed in an iterative man-
Iˆg,(mf −2),0,% ≤ Iˆg,(mf −2),desired,% . Iˆg,(mf −2),0,% denotes the ner by applying (7)–(10).
1678 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

The maximum amplitude of the inductor current ripple at no

load conditions is approximated by

Vg,1
Iˆripple,max,pu ≈ √ (11)
2 6fC Lf,t

neglecting the inductor resistance and assuming a closed-loop

control [13]. Furthermore, the dc-link voltage reserve for the
control system can be defined as follows:

Vdc − Vdc,min
Vdc,reserve,% = 100 (12)
Vdc

where Vdc,min is the minimum required dc-link voltage for a

designed filter inductance.
According to the filter voltage drop (1) and the fundamental
component of the converter phase voltage (8), the minimum
required dc-link voltage for a total filter inductance of Lf,t =
Lg + Lf is

 
Vdc,min = Vg,1 m 1 + L2f,t,pu (13)

where parameter m is 8 for S-PWM and 6 for ZSS-PWM.

Consequently, the dc-link voltage reserve in percent of the rated
dc-link voltage for a designed filter inductance is
 
Vg,1
Vdc,reserve,% = 100 1 − m(1 + Lf,t,pu )2 . (14)
Vdc

A flowchart of the proposed L filter design procedure is

shown in Fig. 4. The design can be started with useful initial
values of the dc-link voltage and the modulation index (e.g.,
Vdc = 700 V and mf = 81). The dc-link voltage or the switch-
ing frequency can be increased to achieve an increased upper
limit of the inductance if the calculated inductance is larger than
the upper limit according to (3). In the flowchart of Fig. 4, the Fig. 4. Flowchart of the proposed L filter design procedure to limit the
dc-link voltage is increased in the first step to get a higher upper amplitude of the grid harmonic current to a desired value.
limit filter inductance. In a second step, the carrier frequency
fC and, subsequently, the frequency index should be increased TABLE III
if the limits of the IEEE-519 cannot be achieved for the given RESULTS OF THE L FILTER DESIGN PROCEDURE FOR DIFFERENT DC-LINK
VOLTAGES; Vdc,reserve,% ≈ 5
maximum dc-link voltage. The maximum possible dc-link volt-
age Vdc,max is determined by the blocking characteristics of the
applied power semiconductors, gate units, cooling conditions,
and the stray inductance of the converter configuration [30].
The upper limit of the filter inductance is Lf,max = 4.2 mH
according to (3) and assuming the conditions of Table I and
S-PWM. The grid current harmonic of (mf − 2)th order is
limited to about 1% of the rated grid current amplitude in
this case. By using a proper gate resistance and a suitable quency has to be increased to reach the IEEE-519 compliance.
mechanical design to reduce the turn-off overvoltage, the dc- Finally, an inductance value of Lf = 6.2 mH was calculated
link voltage can be increased to 800 V considering the applied during the iterative design procedure according to the flowchart
IGBT modules. of Fig. 4 for fC = 10.125 kHz (mf = 202.5) and Vdc = 800 V.
The upper limit of the filter inductance is calculated to The dc-link voltage reserve is about 5% in this case according
Lf,max = 7.5 mH for Vdc = 800 V. If the new upper limit is to (14). Required switching frequency and filter inductance in
used, the grid current harmonic of (mf − 2)th order is limited order to fulfil the IEEE-519 conditions (Iˆg,(mf −2),n,% ≤ 0.3)
to about 0.7% of the rated grid current amplitude which is again for different dc-link voltages are presented in Table III. The dc-
above the IEEE-519 limitation of 0.3%. Thus, the carrier fre- link voltage reserve Vdc,reserve,% is considered to be about 5%.
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1679

harmonic is required to determine Lf,conv which is calculated

by applying the IEEE-519-defined grid current harmonic am-
plitude and the filter attenuation factor ig (s)/iconv (s).
According to Fig. 5, the grid current harmonics are related to
the converter current harmonics by

ig (s) 1
= , Lf,g,t = Lg +Lf,g , s = jωg .
Fig. 5. Single-phase representation of the active rectifier with LCL filter. iconv (s) 1+s2 Lf,g,t Cf
(17)
B. LCL Filter
As shown in the previous section, the L filter is only a Substituting the filter inductance values and the resonance
useful solution at very high switching frequencies. An LCL frequency for the filter capacitance, the attenuation factor (17)
filter enables a distinctly cheaper and smaller filter solution at becomes
low switching frequencies (e.g., fC = 4 kHz–8 kHz) which are  
Iˆg,(mf −2)  kf2 
usually applied in industrial low-voltage drives [10], [20].  
= 2  (18)
An iterative design procedure of an LCL filter is proposed ˆ
Iconv,(mf −2)  kf − r − 1 
in this section. The main goal is to limit the (mf − 2)th grid
current harmonic at nominal load to the values defined in for the (mf − 2)th current harmonic, with
IEEE-519. A single-phase representation of the active rectifier
fres
with LCL filter is shown in Fig. 5. The filter split factor r and kf = . (19)
the filter resonance frequency fres as the LCL filter parameters (mf − 2)fg
are given by
Applying (18), the converter-side filter inductance is derived
Lf,g,t for given filter parameters r and fres , on the basis of (7), to
r= , Lf,g,t = Lg + Lf,g (15)  
Lf,conv  
 kf2 
Lf,conv,pu = a1  2  (20)
1 Lf,conv + Lf,g,t  kf − r − 1 
fres = . (16)
2π Lf,conv Lf,g,t Cf
where
The filter resonance frequency (16) is considered to be in a  √ 
V
range between ten times of the grid frequency and one-half of √ J2 π 2q1,−2 Vg,1
dc
a1 = 100 2 V
the carrier frequency in order to avoid a filter excitation by the πq1,−2 (mf − 2)Iˆg,(mf −2),0,% Vg,1
dc
converter voltage harmonics [10].
In the proposed LCL filter design procedure, the converter- Lf,conv Vg,1
Lf,conv,pu = , Lb = .
side filter inductance Lf,conv is determined at no load con- Lb ωg Ig,1
dition M = M0 in a first step. The required inputs of the
design procedure are the filter parameters r and fres , the Iˆg,(mf −2),0,% is the amplitude of the grid harmonic current of
IEEE-519-defined (mf − 2)th grid current harmonic amplitude (mf − 2)th order at no load conditions in percent of the rated
Iˆg,(mf −2),desired,% , and the active rectifier basic parameters grid current amplitude.
(see, e.g., Table I). The other passive filter components Lf,g Applying the determined converter-side filter inductance (20)
and Cf are calculated then based on Lf,conv and the filter and the filter split factor (15), the grid-side filter inductance is
parameters defined in (15) and (16). The Thevenin equivalent  
 kf2 
circuit of the converter-side LC-grid is used in the next step  
Lf,g,t,pu = a1 r  2  , Lf,g,pu = Lf,g,t,pu − Lg,pu .
to model the LCL filter as an L filter. The (mf − 2)th grid  kf − r − 1 
current harmonic amplitude Iˆg,(mf −2),n,% for rated grid current (21)
is determined by applying this model and the calculated passive
filter components in order to verify the filter effectiveness at By using (16), the filter capacitance is
nominal load. Finally, the required passive filter components
r2 +r(2−kf2 )+(1−kf2 ) 1
for nominal load conditions are calculated in an iterative man- Cf,pu = a2 , a2 = (22)
ner by applying the calculated deviation ΔIˆg,(mf −2),0,% = rkf 4 (mf −2)2 a1
Iˆg,(mf −2),n,% − Iˆg,(mf −2),desired,% .
for a chosen filter resonance frequency and split factor with
The converter-side filter inductance Lf,conv is determined
on the basis of (7) to limit the (mf − 2)th converter current Cf Ig,1
harmonic at no load condition like described before for the Cf,pu = , Cf,b = .
Cf,b ωg Vg,1
design of the L filter. The filter capacitors are assumed to have
zero impedance for the current harmonics at the switching fre- The modulation depth at nominal load condition Mn can
quency. The amplitude of the (mf − 2)th converter-side current be specified using the calculated passive component values
1680 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

By using the dc-link voltage reserve defined in (12) and the

LCL filter voltage drop in Fig. 6, the dc-link voltage reserve for
the active rectifier at unity power factor is calculated like before
for the L filter design

Vdc,reserve,% = 100
 
Vg,1  
× 1− 2
m XLC,f +(Lf,g,t,pu XLC,fg +Lf,conv,pu )2
Vdc g

(26)

where parameter m is 8 for S-PWM and 6 for ZSS-PWM.

If the influence of the filter capacitance on the converter-side
Fig. 6. Single-phase representation of the converter with the LCL filter
applying the Thevenin equivalent circuit for converter-side LC-grid.
current ripple is neglected, the following equation can be used
to approximate the maximum converter current ripple [13]:

Lf,conv , Lf,g , and Cf . Mn is used to verify the amplitude of Vg,1

Iˆripple,max ≈ √ . (27)
the (mf − 2)th grid current harmonic, while the active rectifier 2 6fsw Lf,conv
operates at nominal load and unity power factor. In order to
calculate Mn , the single-phase representation of the LCL filter The grid current harmonics at rated load condition should not
in Fig. 5 is simplified to the single-phase representation shown exceed the IEEE-519 limits. The chosen amplitude of the grid
in Fig. 6 by applying the Thevenin equivalent circuit of the current harmonic Iˆg,(mf −2),0,% should be reduced in (20), and
converter-side LC-grid. The parameters shown in Fig. 6 for an the passive filter components should be designed in an iterative
angular frequency ω are manner by applying (20)–(26) if the grid current harmonics in
(25) are higher than the limits. A flowchart of the proposed
Lf,conv LCL filter design procedure is shown in Fig. 7. The design
Lth =
XLC procedure can be started with initial values of dc-link voltage
Vdc , modulation index mf , chosen filter parameters r and fres ,
vconv and the desired amplitude of the (mf − 2)th grid current har-
vth =
XLC monic Iˆg,(mf −2),desired,% . In the first iteration, Iˆg,(mf −2),0,% is
 2 considered to be equal to Iˆg,(mf −2),desired,% .
ω
XLC = 1 − Lf,conv Cf ω = 1 − Lf,conv,pu Cf,pu
2
. Applying (20)–(22), the LCL filter reactive component val-
ωg ues Lf,conv , Lf,g , and Cf are determined at no load condition.
The rated load modulation depth Mn is calculated using (24) to
(23)
determine the dc-link voltage reserve and the (mf − 2)th grid
current harmonic Iˆg,(mf −2),n,% at nominal load. Obviously, the
Considering the fundamental component of the filter voltage
dc-link voltage reserve must be positive and correspond to the
drop in Fig. 6, the modulation depth for an S-PWM at rated
required converter dynamic. Furthermore, Iˆg,(mf −2),n,% should
load can be calculated in the same manner as presented for the
L filter design in Section III-A. be in vicinity of Iˆg,(mf −2),desired,% with an acceptable tolerance
ε. The difference between Iˆg,(mf −2),n,% and Iˆg,(mf −2),desired,%
√ Vg,1 
Mn = 2 2 2
XLC,f + (Lf,g,t,pu XLC,fg + Lf,conv,pu )2 is applied to change the initial value of Iˆg,(mf −2),0,% and
Vdc g
design the filter components in an iterative procedure as shown
in Fig. 7. The grid current harmonics will be limited to the
XLC,fg = 1 − Lf,conv,pu Cf,pu . (24)
required values (e.g., IEEE-519) for every combination of the
filter parameters r and fres , while considering the limitation
Applying the simple single-phase representation of the con- of the resonance frequency and the dc-link voltage reserve, if
verter with LCL filter in Fig. 6 and the nominal modulation the filter components are designed according to the procedure
depth (24), the amplitude of the most significant grid current shown in Fig. 7.
harmonic Iˆg,(mf −2),n,% at nominal load condition is Fig. 8 shows the LCL filter components for different values
√ of r and fres . The filter design is achieved by applying the
100 2Vdc
Iˆg,mf −2,n,% = iterative procedure to get a grid harmonic current Iˆg,(mf −2),n,%
πq1,−2 (mf − 2)Vg,1 of, e.g., 0.2% according to IEEE-519. The error tolerance
π
ε in Fig. 7 is considered to be 0.001% of the fundamental
J2 2 q1,−2 Mn component of the grid current. The system parameters are taken
×
XLC,(mf −2)fg Lf,g,t,pu + Lf,conv,pu from Table I.
It is shown in Fig. 8 that, for high resonance frequencies,
XLC,(mf −2)fg = 1 − (mf − 2)2 Lf,conv,pu Cf,pu . (25) the value of the filter total inductance Lf,t = Lf,g,t + Lf,conv
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1681

order to select a useful LCL filter design, the stored energy, as

a measure for the size and expense of passive components, is
considered in this paper. Thus, the filter parameters r and fres
are derived corresponding to the minimum filter energy. The
total filter energy can be approximated by

3 2
Wt = I (Lf,conv + Lf,g,t ) + Cf Vg2 . (28)
2 g,1

The fundamental current of the filter capacitor and the grid-

side inductor voltage drop are neglected in this approxima-
tion. The stored energy in the total filter inductance Lf,t ,
the energy of the filter capacitance Cf , and the total stored
energy corresponding to the filter reactive component values
in Fig. 8 are shown in Fig. 9. The amplitude of the grid current
harmonic Iˆg,(mf −2),desired,% is limited to 0.2% with a tolerance
of 0.001%.
Obviously, the total stored filter energy reaches a minimum
for a specific filter resonance frequency. In contrast, the ratio
r = Lf,g /Lf,conv only slightly influences the stored energy of
the filter. The filter parameters and the filter component values
corresponding to the minimum energy are presented in Table IV
for grids with different rated currents, different dc-link voltages,
and industrial line-to-line voltages of 400 and 690 V. As shown
in Table IV, the per unit values for the reactive filter compo-
nents and also the filter parameters r, kf corresponding to the
minimum stored energy remain constant for grids with different
rated currents. Furthermore, the parameters and component
values do not change for the 690 V grid if the dc-link voltage
increases proportional to the line voltage (Vdc = 1212 V).
The design results are independent of rated grid voltage and
dc-link voltage according to (20)–(22) if the ratio of Vg,1 /Vdc
is considered to be constant. An increased dc-link voltage to
800 V leads to smaller filter components because of a lower
modulation depth at nominal load condition. The amplitude of
the (mf − 2)th converter voltage harmonic reduces according
to (5) if M is reduced. Obviously, a smaller inductance is
required for a reduced converter voltage harmonic and constant
Fig. 7. Flowchart of the proposed LCL filter design procedure to limit the desired grid current harmonics. The converter current ripple for
amplitude of the grid current harmonics to a desired value with a constant the active rectifier with 800 V dc-link voltage increases, and
dc-link voltage and carrier frequency.
the resonance frequency causing minimum filter energy varies
from 1.016 to 1.046 kHz. The converter-side inductance and the
increases. Moreover, the total inductance remains almost con- grid-side inductance are almost equal for all converter data of
stant for every resonance frequency while r changes. In con- Table IV.
trast, the filter capacitor increases if the resonance frequency The ZSS-PWM is usually applied in industry applications
is decreased. Furthermore, the grid current harmonic with due to the reduced dc-link voltage (15%) compared to the
(mf − 2)th order at nominal load condition is shown in S-PWM for the same maximum output voltage. The filter
Fig. 8(e), which remains almost constant for filters with differ- components depicted in Table IV are used for active rectifier
ent component values. The maximum converter current ripple with LCL filter and ZSS-PWM, and the simulation results for
in per unit is shown in Fig. 8(f). The converter-side filter (mf − 2)th order grid current harmonics are shown in Table V.
inductance increases for high resonance frequencies, and conse- The dc-link voltage is reduced to achieve a dc-link voltage
quently, the maximum amplitude of the converter current ripple reserve like that of S-PWM. The amplitude of the (mf − 2)th
decreases. As mentioned, the total inductance Lf,t remains grid current harmonic is shown in Table V, which is reduced
almost constant while r changes. Therefore, the converter-side to 0.15%. However, a certain reserve is useful in the practical
inductance decreases, and consequently, the converter current implementation of LCL filter considering parasitic effects and
ripple increases for rising values of r. component variation in real configuration (see Section VI).
There are several LCL filter optimization criteria like mini- The dc-link voltage is considered to be constant for filters
mum volume and weight and minimum filter stored energy. In with different component values in the LCL filter design
1682 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

Fig. 8. Filter components for various values of r and fres to fulfill the IEEE-519 condition; Vg,ll = 400 V, Vdc = 700 V, mf = 81. (a) The converter-side
inductance, (b) the total grid-side inductance, (c) the filter total inductance, (d) the filter capacitance, (e) the amplitude of the grid harmonic current, and (f) the
converter current ripple.

Fig. 9. Stored energy of the reactive components of the LCL filters shown in Fig. 8; Vg,ll = 400 V, Ig,1 = 70 A, Vdc = 700 V, mf = 81. (a) Energy of the
total inductance, (b) energy of the filter capacitance, and (c) the filter total energy.
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1683

TABLE IV
LCL FILTER PARAMETERS AND REACTIVE COMPONENT VALUES CORRESPONDING TO THE MINIMUM FILTER ENERGY FOR DIFFERENT RATED GRID
CURRENTS, DC-LINK VOLTAGE, AND LINE VOLTAGE (MODULATION: S-PWM, Ig,(mf −2),desired,% = 0.2)

TABLE V
LCL FILTER PARAMETERS AND REACTIVE COMPONENT VALUES CORRESPONDING TO THE MINIMUM FILTER ENERGY FOR DIFFERENT RATED GRID
CURRENTS, DC-LINK VOLTAGE, AND LINE VOLTAGE (MODULATION: ZSS-PWM, Ig,(mf −2),desired,% = 0.2)

procedure of Fig. 7 which induces different control reserves. active rectifier with LCL filter in Fig. 5, the current of the
The total filter inductance increases, as shown in Fig. 8, for converter-side inductor can be described by
filters with increasing resonance frequencies, and consequently,
d
the control reserve decreases, leading to a decreasing dynamic Lf,conv iconv + RLf,conviconv = vCf − vconv . (29)
performance. The dc-link voltage can be changed considering dt
the control reserve (26) in order to achieve a defined dc-link Equation (29) is transformed into the rotating frame. The
voltage reserve (Fig. 10). As mentioned in the L filter design, it corresponding d–q components are given in (30), shown at the
should be noticed that the maximum value of the dc-link voltage bottom of the page. The following decoupling terms should be
is limited by the blocking characteristics of the semiconductors added to the output of the current controllers to get a first-order
and the converter design. current control loop:

Δvd = vCf ,d + Lf,conv ωg iconv,q
IV. C ONTROL S YSTEM (31)
Δvq = vCf ,d − Lf,conv ωg iconv,d .
In order to evaluate the proposed design procedure of LCL
filter with simulation and experimental results, a closed-loop The current control loop with corresponding processing and
control system with active damping is applied. The voltage- PWM delays [17] is shown in Fig. 12. The parameters of the
oriented control (VOC) applying a PI current control was cho- current control loop are
sen as a control scheme of the active rectifier [20]–[22], [25].
1 Lf,conv
The converter currents are transformed into the rotating frame K= , τ=
synchronous to the voltage vector of the filter capacitors. The RLf,conv RLf,conv
converter-side inductor current is controlled using the capacitor Lf,conv
Kp = , Ti = τ, a≥2
voltages and the converter currents as feedback. The main 1.5aTs
advantage of such a control is the robustness of the current 1
controller against the grid inductance variation and the effect Ts = : sampling time. (32)
fs
of the active damping based on the capacitor voltages [20].
A block diagram of the applied control system is shown Fig. 12 shows that it is not possible to achieve a completely
in Fig. 11. Considering the single-phase representation of the decoupled system due to the current control loop delay. The

 d
Lf,conv dt iconv,d + RLf,conv iconv,d = −vconv,d + vCf ,d + Lf,conv ωg iconv,q
(30)
d
Lf,conv dt iconv,q + RLf,conv iconv,q = −vconv,q + vCf ,q − Lf,conv ωg iconv,d
1684 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

Fig. 11. Block diagram of the control system.

Fig. 12. Converter current control loop including the processing and PWM
delays.

in order to design the parameters of the lead–lag compensator.

Consequently, the following lead–lag compensator is added to
Fig. 10. Flowchart of the proposed LCL filter design procedure to limit the
amplitude of grid current harmonics to a desired value for a defined control compensate the delay partially with unity gain for the funda-
reserve of k%. mental component of the capacitor voltage:

total delay of the current control loop is approximated by 1 + 1.5Ts s

GLead−Lag = . (37)
1 + 1.5αTs s
1
Gdelay,total = . (33)
1 + 1.5sTs + 0.5s2 Ts2 A compromise must be achieved between compensation and
noise amplification to design the position of the lead–lag pole
The following compensator should be applied to achieve an (α < 1). Fig. 13 shows the bode plots of the ideal compensator
ideal decoupled system: (1 + 1.5sTs ) as well as the lead–lag compensator with two
different values of α = 4/3π and α = 2/3π if the lead–lag
Gcompensator = 1 + 1.5sTs + 0.5s2 Ts2 . (34)
pole position is considered to be at switching and sampling
Applying this compensator leads to the amplification of noise frequencies in a regular asymmetric PWM modulation. It can be
and harmonics around the switching frequency. In order to seen in Fig. 13 that the smaller α leads to a better compensation
avoid the noise amplification problem, a lead–lag compensator but more noise amplification. The next sections will show
with limited amplification of high frequencies is applied simulation and experimental results of the influence of different
compensator designs on the dynamic behavior of the current
1 + Td s control loop.
GLead−Lag = kll , α < 1. (35)
1 + αTd s
A part of the delay can be compensated using the lead–lag V. S IMULATION R ESULTS
compensator [20], [21]. The total delay of the current control
The entire system comprising grid, LCL filter, an ideal
loop is approximated by
2L VSC, and the control system is simulated in MATLAB/
1 SIMULINK in order to verify the performance of the con-
Gdelay,total ≈ (36)
1 + 1.5sTs trollers and the effectiveness of the designed LCL filters
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1685

which was assumed in the filter design procedure. The main

reason is the difference between the grid and the converter
currents caused by the filter capacitors. Furthermore, the grid
voltage angle, which is required for the transformations, cannot
be measured exactly in a discrete control system. By using a
proper set point of iq , the grid reactive power is adjusted to zero
in the presented simulation results in Table VI. Both grid and
the converter currents and the corresponding harmonic spectra
are shown in Fig. 14. It can be seen in Fig. 14 that the appli-
cation of a higher filter resonance frequency leads to a lower
amplitude of the converter current harmonics. However, the
filter voltage drop increases because of the higher value of the
total filter inductance. Consequently, the dc-link voltage reserve
is reduced. The amplitude of the converter current harmonics,
as well as the control reserve for both filters with S-PWM, is
Fig. 13. Bode diagram of the compensators with various parameters
and the approximated ideal compensator: 1 + 1.5Ts s, Lead–Lag1 = (1 +
presented in Table VII. Applying (27), the maximum converter
1.5Ts s)/(1 + 1.5α1 Ts s), α1 = 4/3π, Lead–Lag2 = (1 + 1.5Ts s)/(1 + current ripples are 24.3% and 13.7% of the rated grid current
1.5α2 Ts s), α2 = 2/3π. for the filter with resonance frequencies of 1016 and 1350 Hz,
respectively. The performance of the current control loop is
TABLE VI
SIMULATION RESULTS FOR THE AMPLITUDE OF THE GRID CURRENT also investigated for the designed filters. As shown in Fig. 11,
HARMONICS FOR TWO SETS OF THE LCL FILTER the converter current is measured and controlled by applying
the capacitor voltages for decoupling and active damping. The
parameters of the current controllers are designed according to
(32). A lead–lag compensator with two different designs (α =
4/3π, α = 2/3π) is applied to investigate the current control
loop. The simulation results for a reference step of 100 A on
the q-axis are shown in Fig. 15(a) and (b) for a filter with
resonance frequencies of 1030 and 1350 Hz, respectively. It is
remarkable that the current control loop is stable even without
compensation. The application of the lead–lag compensator
leads to a faster step response and lower current overshoot
particularly for the filter with the higher resonance frequency.
following the presented procedure. The sampling and switching
The resonance frequency is far from the corner frequency of
frequencies are 8.1 and 4.05 kHz, respectively.
the current control loop in that case. As shown in Fig. 15,
The other parameters were chosen according to Table I.
applying the lead–lag with stronger compensation leads to a
In order to compare the filter effectiveness and performance,
better current step response but can cause noise amplification
two sets of filter components were designed by applying the
in the implementation.
flowchart in Fig. 7. The first design variant is the LCL filter
with minimum energy for Ig,1 = 70 A, Vll,g = 400 V, and
Vdc = 700 V, as presented in Table IV. The second variant was VI. E XPERIMENTAL R ESULTS
determined for a unity split factor r and a resonance frequency The effectiveness of the designed LCL filters and the dy-
fres = 1350 Hz larger than the resonance frequency of the filter namic characteristics of the current control loop are verified by
with minimum stored energy. experimental investigations. A 400 V induction machine drive
1) Lf,g,t = 0.703 mH (0.067 pu), Lf,conv = 0.711 mH on the basis of the parameters presented in Table I is applied.
(0.068 pu), Cf = 69.418 μF (0.072 pu), and fres = The LCL filter parameters and component values are chosen to
1016 Hz. be similar to the parameters and values of the simulated filters.
2) Lf,g,t = 1.379 mH (0.132 pu), Lf,conv = 1.379 mH 1) Lf,g = 0.6 mH (0.057 pu), Lf,conv = 0.6 mH (0.057 pu),
(0.132 pu), Cf = 20.153 μF (0.021 pu), and fres = Cf = 88 μF (0.091 pu), and fres = 980 Hz.
1350 Hz. 2) Lf,g = 1.2 mH (0.114 pu), Lf,conv = 1.2 mH (0.114 pu),
The amplitude of the (mf − 2)th grid current harmonic is 0.2% Cf = 22 μF (0.023 pu), and fres = 1385 Hz.
of the amplitude of the fundamental component of the grid The filter capacitance has tolerance within ±5%. Furthermore,
current for both filters. The simulation results of the main a tolerance of −10% to −15% is specified for the filter induc-
harmonics of the first carrier band are depicted in Table VI. tance at the switching frequency of 4 kHz according to achieved
Assuming an S-PWM, the amplitude of the most significant measurements.
current harmonic for both filters is around the desired value of The grid and the converter currents and the corresponding
0.2% with an acceptable error. spectra for both filters are shown in Fig. 16. The amplitude of
A VOC-led active rectifier based on the control of the con- the fundamental component of the grid current is 100 A. The
verter currents does not operate exactly at unity power factor, grid line-to-line voltage and the dc-link voltage are 400 and
1686 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

Fig. 14. Grid and converter currents and the corresponding harmonic spectra. (a) Lf,conv = 0.711 mH, Lf,g = 0.703 mH, Cf = 69.418 μF, fres = 1016 Hz,
(b) Lf,conv = 1.33 mH, Lf,g = 1.33 mH, Cf = 20.92 μF, fres = 1350 Hz. (a-1) and (b-1) The grid and the converter currents. (a-2) and (b-2) The
corresponding harmonic spectra.

TABLE VII
SIMULATION RESULTS FOR THE AMPLITUDE OF THE CONVERTER
CURRENT HARMONICS AND THE CONTROL RESERVE FOR
TWO SETS OF THE LCL FILTER

700 V, respectively. The filter capacitor voltages without

lead–lag compensator are used in the VOC and the active damp-
ing. The low-order harmonics of the grid voltage leads to a
distorted grid current with low-order harmonics (5th, 7th, . . .),
as can be seen in Fig. 16 (a-1) and (b-1) [31]–[33].
The influences of the line voltage distortion on the grid
current are stronger in the case of the filter with the lower
resonance frequency because of the lower filter total induc- Fig. 15. Current controller performance. (a) Lf,conv = 0.711 mH, Lf,g =
tance. The amplitudes of major grid current harmonics of the 0.703 mH, Cf = 69.418 μF, fres = 1016 Hz. (b) Lf,conv = 1.33 mH,
Lf,g = 1.33 mH, Cf = 20.92 μF, fres = 1350 Hz. 1: AD without com-
first carrier band are presented in Table VIII for simulation pensator, 2: AD with lead–lag compensator and α = 4/3π, and 3: AD with
and measurement. A current monitor with a sensitivity of lead–lag compensator and α = 2/3π.
0.1 V/A +1/ − 0% is used to measure the current harmonics.
The fundamental grid current component is filtered by applying
a fourth-order Butterworth high-pass filter to enable preciseness values. The simulation results are summarized in Table IX, and
of the current harmonic measurement. The main reason of the it can be seen that the simulation results are comparable to the
difference between the simulation and experimental results is experimental results given in Table VIII. The drawbacks of the
the tolerance of the filter component values at the switching reactive component value deflection can be counterbalanced by
frequency. The active rectifier with LCL filter and a −10% choosing a proper desired amplitude of the (mf − 2)th grid cur-
deviation of the component values given in Table VIII is sim- rent harmonic Iˆg,(mf −2),desired,% or applying filter components
ulated to investigate the effects of the variation of component with appropriate values regarding the eventual variations.
JALILI AND BERNET: DESIGN OF LCL FILTERS OF ACTIVE-FRONT-END TWO-LEVEL VSCs 1687

Fig. 16. Experimental results for the grid and the converter currents and the corresponding harmonic spectra for S-PWM. (a) Lf,conv = 0.6 mH, Lf,g =
0.6 mH, Cf = 88 μF, fres = 980 Hz: (a-1) The grid and the converter currents and (a-2) the harmonic spectra of the grid and the converter currents.
(b) Lf,conv = 1.2 mH, Lf,g = 1.2 mH, Cf = 22 μF, fres = 1385 Hz: (b-1) The grid and the converter currents and (b-2) the corresponding harmonic spectra.

TABLE VIII
SIMULATION AND EXPERIMENTAL RESULTS FOR THE AMPLITUDE OF THE GRID CURRENT HARMONICS FOR TWO SETS OF LCL FILTERS

TABLE IX The control system is stable without compensator as described

SIMULATION RESULTS FOR −10% DEVIATION OF THE FILTER
COMPONENT VALUES FOR THE LCL FILTERS PRESENTED IN TABLE VIII in Section IV. The lead–lag compensator leads to a faster step
response with lower overshoot particularly if the resonance
frequency is far from the corner frequency of the current
controller. The current control loop features a rise time of about
1.5 ms and an overshoot of 20% for both filters if there is no
compensator in the active damping loop.

VII. C ONCLUSION
This paper has proposed an iterative procedure to design L
and LCL filters for active rectifiers. The analytical expression
The experimental results for the step response of the current of the converter voltage harmonics based on Bessel functions
control loop are shown in Fig. 17. The performance of the is applied to determine the filter parameters which enable suffi-
current controller for a step of 100 A on the q-axis for the filters cient damping of the grid current harmonics (e.g., according to
with 980 and 1385 Hz as resonance frequencies is shown in IEEE-519-1992).
Fig. 17(a) and (b), respectively. The capacitor voltage feedback The LCL filter is modeled as L filter. The analytical expres-
is considered to be without compensator for waveform 1, with sion of the amplitude of the significant grid current harmonics
a lead–lag compensator and α = 4/3π for waveform 2, and at nominal load and unity power factor is presented. It is
with a lead–lag compensator and α = 2/3π for waveform 3. shown that LCL filters with different parameters (fres , r) and
1688 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 5, MAY 2009

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[28] M. Malinowski and S. Bernet, “A simple voltage sensorless active damp- Steffen Bernet (M’97) received the Diploma de-
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Kamran Jalili received the B.Sc. degree in power

engineering from the Power and Water Institute of
Technology, Tehran, Iran, in 1997, the M.Sc. de-
gree in control engineering from Tehran Univer-
sity, Tehran, in 2000, and the Ph.D. degree, holding
a DAAD scholarship, from Dresden University of
Technology, Dresden, Germany, in 2009.
From 2000 to 2003, he was a Research Associate
with the R&D Center of Iran Khodro Co. Currently,
he is with Converteam, Berlin, Germany. His fields
of interest include power electronics, electrical ma-
chines and drives, passive and active filters, and digital control of power
converters.