By Madhu:

213. Based on what we will place the macros?

A. Hierarchy, macro to macro communication, macro to IO communication and guidelines.

214. If macros are placed at the center, what are the problems we get?
A. Congestion, net lengths will be more due to detouring, timing issues, IR drop.

215. How will you give spacing between macros?

A. Spacing = (no. of pins * pitch of routing layer)/no. of available layers in the preferred direction

216. To avoid congestion in between macros, what are the cares we take?
A. proper channel spacing should be provided between macro to macro and the halo should be provided around the macro,
there should not be crisscrossing between macro to macro.

217. What are the types of blockages?

A. placement blockages:
1. Hard blockage: It will not allow any cells inside the blockage.
2. Soft blockage: It will not allow std cell but it will allow buffers and inverters during optimization.
3. Partial blockage: It will allow only certain specified percentage of cells.
Routing blockage: It will allow only some specified metal layers inside the blockage.

218. If we place soft blockage in between the macros it will allow the buffers and inverters, in that, then how will the
power will get to that cells?
A. Stripe should be added to get the power to those cells.

219. What are all the targets after power plan?

A. Checks after power planning:
1. Connectivity should be verified.
2. Any open, floating or dangling nets in the design.

220. Inputs of placement?

A. Design database upto power plan, lib, sdc, scandef

221. What are contents in SDC?

A. Sdc: clock definitions: create clock, create generate clock, virtual clock
Input delay
Output delay
DRVs: max tran, max cap, max fanout
Timing exceptions: false path, multicycle path, max delay, min delay

222. What is multicycle path and false path?

A. The combinational data path between two flip-flops can take more than one clock cycle to propagate through the
logic. In such cases, the combinational path is declared as a multicycle path.

Some certain timing paths are not real (or not possible) in the actual functional operation of the design. Such paths can
be turned off during STA by setting these as false paths. A false path is ignored by the STA for analysis.

223. At the placement stage what are all the different types of congestion you see? And how you overcome that
congestion
in your design?
A. 1. Using hard blockages in case of congestion due to notches.
 2. Using partial blockage, in case of high cell density.
3. Using cell padding, in case of congestion due to pin density.

224. Explain different techniques to overcome the congestion?

A. same as above

225. At placement stage, if we have the utilization of 95%, can we move forward and why?
A. No, we should not proceed with that utilization. We have to check the reason for the jump in the utilization number.

226. What are the timing checks we do after placement?

A. DRVs and setup checks

227. If the design had violated by 500ps of setup then will you move forward and why?
A. No, we have to fix the setup violation. If we proceed at this stage by the next stage the setup will be violated more there
may
not be chance to fix.

228. What are inputs of CTS?

A. placement database, sdc, lib, spec.

229. What exactly the spec will contain?

A. Clock grouping,
Through pin,
Exclude pin,
Clocks,
Period,
Sink pin,
Min. delay,
Max. delay,
Min. skew,
Clock buffers and inverters,
Routing layers,
NDRs

230. What is the use of clock groups in the spec file?

A. clock groups that are mutually exclusive or asynchronous with each other in a design so that the paths between these
clocks
are not considered during the timing analysis.

231. What are the targets of CTS?

A. balanced skew and minimum insertion delay.

232. What is the skew?

A. Skew is the difference in timing between two or more signals, maybe data, clock or both. Clock skew is the difference in
arrival times at the end points of the clock tree. Clock latency is the total time it takes from the clock source to an end
point.
Skew is the difference between capture flop latency and launch flop latency.

233. Explain setup and hold with equation.

A. Setup: The minimum time before the active clock when the data input must remain stable is called the setup time.
Setup time = Required Time - Arrival Time
Required time = Clock period + capture clock latency – lib setup – setup uncertainity
Arrival time = launch clock latency + C to Q delay + combo delay

Hold: The minimum time the data input must remain stable just after the active edge of the clock.
Hold time = Arrival Time – Required Time
Required time = Capture clock latency – lib setup – setup uncertainity
Arrival time = launch clock latency + C to Q delay + combo delay
234. If launch clock is 20ns and capture clock is 10ns then where do we check the setup and hold? and vice versa?
A.

235. How to fix the setup and hold violations?

A. setup:
upsizing,
Vt swapping (HVT to LVT)
Pushing capture flop (adding delay)
Pulling launch flop(reducing delay)
Hold:
downsizing
 Vt swapping (LVT to HVT)
Pulling capture flop (reducing delay)
Pushing launch flop (adding delay)
Buffering for net delays

236. What is the resistor, capacitor and current formulae?

A. Capacitance, C = ∈ 𝐴/𝑑,
Where, ∈ is the permittivity, A is area and d is distance.
Resistance, R = ρl/A,
Where, ρ is resistivity, l is length and A is area.
Current, I = V/R,
Where, V is voltage and R is resistance.

237. What is antenna violation? On what basis antenna violation will affect the cell.
A. It is also called “Plasma induced gate effect damage”. It will occur at manufacturing stage. It is a gate damage that can
occur due to charge accumulation on metals and discharge to a gate through gate oxide. These are normally expressed
as an allowable ratio of metal area to gate area greater than allowable area.

238. What is cloning?

A.

239. On what tool and technology, you have worked? Have you ever seen PT and calibre tools?

241. What happens if we have setup and hold violations in our design?
A. setup and hold timings are to be met in order to ensure that data launched from one flop is captured properly at
another and in
accordance to the state machine designed. In other words, no timing violations means that the data launched by one
flip-flop at one clock edge is getting captured by another flip-flop at the desired clock edge. If the setup check is
violated, data will not be captured properly at the next clock edge. Similarly, if hold check is violated, data intended to
get captured at the next edge will get captured at the same edge. Moreover, setup/hold violations can lead to data
getting captured within the setup/hold window which can lead to metastability of the capturing flip-flop. So, it is very
important to have setup and hold requirements met for all the registers in the design and there should not be any
setup/hold violations.

242. What will you do if your design has setup violation and how will you meet setup in such cases where there are
no
margins available?
A. We can meet the setup violations by adding buffers and downsizing the buffers present in the clock path.

243. What is time borrowing?

A. The time borrowing technique, which is also called cycle stealing, occurs at a latch. In a latch, one edge of the clock
makes
the latch transparent, that is, it opens the latch so that output of the latch is the same as the data input; this clock edge
is called the opening edge. The second edge of the clock closes the latch, that is, any change on the data input is no
longer available at the output of the latch; this clock edge is called the closing edge.
244. What are the concepts involved in STA?
A. modeling of cells, propagation delay, slew of waveform, skew between signals, Timing arcs, Timing paths, Clock
domains,
Operating conditions.

245. What is signal integrity?

A. The ability of the signal to with stand the interference from the nearby signal.

246. What is aggressor net? Why it’s called aggressor net?

A. The net in which high switching activity is performed is aggressor. It is the affecting net so that it is called as aggressor
net.

247. Both nets are having same drive strength, but voltage is different, capacitance is occurred or not?
A. yes, the capacitance occurs due to different voltage levels.

248. Both nets are having same voltage, but voltage is same, capacitance is occurred or not?
A. No, the capacitance does not occur because the voltage levels are same.

249. Both nets having same voltage capacitance is occurred or not?

A. No

250. What is cross coupling capacitance? Why it occurs?

A. The capacitance formed between two different nets in which one of the net is having high switching activity and other
net is
containing low level signal. The capacitance is formed because of different voltage levels in the nets and different
switching.

251. What is dielectric? Do know dielectric formula?

A. A dielectric (or dielectric material) is an electrical insulator that can be polarized by an applied electric field. When a
dielectric is placed in an electric field, electric charges do not flow through the material as they do in an electrical
conductor but only slightly shift from their average equilibrium positions causing dielectric polarization. Because
of dielectric polarization, positive charges are displaced in the direction of the field and negative charges shift in the
opposite direction.

Dielectric constant, κ = C/C0

Where, C is value of the capacitance of a capacitor filled with a given dielectric
C0 is the capacitance of an identical capacitor in a vacuum

253. What is cross talk? Explain in detail.

A. The interference of the high switching signal on the low level signal due to the formation of coupling capacitor between
the
nets. The net in which high switching activity is there and affecting the idle net is called aggressor net. The net which is
having low switching activity and affected by aggressor is called victim net.
When aggressor net is switching and victim net is idle, we may get cross talk noise.
When aggressor net and victim net both are switching, we may get cross talk delay.

254. How to avoid crosstalk?

A. Applying NDRs, downsizing aggressor, upsizing victim, shielding victim net.

257. What is data path?

A. The path between Q pin of the launch flop and D pin of the capture flop is called data path.

258. What is OCV?

A. The process and environmental conditions may not be uniform across the different portions of the chip. Due to process
variations, identical transistors may not have similar characteristics in different portions of the chip.

259. What is process?

A. Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness)
 when integrated circuits are fabricated. The amount of process variation becomes particularly pronounced at smaller
process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the device and as
feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for
patterning lithography masks.

260. Explain the corners.

A. Parasitics can be extracted at many corners. These are mostly governed by the variations in the metal width and metal
etch in
the manufacturing process. Some of these are:
• Typical: This refers to the nominal values for interconnect resistance and capacitance.
• Max C: This refers to the interconnect corner which results in maximum capacitance. The interconnect resistance is
smaller
than at typical corner. This corner results in largest delay for paths with short nets and can be used for max path
analysis.
• Min C: This refers to the interconnect corner which results in minimum capacitance. The interconnect resistance is
larger
than at typical corner. This corner results in smallest delay for paths with short nets and can be used for min path
analysis.
• Max RC: This refers to the interconnect corner which maximizes the interconnect RC product. This typically
corresponds to
larger etch which reduces the trace width. This results in largest resistance but corresponds to smaller than typical
capacitance. Overall, this corner has the largest delay for paths with long interconnects and can be used for max path
analysis.
• Min RC: This refers to the interconnect corner which minimizes the interconnect RC product. This typically
corresponds to
smaller etch which increases the trace width. This results in smallest resistance but corresponds to larger than
typical capacitance. Overall, this corner has the smallest path delay for paths with long interconnects and can be
used for min path analysis.
By Nandini:

262. Tell me about STA?

Ans: It is a method of validating the timing performance of the design by checking all
possible paths for timing violations under worstcase conditions.

Read lib
Read netlist
(Link the design and check any unresolved references and black box)
Read SDC
(check_timing(we should not get any unconstrained end points; clock
notfound; No drive Assertion))
Read spef
(report_annotated parasitics)
Report timing
(we need to generate timing reports for all variable paths in the design)
Analysis
(After generating the reports we should analyse all the slack, setup, hold
values)

263. Tell me about PD?

Ans: A. Inputs for PD are

1. lib (timing, functionality, power)
2. lef (physical info)
3. v (logical connectivity)
4. sdc (clock definitions)
5. cpf/upf (consists of power domain info)
6. cap table (RC values for every net)
B. Sanity checks
a)Library sanity checks (physical and logical library)
1. Missing cells and pins
2. Mismatched pins
3. Duplicate cell name
b)Design sanity checks (checkNetlist)
1. Floating pins
2. Combinational loops
3. Assign statements
4. Tristate buffers
5. Empty modules
6. Multi Driven nets
c) Constraint sanity checks
1. All flops are clocked or not
2. No unconstrained path
3. Input and Output delays
 • Floorplan (defining core and die area based on Aspect ratio and Utilization factor and
placing macros physical cells )
• Power Plan (supplying power from Pads to the Design)
• Placement (finding the appropriate location of the std cells)
• Place opt (to meeting area congestion and timing [setup])
• CTS (Distributing clock from clock port to clock pin)
• opt CTS (balancing skew and latency also DRC's to meet the timing[setup, hold])
• Routing (Connecting components physically and finding optimized net length with
introduced net delays)
• opt Routing (Assigning the track for every net and fixing the timings )
• Signoff (meeting the all requirements timing, functionality, power, area and DRC.)
264. Inputs of STA?
Ans: 1. Lib
2. netlist
3. sdc
4. Spef
265. Inputs of PD?
Ans: Technology Related inputs:
1. .lib
2. Lef
3. captables
Design Related inputs:
1. .v
2. SDC
3. CPF
266. What is Setup? How you fix setup?

Ans: The time taken by the data to be stable before the clock edge called Setup.

How to fix setup :

1. Upsizing the cell.

2. Vt swapping.
3. Pulling the launch.
4. Pushing the capture.

267. what is hold? How u fix hold?

Ans: The time taken by the data to be stable before the clock edge called hold.

How to fix hold:

1. Downsizing the cell.

2. Vt swapping.
3. Pulling the capture.
4. Pushing the launch.
5. Inserting the buffer in the data path.

271. What is BlackBox?

Ans: It consists of input and output but we cannot see the inside functionality.

272. What are the commands using entire pd flow?

Ans:

FloorPlan:

1. floorPlan -site CoreSite -r 1 0.698983 1.0 1.14 1.0 1.0

2. editPin -fixedPin 1 -fixOverlap 1 -unit MICRON -spreadDirection
clockwise -side Top -layer 4 -spreadType start -spacing 0.4 -start 4.337
750.8455 -pin {pin names}
3. addHaloToBlock 1 1 1 1 -allBlock
4. addEndCap -preCap FILL2 -postCap FILL2 -prefix ENDCAP
5. addWellTap -cell FILL8 -cellInterval 40 -fixedGap -prefix WELLTAP
PowerPlan:
1. for global net connection
globalNetConnect VDD -type pgpin -pin VDD -inst *
globalNetConnect VSS -type pgpin -pin VSS -inst *
globalNetConnect VDD -type tiehi -pin VDD -inst *
globalNetConnect VSS -type tielo -pin VSS -inst *
Placement:
1. placeDesign
2. for hard blockage (createPlaceBlockage -box <area> )
3. softblockage (createDensityArea <area> <percentage>)
4. placeDesign -incremental
5. optDesign -preCTS
CTS:
1. clockDesign
2. optDesign -postCTS
Routing:
1. RouteDesign
2. optDesign -postRoute
273. what are the commands using CTS level?

Ans: 1. clockDesign

2. optdesign-postCTS

3. report_timing

4. report_constraints –all _violators

274. Tell me ten ways to fix Setup and hold?

Ans: To fix SETUP:

1. Upsizing the cell.

 2.Vt Swapping.

3. Pulling the launch.

4. Pushing the capture.

5. Logical Restructuring.

6. Pin Swapping.

7.Cloning.

8. If net delay dominates the cell delay :

Break the net and adding buffers.

To fix HOLD:

1. Downsize the cell

2. Vt Swapping
3. Pulling the capture
4. Pushing the launch
5. Insert the buffer in the data path

276. What is OCV and AOCV?

Ans: : OCV:

Minor changes in delays due to the variations in PVT conditions.As cell delays
are varying we will apply a global derating factor then every cell having min and max delay.
All the cells are applying with same derating factor.

AOCV:

Here we r applying a derating factor based on logical depth and distance.OCV is

more pessimistic than AOCV so we r going for AOCV.

277. Create Clock Command?

Ans: create_clock -name top – period 10 -waveform (0 5) –get_ports[scan clk]

278. What is Dutycycle?

Ans: A duty cycle is the fraction of one period in which a signal or system is active known as
Duty cycle.

Duty cycle = (Ton/Ton+Toff)*100

275. What is PVT?

Ans: PVT- Process Voltage Temperature

 Best case: fast process, highest voltage and lowest temperature

 Worst case: slow process, lowest voltage and highest temperature

 Normal case: normal process, normal voltage, normal temperature

279. Make a waveform 30./. dutycycle?

Ans:

280. How many spef files used in your project?

Ans: 6 spef files

281. Cell Delay Vs VTH?

Ans: If temperatute increases mobility decreases and Vth decreases.

If temperature decreases mobility increases and Vth increases.

In lower technologies temperature decreases delay increases because it depends on threshold

voltage.

I
Because of Drain current i.e., d is inversely proportional to Vth if vth increases Id
decreases then process is slow then delay also increases.

282. which is being used currently AOCV or POCV?

Ans: POCV [Parametric On Chip Variation]:

It uses a statistical approach, it calculates delay variation by modeling the intrinsic cell delay
and parasitic of load which determines sigma and mean of a logic stage.

283. Draw a clock waveform. What is the time period of a clock with 1GHZ frequency?
Ans:

284.What is netlist? What it contains?

Ans: Logical connectivity information between combinational and sequential cells known as
Netlist. It contains 1. Module information

2. Hierarichal information

3. Input Output Notations

4. port information
 5. Instance and net names

285. What .lib contains?

Ans: It contains

1. Power Information

2. Timing Information

3. cell Functionality

4. PVT

286. Where will the data get launched and captured?

Ans:

290. What is Setup Equation?

Ans: SETUP:

R.T – A.T
R.T = Clkperiod+Capture clock latency-lib.setup time-uncertainity

A.T= Launch Clock latency+ Clk-Q delay+ combinational path

HOLD:

A.T - R.T

A.T = Launch Clock latency+ Clk-Q delay+ combinational path

R.T= Capture clock latency+lib.hold time+hold uncertainity

291. If setup checks and hold checks not done what happened? If it necessary why?

Ans: Timing doesn’t meet if we do not do setup and hold check.

292. Why NMOS is Called NMOS?

Ans: N-type metal-oxide-semiconductor logic uses N type field effect transistors

MOSFETs to implement logic gates and other digital circuits. These NMOS transistors
operate by creating an inversion layer in a p-type transistor body. This inversion layer, called
the n-channel, can conduct electrons between n-type "source" and "drain" terminals. The n-
channel is created by applying voltage to the third terminal, called the gate.

293. What is NMOS and PMOS ?

Ans: NMOS: N-type metal oxide semiconductor

A NMOS transistor is made up of n-type source and drain and a p-type substrate.
When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away
from the gate. This allows forming an n-type channel between the source and the drain and a
current is carried by electrons from source to the drain through an induced n-type channel.

PMOS: P-type Metal oxide Semiconductor

A PMOS transistor is made up of p-type source and drain and a n-type substrate.
When a positive voltage is applied between the source and the gate (negative voltage between
gate and source) a p-type channel is formed between the source and the drain with opposite
polarities. A current is carried by holes from source to the drain through an induced p-type
channel. A high voltage on the gate will cause a PMOS not to conduct, while a low voltage
on the gate will cause it to conduct .

294. What is MOSFET? Draw the MOSFET Diagram?

Ans: MOSFET: Metal Oxide Semiconductor

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET,

or MOS FET) is a type of field-effect transistor (FET), most commonly fabricated by
the controlled oxidation of silicon. It has an insulated gate, whose voltage determines the
conductivity of the device. This ability to change conductivity with the amount of applied
voltage can be used for amplifying or switching electronic signals.

295. What is Transistor?

Ans: Transfer of Resistance

A transistor is a semiconductor device used to amplify or switch electronic signals

and electrical power. It is composed of semiconductor material usually with at least
three terminals for connection to an external circuit .
296. What is Inverter? Explain in Cmos Inverter logic?

Ans: It is an electronic device which changes Direct current to Alternating current.

297. What is buffer explanation in CMOS logic?

Ans:

By interchanging the positions of the NMOS and PMOS transistors in the NOT circuit can
give a Buffer and this technique uses only two transistors.

(OR)
A BUF gate is essentially constructed from two NOT gates connected in series

298. What is the function of AND,NAND,NOT?

Ans: AND: A*B

NAND: AB Bar

NOT : A Bar

299. What are opens and shots? How u fix?

Ans: Opens: Different metals with same name known as Opens.

How to fix opens:

1. Stretching the metal layers.

2. Metal jogging

Shorts: Same metal with different name known as shorts.

How to fix shorts:

1. Metal shorts:
Metal Jogging (or) change the metal layers.
2. Via shorts:
Changes the vias.

300. What is FV?

Ans: FV (Or) LEC:

It checks the functionality of the netlists

LEC Flow :

Read lib

Read golden netlist

Read revised netlist

Mapping(Names are mapping here)

Comparing

302. What kind of errors u seen in LEC?

Ans: 1. Unmapped names

303. What is Congestion? If congestion is there what happened?

Ans: Available tracks are less than Required tracks known as Congestion.

1. First we need to do set uniform density then also if we observe congestion

2. If Global congestion is there:

• The congestion which is occurring at every g-cell in the design is called global
congestion
• Due to this global congestion we are facing the improper routing (it will generate
opens)
• This is mainly occurred due to improper placement of macros and bad floor plan
To reduce the global congestion change the core size(increase area) and fixing the proper
placement area for std cells.

3. If there are notches congestion there is a possibility to apply hard blockage.

4. If there is more cell density at particular stage we r applying partial blockage and also
cell padding.

304. What is CrossTalk?Explain CrossTalk?

Ans: The voltage transition from one net to another net through coupling capacitor known as
Crosstalk.

There are two types:

1. Crosstalk Noise
2. Crosstalk Delay

Crosstalk Noise:
 If aggressor switches victim is constant known as Crosstalk noise.

If bump is above 50% it goes to metastable state(or) functionality failure.

Crosstalk Delay:

If aggressor and victim both in same direction delay decreases.

If aggressor and victim both in opposite direction delay increases.

305. What is Coupling Capacitor?

Ans:

A coupling capacitor is a capacitor which is used to couple or link together only the AC
signal from one circuit element to another. The capacitor blocks the DC signal from entering
the second element and, thus, only passes the AC signal.
306. Capacitance Formula? Explain in detail?

Ans: It is a passive element that has ability to store the charge in the form of potential
difference between plates known as capacitor.

Effect of capacitor is called capacitance.

/
C= permitivitty of dielectric* Area of plate overlap in sq.mt Distance between 2
plates

307. Tell me the manufacture process of metals?

Ans: Metal Manufacturing Processes: Production

1. CASTING
Depending on the metal and its purpose, the metal may simply be melted down and molded to
shape. This process is known as casting. Casting is best for small or intricate parts. Casting
SHOULD NOT be used for products that require high strength, high ductility, or tight
tolerances.

Dies, jewelery, plaques, and machine components all benefit from this simple production process.

2. POWDER PROCESSING

Powder processing treats powdered metals with pressure (pressing) and heat (sintering) to form
different shapes. Powdered metallurgy is known for its precision and output quality -- it keeps tight
tolerances and often requires no secondary fabrications.

However, it's incredibly costly and generally only used for small, complex parts. Powder
processing is NOT appropriate for high-strength applications.

3. FORMING

Metal forming takes a raw metal (usually in sheet metal form) and mechanically manipulates it into a
desired shape. Unlike casting, metal forming allows for higher strength, ductility, and
workability for additional fabrications.

Metal Manufacturing Processes: Fabrication

1. DEFORMATION

Deformation includes bending, rolling, forging, and drawing.

2. MACHINING

Machining refers to any fabrication method that removes a section of the metal. Machining is also
known as material removal processing. Cutting, shearing, punching, and stamping are all
common types of machining fabrication.

When planning for machining in your supply chain, hardening processes should happen AFTER
machining processes. Hardened metals have a high shear strength and are more difficult to cut.

3. JOINING

Joining, or assembly, is one of the last steps of the metal manufacturing process. This category
includes welding, brazing, bolting, and adhesives. Assembly can be done by machine or by hand.

4. FINISHING

Depending on your material and application, you may also need finishing services. Finishing includes
everything from galvanization to powder coating, and can take place throughout the manufacturing
process.

308. Why metals are placed in horizontal and vertical fasion?

Ans: At routing stage if we place metals in horizontal and vertical manner it leads to metals lays
exactly on tracks.

309. What is CTS? Explain CTS?

Ans: Before CTS we need to check:

1. All cells should be legalized.

2. All power nets are prerouted.
3. All pins should legalized.
4. Congestion, timing should control.
GOALS OF CTS :
1. To minimize the logical DRCs.
2. Balancing the skew.
3. Minimum Insertion Delay.
INPUTS OF CTS:
1. SDC
2. SPEC FILE
3. PLACEMENT DATABASE
WHAT IS CTS ?:
To distribute a clock from Clockport to Clockpin
WHY CTS?:
To minimize skew and insertion delay to build the clock tree.
Here we are generating SPEC file using clock buffers and clock inverters.
SPEC file consists of
1. Buffers list
2. Max skew
3. Min and Max Insertion delay
4. Max trans, Cap, Fanout
5. Inverters list
6. Clock tree leaf pin, exclude pin, stop pin
7. Clock name
8. Clock period
COMMANDS USED IN CTS:
clockdesign
optDesign -postCTS
CHECKS IN CTS:
1. Timing numbers
2. Utilization numbers
3. Congestion
4. All cells should legalize

311. What is CD in shell command?

Ans: change directory

312. how you make a directorie?

Ans: makedirectory(mkdir)
313. Tell me the command for directory with in a directory?
Ans: mkdir dir1