This document discusses various topics related to physical design and clock tree synthesis (CTS) in integrated circuit design. It covers CTS tree types, cell types used, constraints, metal layer allocation, pros and cons of different CTS schemes, non-default routing rules, CTS inputs and checks, factors in determining minimum and maximum insertion delays, and techniques for fixing timing violations. The document provides detailed explanations on several important aspects of CTS to help prepare for interviews.
This document discusses various topics related to physical design and clock tree synthesis (CTS) in integrated circuit design. It covers CTS tree types, cell types used, constraints, metal layer allocation, pros and cons of different CTS schemes, non-default routing rules, CTS inputs and checks, factors in determining minimum and maximum insertion delays, and techniques for fixing timing violations. The document provides detailed explanations on several important aspects of CTS to help prepare for interviews.
This document discusses various topics related to physical design and clock tree synthesis (CTS) in integrated circuit design. It covers CTS tree types, cell types used, constraints, metal layer allocation, pros and cons of different CTS schemes, non-default routing rules, CTS inputs and checks, factors in determining minimum and maximum insertion delays, and techniques for fixing timing violations. The document provides detailed explanations on several important aspects of CTS to help prepare for interviews.
This document discusses various topics related to physical design and clock tree synthesis (CTS) in integrated circuit design. It covers CTS tree types, cell types used, constraints, metal layer allocation, pros and cons of different CTS schemes, non-default routing rules, CTS inputs and checks, factors in determining minimum and maximum insertion delays, and techniques for fixing timing violations. The document provides detailed explanations on several important aspects of CTS to help prepare for interviews.
INTERVIEW PREPSRATION BY ABHAY KUMAR @VLSIGURU, Physical Design - CTS
CTS Experiments:
1. Type of CTS tree
a. Default b. H tree c. Clock mesh 2. Type of cells a. Buffers b. Inverters c. Mixed (buffer + inverters) i. Trunk : buffers & Leaf: inverters ii. Trunk : inverter & leaf : buffer 3. Different CTS constraints: a. Stop_pin b. Non_stop_pin c. Don’t_touch_subtree 4. Build CTS to 3-4 macros which are getting driven from same source. 5. Disadvantage of clock gating a. Having extra check for timing b. More design time for closure 6. Metal Layer allocation in design a. Top: i. Power to carry more current b. Middle: i. For clock network c. Bottom : i. Uniform Distribution of power to STD cells 7. Pros and Cons of CTS scheme a. Mesh: i. More routing resource ii. Robust for design variation b. H tree: i. Balance CTS ii. More branches, more area, more power 8. Pros and cons of NDR Pros: Xtalk (glitch, delay) , net delay will be lesser for more width , EM with more width Report_timing -crosstalk_delay -net -input This will show the total net delay on input pin of each cell This delay component is total of net delay and Xtalk delay By using “-crosstalk_delay” option, it will print xtlak delay separately. Cons: Congestion, extra route length 9. Which is the type of design where H tree failed? a. Designs using useful SKEW 10. Why is mixing of VT types are not allowed in CTS? a. Design variation are different for each VT type 11. Max Transition analysis a. Check the driver,
ii. reason: non-buffer element => insert buffer the driving pin iii. reason: long wire length => insert buffer to break the net length as per buffer driving capability. 12. Why are metal layers taller in lower technology? a. After reduction in width resistance gets increased with the same multiplier. To reduce the resistance on metal layer, it needs to increase the cross-sectional area. With is fixed for the give technology so metal height need to increase for this. 13. CGC vios fixing techniques: a. Automatically in TOOL: i. Use usefulSKew by adding float pin constraints on all the startpoint of the violating CGC. Apply the usefulSkew as per the violation value. 14. Checks a. All cells are legally placed, macro are already checked before placement b. TILE : comes from Tech File c. Design is divided into placement grid based on SITE/TILE d. SITE_7T, SITE_8T,SITE_12T, HD, HP e. Performance : HP, 12T cells at the cost of power and area f. Area: HD, 7T at the cost of performance g. Area with high performance design: 12T as performance is the main target h. Target to battery operated device : 7T, HD i. Target to battery operated device with high performance: 7T at the cost of higher area j. Xbar architecture: maximum utilization for these arch are below 50%. These arch are net dominating k. Cell dominating and net dominating l. Starting utilization is depends on Architecture and given shape m. Timing i. WNS (worst negative slack) ii. TNS ( Total negative slack) iii. FEP (failing endpoints) n. Timing and congestion are going to degrade in further stage i. Main reason for this is routing estimation at placement o. Why is timing BAD at CTS? i. Routing estimation ii. Timing estimation (clock SKEW, in uncertainty of clocks) iii. Placement level clock uncertainty : Jitter (fixed)+ SKEW (fixed) + distortion on clock path (fixed) iv. CTS level clock uncertainty : Jitter (fixed)+ SKEW (depends on path) + distortion on clock path (depends on nos of levels, cells used) p. Congestion 15. CTS Inputs: a. DB completed all placement checks b. CTS target c. CTS constraints d. CTS cells e. CTS NDR f. CTS exceptions 16. CHECKS after CTS
b. Cells used as per input given c. Transition time on clock path d. SKEW e. Insertion delay f. Timing g. Congestion 17. Targets a. SOC level insertion delay is hard requirement to meet (WIFI chip max insertion delay 5ns) b. Balance clocks only for the blocks communicating c. Clock transition is hard limit to meet for block i. Sequential cell delay ii. Tsetup and Thold requirement of the flop iii. Lesser short ckt current iv. For sharper trans time : bigger cells will be used which will consume more switching power v. For sharper trans time : More number of levels 18. How to decide on minimum insertion delay of block? a. Communication to other blocks b. It is must to decide and apply in design 19. How to decide the maximum insertion delay of block? a. SKEW 20. What is the impact if insertion delay of the memory and macro not defined during CTS? a. MEM2REG paths for setup timing b. REG2MEM paths for hold timing 21. Why is there a guidelines for flops, keeping outside channels? a. NDR , which is consuming more routing tracks , it was not accounting in placement congestion estimation b. Solution to this is “EARLY CLOCK” flow. This is used in lower technology which gives correct estimation of routing tracks requirement and STD cells area. c. Another solutions : reserve some percentage of tracks for each layer, impact the timing of design 22. Why is clock transition better than data transition? a. Xtalk b. Better skew c. Lesser short ckt current 23. Why are clock nets have extra spacing? a. To avoid Xtalk on data nets 24. Factor in deciding the clock gating cell placement a. Timing , start from register which is generating the enable signal and ending at clock gater (ICG or CGC) b. CGC are placed during placement stage c. Clock path delays are ZERO at placement stage d. Data path delay will decide the clock gating placement 25. NDR , non default routing rules a. Any change in default routing rule (minSpace, minWidth) , is called NDR b. WIDTH:
i. EM (electro migration) ii. Low resiatance c. Spacing: i. XTALK to data nets ii. Only in specific condition where data net transition is faster than clock net, it may create XTALK on clock, Spacing is helping in reducing this XTALK. 26. Why is XTALK so important in design? a. It effect hold and setup together as the polarity of XTALK is not fixed. b. Setup path delay will increase with XTALK effect c. Hold path delay will reduce with XTALK at the same time. d. By fixing XTALK , it fixed the setup and hold path at the same time. 27. Why is spacing preferred over shielding of clock nets? a. Shielding adds extra ground cap to clock nets which is increasing the load. b. Shielding also consume more routing resource. 28. Is shielding or spacing hard constraints or soft constraints for clock nets? a. This is soft constraints, tool will follow wherever space is available b. Typically in congested areas , these are not getting followed. c. Clock nets always has more than 70% nets NDR honoured 29. Why is shielding percentage reduced at post_route stage compare to CTS stage? a. Difference between Routing estimation to actual routes b. More areas become congested, so the NDR reduced in design. c. STEPS: i. Shielding is removed ii. Actual routing of signal nets completed iii. Shielding will be re-applied wherever it is possible. 30. Select the cells required for CTS a. Main clock tree b. Size_only c. Delay insertion 31. Select the NDR a. Main tree b. Leaf branch 32. Constraints 33. Layer selection for CTS 34. Why is no NDR on sink pin routing? a. Congestion 35. Debug steps for hold fixing: a. Review the list of cells given for hold fixing b. Check that cells should be available (should not have dont_use attribute to 1) c. Check the command to make these cells available for hold (set_prefer –min) d. Check the hold corner is available 36. Fixing timing on clock gating vios: a. Fixing on data path b. Reduce clock insertion delay on startpoint (useful Skew / floatpin) 37. Command to report all vios to clock_gater
a. DONE at post_cts (fixed vios upto -0.020) + post_route fix all vios (preferred) b. DONE at post_route only 39. Macro Model: a. Having clock, from IO port (macro pin) to registers inside macro. i. Required during CTS build (min and max insertion delay) b. Transition and load information of all macro pins i. Required for macro clock port during CTS build ii. For other macro ports, these info required for correct timing computation c. RISE, FALL, MIN, MAX : capacitance should be defined for all 4 case d. Insertion delay : usually given in LIB/.DB e. If not defined: timing violations will be seen when macro is become flat during STA. f. Should block level insertion delay be higher than macro insertion delay? 40. CTS Build STEPs a. Trace b. Deletion c. Buffer insertion as per Trans limit, tool maintain the more common path d. Skew balance based on highest delay path 41. Global SKEW: a. Maximum insertion delay – minimum insertion delay 42. Local SKEW: a. Difference of clock path delay for the registers having valid timing path 43. CTS Checks: a. DRV (max_Transition, max_capacitance, fanout) b. SKEW ( local and Global) c. Timing (setup and Hold) d. Clock quality e. Power 44. Basic of clock gating: a. What is clock gating b. What is the CKT at Synth which translate to clock gating c. How many gates dynamic power is saved for one clock gating ckt? d. How many gates dynamic power is saved if one clock gater is used for all 100 similar Synth loop CKT with mux at INPUT D. e. Explain clock gating assertion and de assertion in terms of timing for Integrated clock gating cell with latch which is negative level sensitive. 45. Clock_gating vios: a. Clock gater always be at capture side, it cannot launch data to any flops. i. Timing paths always be “TO clock gater” b. What are the basic problems with clock gating vios i. SKEW (launch clock path delay – capture clock path delay) : where launch register is having higher clock path delay than clock gating cell. c. Solutions:
1. Reduce the clock path delay of all launch register as per their timing violation. Use Float pin on all these startpoint CLK pin with positive value of the violation 2. Use below commands 3. get_timing_paths ii. ENDPOINT BASED fixing 1. Endpoints are lesser in count 2. Margin needs to be there from the register getting driven by clock gater
