Ec3352 - DSD Lab Manual

FORMAT: QP10 EC 3352 – Digital Systems Design Laboratory
CONTENTS
MARKS
S.NO DATE TITLE OF THE EXPERIMENT PAGE SIGN
(10)
CYCLE-I
1. Study of basic Logic Gates 02
(i) Design and implementation of Half

Adderr & Full Adder using logic gates. 08
2. (a)
(ii) Design and implementation of Half
Subtractor & Full Subtractor using logic 11
gates.
Design and implementation of code
converters using logic gates
(i) Binary code to Gray
code converter
(ii) Gray code to Binary
(b) 15
code converter
(iii) BCD to Excess-3 code
converter
(iv) Excess-3 to BCD code
converter
Design and implementation of
3. Multiplexer and De-multiplexer using IC74150 24
and IC 74154
Design and implementation of Encoder
4. 29
and Decoder
Design and implementation of 2 Bit

5. 37
Magnitude Comparator using IC 7485
Design and implementation of Synchronous
6. 42
counters.
Implementation of SISO, SIPO, PISO and
7. 46
PIPO shift registers using Flip- flops
Kings College of Engineering Page No.1

STAFF INCHARGE HOD / ECE
EXPT.NO.1
STUDY OF LOGIC GATES
AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
S. No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1

THEORY:
7. X-NOR GATE IC 74266 1
Digital systems are said
to be 8. NAND GATE 3 I/P IC 7410 1 constructed by
using logic gates. These
gates are the 9. IC TRAINER KIT - 1 AND, OR, NOT,
NAND, NOR, EXOR and
EXNOR gates. 10. PATCH CORD - 14 Each gate has
one or more input and only
one output. The NAND and
NOR gates are called universal functions.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The AND
gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is
used to show the AND operation i.e. A.B.

OR GATE:
The OR gate performs a logical addition commonly known as OR function. The OR gate is
an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is
used to show the OR operation.
NOT GATE:
The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as
NOT A. This is also shown as A', or A with a bar over the top.
NAND GATE:
This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs
of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.
NOR GATE:
This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of
all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on
the output. The small circle represents inversion.
EX-OR GATE:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its
two inputs are high. An encircled plus sign ( ) is used to show the EX-OR operation.
EX-NOR GATE:
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if
either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output.
The small circle represents inversion.
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:

OR GATE:
NOT GATE:

2-INPUT NAND GATE:
3-INPUT NAND GATE:

NOR GATE:
EX-OR GATE:

EX-NOR GATE:
RESULT:
Thus the logic gates are studied and their truth tables were verified.

VIVA VOCE QUESTIONS:

1. What is a gate?
2. What are universal gates?
3. Implement AND gate using NAND gate.
4. What is the difference between 74 series and 54 series?
5. Give the IC No. of AND, OR, NOT, NAND NOR & EX-OR Gate.
EXPT.NO.2a
HALF ADDER AND FULL ADDER
AIM:
To design and construct half adder and full adder circuits and to verify the truth table using
logic gates.
APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY.
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23
THEORY:

HALF ADDER:
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry
(C). The carry signal represents an over flow into the next digit of a multi-digit addition. The value
of the sum is 2C + S. The simplest half-adder design, given below, incorporates an XOR gate for sum
(S) and an AND gate for carry (C). The half adder adds two input bits and generates a carry and
sum, which are the two outputs of a half adder. The input variables of a half adder are called the
augend and addend bits. The output variables are the sum and carry.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A one-bit full adder adds three one-bit numbers, often written as A, B,
and C ; A and B are the operands, and C is a bit carried in from the previous less-significant stage. A
full adder can be constructed from two half adders by connecting A and B to the input of one half
adder, connecting the sum from that to an input to the second adder, connecting C to the other
input and OR the two carry outputs. The critical path of a full adder runs through both XOR-gates
and ends at the sum bit.
HALF ADDER
LOGIC DIAGRAM:

FULL ADDER
LOGIC DIAGRAM: (FULL ADDER USING TWO HALF ADDER)
TRUTH TABLE:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
K-Map for SUM: K-Map for CARRY:

PROCEDURE:
(i) The connections are made as per the circuit diagram.

RESULT:
Thus the half adder & full adder logic circuits were constructed and designed and their truth
tables were also verified.
1. Draw circuit diagram of Half Adder circuit.
2. Draw circuit diagram of Full Adder circuit.
3. Draw Full Adder circuit by using Half Adder circuit and minimum no. of logic gate.
4. Write the Boolean function for half adder and Full adder.
5. Write the Boolean function for half subtractor and Full subtractor.
EXPT.NO.2a
HALF SUBTRACTOR AND FULL SUBTRACTOR
AIM:
To design and construct, half sub tractor and full subtractor circuits and verify the truth
table using logic gates.
APPARATUS REQUIRED:

4. PATCH CORDS - 23
THEORY:
HALF SUBTRACTOR:
Half Subtractor is a combinational circuit that performs subtraction of two bits and has two
inputs and two outputs. The two inputs denoted by A and B represents minuend and subtrahend.
The two outputs are the difference “D” and the borrow bit “B”. The half subtractor is constructed
using X-OR and AND Gate. The Difference can be obtained using X-OR Gate, Borrow output can be
implemented using an AND Gate and an inverter.
FULL SUBTRACTOR:
Full Subtractor is a combinational circuit that performs subtraction of three bits and has
three inputs and two outputs. The minuend ‘A’ , subtrahend ‘B’ and borrow in ‘C’. The full
subtractor generates two output bits: difference “D” and the borrow out “Bout” . The full subtractor
is a combination of X-OR, AND, OR & NOT Gates. The two half subtractor put together gives a full
subtractor.
HALF SUBTRACTOR

LOGIC DIAGRAM:
TRUTH TABLE: K-Map for DIFFERENCE: K-Map for BORROW:
FULL SUBTRACTOR
LOGIC DIAGRAM:
TRUTH TABLE:

A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-Map for Difference: K-Map for Borrow:
Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C
PROCEDURE:
RESULT:
Thus the half subtractor & full subtractor logic circuits were constructed and designed and
their truth tables were also verified.

1. Draw the circuit diagram of Half Subtractor circuit.
2. Draw the circuit diagram of Full Subtractor circuit.
3. Define Half subtractor.
4. Write the Boolean function for half Subtractor.
5. Write the Boolean function for Full Subtractor.

EXPT.NO.2b
CODE CONVERTOR
AIM:
To design and implement the following 4 bit code converters using logic gates.
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
APPARATUS REQUIRED:
6. PATCH CORDS - 35
THEORY:
Binary to gray code converter and vice versa.

The logical circuit which converts binary code to equivalent gray code is known as binary
to gray code converter. The gray code is a non weighted code. The successive gray code differs in
one bit position only that means it is a unit distance code. It is also referred as cyclic code. It is not
suitable for arithmetic operations. It is the most popular of the unit distance codes. It is also a
reflective code.
The input variable are designated as B3, B2, B1, B0 and the output variables are designated
as G3, G2, G1, G0 and vice versa. From the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable. A two-level logic diagram
may be obtained directly from the Boolean expressions derived by the k-maps.
BCD to excess-3 code converter and vice versa:

Binary coded decimal (BCD) is a system of writing numerals that assigns a four-digit binary
code to each digit 0 through 9 in a decimal (base-10) numeral. The four-bit BCD code for any
particular single base-10 digit is its representation in binary notation, as follows: 0 = 0000, 1 =
0001 .. Numbers larger than 9, having two or more digits in the decimal system, are expressed digit
by digit.
The Excess-3 code is an important BCD code , It is a 4 bit code and used with BCD numbers.
To convert any decimal numbers into its excess- 3 form ,add 3 to each decimal digit and then
convert the sum to a BCD number. As weights are not assigned, it is a kind of non weighted codes.
The input variable are designated as B3, B2, B1, B0 and the output variables are designated
as E3, E2, E1, E0 and vice versa. From the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable. A two-level logic diagram
may be obtained directly from the Boolean expressions derived by the k-maps.

BINARY TO GRAY CODE CONVERTOR
TRUTH TABLE:

K-Map for G3: K-Map for G2:
G 3 = B3
K-Map for G1:
K-Map for G0:

LOGIC DIAGRAM:
GRAY CODE TO BINARY CODE CONVERTOR
TRUTH TABLE:
GRAY CODE BINARY CODE
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-Map for B3: K-Map for B2:
B3 = G3
K-Map for B1: K-Map for B0:
LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE:
BCD CODE EXCESS-3 CODE
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
K-Map for E3: K-Map for E2:

E3 = B3 + B2 (B0 + B1)
K-Map for E1: K-Map for E0:
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR
TRUTH TABLE:
EXCESS-3 CODE BCD CODE
X1 X2 X3 X4 A B C D
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
K-Map for A: K-Map for B:
A = X1 X2 + X3 X4 X1
K-Map for C: K-Map for D:
LOGIC DIAGRAM:

PROCEDURE:
(ii) Logical inputs were given as per the truth table.
(iii) Observe the logical output and verify with the truth tables.
RESULT:
Thus the 4-bit Binary to gray code converter, Gray to binary code converter, BCD to excess-
3 code converter & Excess-3 to BCD code converter were designed, implemented and their truth
tables were also verified.
1. What are the applications of code convertors?
2. What are code converters?

3. What are BCD codes?
4. Define excess 3 codes.
5. Define gray code.
EXPT.NO.03
MULTIPLEXER AND DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic gates and study of IC
74150 and IC 74154.
APPARATUS REQUIRED:
1. 3 I/P AND GATE IC 7411 2
3. PATCH CORDS - 32
THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number
of channels or lines. A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a particular input

line is controlled by a set of selection lines. Normally there are 2 n input line and n selection lines
whose bit combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information

from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass through the
selected gate to the associated data output line.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXERS:

FUNCTION TABLE:
S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0
LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0

1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
PIN DIAGRAM FOR IC 74150: PIN DIAGRAM FOR IC 74154:
PROCEDURE:

RESULT:
Thus the multiplexer and demultiplexer were designed and implemented using logic gates and
truth tables were also verified.
1. What is meant by multiplexer?
2. How many 4x1 multiplexers are needed to construct 16x1 multiplexer?
3. Design a full adder using 8x1 multiplexer?
4. Role of Mux in digital Circuit?
5. List out the applications of multiplexer and demultiplexer?
EXPT.NO.04
ENCODER AND DECODER
AIM:
To design and implement encoder and decoder using logic gates and study of IC 74150 and
IC 74154.
APPARATUS REQUIRED:

3. PATCH CORDS - 32
THEORY:
DECODER:
A decoder is a logic circuit that will detect the presence of a specific binary number or word.
The input to the decoder is a parallel binary number and the output is a binary signal that indicates
the presence or absence of that specific number. It is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique output lines.
ENCODER:
The combinational circuits that change the binary information into N output lines are known
as Encoders. The binary information is passed in the form of 2N input lines. The output lines
define the N-bit code for the binary information. In simple words, the Encoder performs the
reverse operation of the Decoder. At a time, only one input line is activated for simplicity. The
produced N-bit output code is equivalent to the binary information.
BLOCK DIAGRAM FOR DECODER:

2 TO 4 LINE DECODER:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and four outputs, i.e.,
Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are given below.
BLOCK DIAGRAM:
TRUTH TABLE:
Enabl
INPUTS OUTPUTS
e
E A1 A0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
The logical expression of the term Y0, Y1, Y2 and Y3is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
CIRCUIT DIAGRAM FOR DECODER:

3 TO 8 LINE DECODER:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there is
a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. This
circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these
four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given
below.
Block Diagram:
TRUTH TABLE:

Enable INPUTS OUTPUTS

E A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2' Y1=A0.A1'.A2' Y2=A0'.A1.A2' Y3=A0.A1.A2'
Y4=A0'.A1'.A2 Y5=A0.A1'.A2 Y6=A0'.A1.A2 Y7=A0.A1.A2
CIRCUIT DIAGRAM FOR DECODER:
BLOCK DIAGRAM FOR ENCODER:

4 TO 2 LINE ENCODER:
In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and two outputs, i.e.,
A0 and A1. In 4-input lines, one input-line is set to true at a time to get the respective binary code in
the output side. Below are the block diagram and the truth table of the 4 to 2 line encoder.
BLOCK DIAGRAM:
TRUTH TABLE:
INPUTS OUTPUTS
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
The logical expression of the term A0 & A1are as follows:
A1=Y3+Y2
A0=Y3+Y1
CIRCUIT DIAGRAM FOR ENCODER:

8 TO 3 LINE ENCODER:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there is a
total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. In 8-
input lines, one input-line is set to true at a time to get the respective binary code in the output
side. Below are the block diagram and the truth table of the 8 to 3 line encoder.
BLOCK DIAGRAM:
TRUTH TABLE:
INPUTS INPUTS
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1
CIRCUIT DIAGRAM FOR ENCODER:
PROCEDURE:
(iv) The connections are made as per the circuit diagram.
(v) Logical inputs are given as per circuit diagram.
(vi) Observe the output and verify the truth table.
RESULT:
Thus the Encoder and Decoder were designed and implemented using logic gates and truth tables
were also verified.

1. What is meant by Encoder?
2. How many inputs and outputs will a decimal-to-BCD encoder have?
3. How is an encoder different from a decoder?
4. How many OR gates are required for an octal-to-binary encoder?
5. For 8-bit input encoder how many combinations are possible?
EXPT.NO.5

MAGNITUDE COMPARATOR
AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 8 – bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
4-BIT MAGNITUDE
5. IC 7485 2
COMPARATOR
7. PATCH CORDS - 30
THEORY:
A magnitude comparator is a combinational circuit that compares two numbers A and B and
determines their relative magnitude. The comparison of two numbers is an operator that
determines one number is greater than, less than (or) equal to the other number. The outcome of
the comparator is specified by three binary variables that indicates whether A>B, A<B (or) A=B.
A = A3 A2 A1 A0, B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit designated by
the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant
digits starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
🡳 🡳 🡳 🡳
x3 x2 x1 x0
2 BIT MAGNITUDE COMPARATOR
TRUTH TABLE
A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
K MAP SIMPLIFICATION:

A=B

LOGIC DIAGRAM:
PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR
TRUTH TABLE:
PROCEDURE:

RESULT:
Thus the design and implementation of 2 – bit magnitude comparator using basic gates and
truth table was verified.
VIVA VOCE QUESTIONS
1. What is a magnitude comparator?
2. What is the logic symbol for 4 bit comparator with inequality indication?
3. A=10112 and B= 10102 are applied to the operand inputs of 7485. Determine the
output.
4. How many 4-bit comparators are needed to construct 12-bit comparator?
5. What does a digital comparator mean?

EXPT.NO.6
SYNCHRONOUS COUNTER DESIGN
3 BIT SYNCHRONOUS UP/DOWN COUNTER
AIM:
To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
4. XOR GATE IC 7486 1
7. PATCH CORDS - 35
THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable
of progressing in increasing order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of the counter is controlled
by up/down signal. When this signal is high counter goes through up sequence and when up/down
signal is low counter follows reverse sequence.
STATE DIAGRAM:

TRUTH TABLE:
Input Present State Next State A B C

Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
K MAP SIMPLIFICATION:

EXCITATION TABLE:
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
LOGIC DIAGRAM:

PROCEDURE:
RESULT:
Thus the 3-bit synchronous counter was designed and the truth table was verified.
1. What is a sequential circuit?
2. What is a latch?
3. Differentiate between synchronous and asynchronous counter.
4. What is propagation delay?
5. What is Johnson counter?
EXPT.NO.7
SHIFT REGISTERS
AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out
APPARATUS REQUIRED:
1. D FLIP FLOP IC 7474 2
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output
of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which
causes the shift in the output of the flip flop. The simplest possible shift register is one that uses
only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register.
Each clock pulse shifts the content of register one bit position to right.
PIN DIAGRAM:
SERIAL IN SERIAL OUT:

LOGIC DIAGRAM:
TRUTH TABLE:
CLK Serial in Serial out
1 1 0

2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
SERIAL IN PARALLEL OUT:

LOGIC DIAGRAM:
TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
PARALLEL IN SERIAL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
PARALLEL IN PARALLEL OUT:

LOGIC DIAGRAM:

TRUTH TABLE:
DATA INPUT OUTPUT

CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:
RESULT:
Thus the design and implementation of Serial in serial out, Serial in parallel out, Parallel in
serial out, Parallel in parallel out and truth was verified.
1. What is a register?

2. Differentiate latch & flip flop.
3. What is edge & level triggering?
4. What is the need of D- flip flop?
5. What is bi directional register?

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FORMAT: QP10 EC 3352 – Digital Systems Design Laboratory

(i) Design and implementation of Half

Design and implementation of 2 Bit

Kings College of Engineering Page No.1

STAFF INCHARGE HOD / ECE

S. No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

3. NOT GATE IC 7404 1

4. NAND GATE 2 I/P IC 7400 1

5. NOR GATE IC 7402 1

6. X-OR GATE IC 7486 1

Kings College of Engineering Page No.2

(i) Connections are given as per circuit diagram.

Kings College of Engineering Page No.3

Kings College of Engineering Page No.4

2-INPUT NAND GATE:

3-INPUT NAND GATE:

Kings College of Engineering Page No.5

Kings College of Engineering Page No.6

Kings College of Engineering Page No.7

VIVA VOCE QUESTIONS:

2. What are universal gates?

3. Implement AND gate using NAND gate.

4. What is the difference between 74 series and 54 series?

1. AND GATE IC 7408 1

2. X-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

Kings College of Engineering Page No.8

Kings College of Engineering Page No.9

LOGIC DIAGRAM: (FULL ADDER USING TWO HALF ADDER)

K-Map for SUM: K-Map for CARRY:

Kings College of Engineering Page No.10

(i) The connections are made as per the circuit diagram.

VIVA VOCE QUESTIONS:

1. Draw circuit diagram of Half Adder circuit.

2. Draw circuit diagram of Full Adder circuit.

S.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1

2. X-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

Kings College of Engineering Page No.12

TRUTH TABLE: K-Map for DIFFERENCE: K-Map for BORROW:

Kings College of Engineering Page No.13

K-Map for Difference: K-Map for Borrow:

Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C

(i) The connections are made as per the circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

VIVA VOCE QUESTIONS:

Kings College of Engineering Page No.14

1. Draw the circuit diagram of Half Subtractor circuit.

2. Draw the circuit diagram of Full Subtractor circuit.

3. Define Half subtractor.

4. Write the Boolean function for half Subtractor.

5. Write the Boolean function for Full Subtractor.

Kings College of Engineering Page No.15

S.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1