Low Power Mixer/Limiter/RSSI

3 V Receiver IF Subsystem
AD608
FEATURES The RF and local oscillator (LO) bandwidths both exceed
Mixer 500 MHz. In a typical IF application, the AD608 can accept the
−15 dBm, 1 dB compression point output of a 240 MHz surface acoustic wave (SAW) filter and down-
−5 dBm IP3 convert it to a nominal 10.7 MHz IF with a conversion gain of
24 dB conversion gain 24 dB (ZIF = 165 Ω). The AD608 logarithmic/limiting amplifier
>500 MHz input bandwidth section handles any IF from low frequency (LF) up to 30 MHz.
Logarithmic/limiting amplifier The mixer is a doubly balanced gilbert-cell mixer and operates
80 dB RSSI range linearly for RF inputs spanning −95 dBm to −15 dBm. It has a
±3° phase stability over 80 dB range nominal −5 dBm third-order intercept. An on-board LO pre-
Low power amplifier requires only −16 dBm of LO drive. The current output
21 mW at 3 V power consumption of the mixer drives a reverse-terminated, industry-standard
CMOS-compatible power-down to 300 μW typical 10.7 MHz, 330 Ω filter.
200 ns enable/disable time
The nominal logarithmic scaling is such that the output is +0.2 V
APPLICATIONS for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V
PHS, GSM, TDMA, FM, or PM receivers at an input of +5 dBm; over this range, the logarithmic confor-
Battery-powered instrumentation mance is typically ±1 dB. The logarithmic slope is proportional
Base station RSSI measurements to the supply voltage. A feedback loop automatically nulls the
input offset of the first stage down to the submicrovolt level.
The AD608 limiter output provides a hard-limited signal output
GENERAL DESCRIPTION
at 400 mV p-p. The voltage gain of the limiting amplifier to this
The AD608 provides a low power, low distortion, low noise mixer output is more than 100 dB. Transition times are 11 ns and the
as well as a complete, monolithic logarithmic/limiting amplifier phase is stable to within ±3° at 10.7 MHz for signals from −75 dBm
that uses a successive-detection technique. In addition, the AD608 to +5 dBm.
provides both a high speed received signal strength indicator
The AD608 is enabled by a CMOS logic-level voltage input,
(RSSI) output with 80 dB dynamic range and a hard-limited
with a response time of 200 ns. When disabled, the standby
output. The RSSI output is from a two-pole postdemodulation
power is reduced to 300 μW within 400 ns.
low-pass filter and provides a loadable output voltage of 0.2 V to
1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply The AD608 is specified for the industrial temperature range of
at a typical power level of 21 mW at 3 V. −25°C to +85°C for 2.7 V to 5.5 V supplies and −40°C to +85°C for
3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC.

FUNCTIONAL BLOCK DIAGRAM

3dB NOMINAL 110dB LIMITER GAIN
24dB MIXER GAIN INSERTION LOSS 90dB RSSI

IF INPUT 7 FULL-WAVE RSSI RSSI OUTPUT

±6mA MAX OUTPUT 11 20mV/dB
(±890mV INTO 165Ω) –75dBm TO RECTIFIER CELLS
+15dBm2 0.2V TO 1.8V
RFHI 5 2MHz
LPF COM3 12
RF INPUT MIXER 10.7MHz IFHI
MXOP BAND-PASS VPS2
–95dBm TO 7 9 14 +2.7V TO 5.5V
–15dBm 1 FILTER
BPF LMOP
DRIVER 330Ω 5-STAGE IF AMPLIFIER LIMITER
RFLO 6 330Ω (16dB PER STAGE)
15
OUTPUT
LO VMID 10nF 400mV p-p
FINAL
+

PREAMP 8 10
LIMITER
+ IFLO
100nF 100Ω
MIDSUPPLY
IF BIAS
13
+

18nF FDBK ±50µA

BIAS
AD608
VPS1 COM1 LOHI COM2 PRUP
1 2 3 4 16

2.7V TO LO INPUT CMOS LOGIC

5.5V –16dBm INPUT
07886-001

1–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.

239.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.

Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1996–2009 Analog Devices, Inc. All rights reserved.
AD608

TABLE OF CONTENTS
Features .............................................................................................. 1 Mixer ...............................................................................................9
Applications ....................................................................................... 1 Mixer Gain .....................................................................................9
General Description ......................................................................... 1 IF Filter Terminations ................................................................ 10
Functional Block Diagram .............................................................. 1 The Logarithmic IF Amplifier .................................................. 10
Revision History ............................................................................... 2 Offset Feedback Loop ................................................................ 10
Specifications..................................................................................... 3 RSSI Output ................................................................................ 11
Absolute Maximum Ratings............................................................ 4 Digitizing the RSSI ..................................................................... 11
Thermal Resistance ...................................................................... 4 Power Consumption .................................................................. 11
ESD Caution .................................................................................. 4 Troubleshooting.......................................................................... 11
Pin Configuration and Function Descriptions ............................. 5 Applications Information .............................................................. 12
Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 13
Test Circuits ....................................................................................... 8 Ordering Guide .......................................................................... 13
Theory of Operation ........................................................................ 9

REVISION HISTORY
2/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Reorganized Layout ............................................................ Universal
Change to General Description Section ........................................ 1
Changes to DC Level Parameter, Operating Range Parameter,
and TMIN to TMAX Parameter, Table 1 .......................................... 3
Added Typical Performance Characteristics Heading ................ 6
Added Test Circuits Heading .......................................................... 8
Changes to Figure 17 and Figure 19 ............................................... 8
Change to Figure 22 ......................................................................... 9
Changes to Table 5 ............................................................................ 9
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 13

Rev. C | Page 2 of 16
 AD608

SPECIFICATIONS
TA = 25°C, supply = 3 V, dBm is referred to 50 Ω, unless otherwise noted.

Table 1.
Parameter Conditions 1 Min Typ Max Unit
MIXER PERFORMANCE
RF and LO Frequency Range 500 MHz
LO Power Input terminated in 50 Ω −16 dBm
Conversion Gain Driving doubly terminated 330 Ω IF filter, ZIF = 165 Ω 19 24 28 dB
Noise Figure Matched input, fRF = 100 MHz 11 dB
Matched input, fRF = 240 MHz 16 dB
1 dB Compression Point Input terminated in 50 Ω −15 dBm
Third-Order Intercept fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz −5 dBm
Input Resistance fRF = 100 MHz (see Table 5) 1.9 kΩ
Input Capacitance fRF = 100 MHz (see Table 5) 3 pF
LIMITER PERFORMANCE
Gain Full temperature and supply range 110 dB
Limiting Threshold 3° rms phase jitter at 10.7 MHz −75 dBm
280 kHz IF bandwidth
Input Resistance 10 kΩ
Input Capacitance 3 pF
Phase Variation −75 dBm to +5 dBm IF input signal at 10.7 MHz ±3 Degrees
DC Level Center of output swing (VPOS – 1 V) 2 V
Output Level Limiter output driving 5 kΩ load 400 mV p-p
Rise and Fall Times Driving a 5 pF load 11 ns
Output Impedance 200 Ω
RSSI PERFORMANCE At 10.7 MHz
Nominal Slope At VPOS = 3 V; proportional to VPOS 17.27 20 23.27 mV/dB
Nominal Intercept −85 dBm
Minimum RSSI Voltage −75 dBm input signal 0.2 V
Maximum RSSI Voltage +5 dBm input signal 1.8 V
RSSI Voltage Intercept 0 dBm input signal 1.57 1.82 V
Logarithmic Linearity Error −75 dBm to +5 dBm input signal at IFHI ±1 dB
RSSI Response Time 90% RF to 50% RSSI 200 ns
Output Impedance At midscale 250 Ω
POWER-DOWN INTERFACE
Logic Threshold System active on logic high 1.5 V
Input Current For logic high 75 mA
Power-Up Response Time Active limiter output 200 ns
Power-Down Response Time To 200 μA supply current 400 ns
Power-Down Current 100 μA
POWER SUPPLY
Operating Range −25°C to +85°C 2.7 5.5 V
−40°C to +85°C 3.0 5.5 V
Powered Up Current VPOS = 3 V 7.3 mA
OPERATING TEMPERATURE
TMIN to TMAX VPOS = 2.7 V to 5.5 V −25 +85 °C
VPOS = 3.0 V to 5.5 V −40 +85 °C
1
VPOS is used to refer collectively to the VPS1 and VPS2 pins.

Rev. C | Page 3 of 16
AD608

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 2.
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Supply Voltages VPS1, VPS2 +6 V
Internal Power Dissipation 600 mW Table 3.
Temperature Range −40°C to +85°C Package Type θJA Unit
Storage Temperature Range −65°C to +150°C 16-Lead SOIC 110 °C/W
Lead Temperature (Soldering 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings ESD CAUTION
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. C | Page 4 of 16
 AD608

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPS1 1 16 PRUP
COM1 2 15 LMOP
LOHI 3 14 VPS2
AD608
COM2 4 TOP VIEW 13 FDBK
RFHI 5 (Not to Scale) 12 COM3
RFLO 6 11 RSSI
MXOP 7 10 IFLO

07886-002
VMID 8 9 IFHI

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 VPS1 1 Positive Supply Input
2 COM1 Common
3 LOHI Local Oscillator Input Connection
4 COM2 Common
5 RFHI RF Input, Noninverting
6 RFLO RF Input, Inverting
7 MXOP Mixer Output
8 VMID Midpoint Supply Bias Output
9 IFHI IF Input, Noninverting
10 IFLO IF Input, Inverting
11 RSSI Received Signal Strength Indicator Output
12 COM3 Output Common
13 FDBK Offset-Null Feedback Loop Output
14 VPS21 Limiter Positive Supply Input
15 LMOP Limiter Output
16 PRUP Power-Up
1
VPOS is used to refer collectively to the VPS1 and VPS2 pins in this data sheet.

Rev. C | Page 5 of 16
AD608

TYPICAL PERFORMANCE CHARACTERISTICS

25.0 3.0
+85°C
+25°C
–25°C
24.5 2.5
MIXER CONVERSION GAIN (dB)

24.0 2.0

RSSI OUTPUT (V)

23.5 1.5

23.0 1.0

22.5 0.5

22.0 0

07886-005

07886-008
0 50 100 150 200 250 300 350 400 450 500 –80 –70 –60 –50 –40 –30 –20 –10 0 10
RF FREQUENCY (MHz) INPUT POWER (dBm)

Figure 3. Mixer Conversion Gain vs. RF Frequency Figure 6. IF RSSI Output vs. Input Power and Temperature,
3 V Supply (See Figure 15)

0 4

–1 3

–2 2
MIXER RESPONSE (dB)

RSSI ERROR (dB)

–3 1
3V

–4 0
5V
–5 –1

–6 –2

–7 –3

–8 –4

07886-010
07886-006

0 10 20 30 40 50 60 70 80 –80 –70 –60 –50 –40 –30 –20 –10 0 10

IF FREQUENCY (MHz) INPUT POWER (dBm)

Figure 4. Mixer IF Port Bandwidth Figure 7. RSSI Error vs. Input Power
(See Figure 15)

3.0
800mV/DIV

2.5
RSSI

2.0
RSSI OUTPUT (V)

5V 100ns/DIV

1.5
1V/DIV

1.0
PRUP

3V
0.5
07886-011

100ns/DIV
0
07886-007

–80 –70 –60 –50 –40 –30 –20 –10 0 10

INPUT POWER AT IFHI (dBm)

Figure 5. IF RSSI Output vs. Input Power at IFHI and Supply Voltage, Figure 8. RSSI Power-Up Response
Ambient Temperature (See Figure 15) (See Figure 19)

Rev. C | Page 6 of 16
 AD608
5
200mV/DIV
4

3
IFHI

LIMITER PHASE (Degrees)

2

–1
RSSI

–2

–3

07886-013
–4
800mV/DIV 50ns/DIV
–5

07886-019
–80 –70 –60 –50 –40 –30 –20 –10 0 10
INPUT POWER AT IFHI (dBm)
Figure 9. RSSI Pulse Response/RSSI Rise Time Figure 12. Limiter Phase Performance vs. Input Power at IFHI
(See Figure 16) (See Figure 21)

10
60mV/DIV
9

LIMITER RMS JITTER (Degrees) 7

6
LMOP

2
07886-015

1
20ns/DIV
0

07886-021
–80 –70 –60 –50 –40 –30 –20 –10 0 10
INPUT POWER AT IFHI (dBm)

Figure 10. Limiter Rise and Fall Times Figure 13. Limiter RMS Jitter Performance vs. Input Power at IFHI
(See Figure 20) (See Figure 21)

220mV/DIV 100ns/DIV
LMOP

1V/DIV
PRUP

07886-017

100ns/DIV

Figure 11. Limiter Power-Up Response Time

(See Figure 17)

Rev. C | Page 7 of 16
AD608

TEST CIRCUITS
PRUP INPUT
U1A TRIGGER

U1B

4.7kΩ 47kΩ
1 VPS1 PRUP 16
VPOS 0.1µF
47kΩ 2 COM1 LMOP 15 NC
1nF 18nF
LO INPUT 3 LOHI VPS2 14
1 VPS1 PRUP 16 18nF
VPOS 0.1µF 51.1Ω 4 COM2
2 COM1 LMOP 15 LMOP OUTPUT FDBK 13
0.1µF 0.1µF 1nF
5 RFHI COM3 12
3 LOHI VPS2 14
RF INPUT 100Ω
51.1Ω 6 RFLO RSSI 11 NC
4 COM2 FDBK 13 51.1Ω 10nF
1nF 1nF
18nF 7 MXOP IFLO 10
5 RFHI COM3 12
1nF 100Ω
51.1Ω 8 VMID IFHI 9
6 RFLO RSSI 11 RSSI OUTPUT
10nF
332Ω
AD608
7 MXOP IFLO 10
332Ω 332Ω
8 VMID IFHI 9 0.1µF 0.1µF
AD608 0.1µF 301Ω
301Ω
IF OUTPUT
332Ω
IF INPUT
0.1µF 54.9Ω
54.9Ω

07886-004
07886-003

U1 – 74HC00 NC = NO CONNECT

Figure 14. IF Test Board Schematic Figure 18. Mixer Test Board Schematic
AGILENT
HP54120A
FLUKE 6082A TEKRONIX DIGITAL
IF TEST BOARD OSCILLOSCOPE
IF TEST BOARD DIGITAL SYNTHESIZER P6201
FLUKE 6082A MULTIMETER
SYNTHESIZER (DMM) IFHI RSSI FET CH 1
PROBE
IFHI RSSI DMM 10.7MHz PRUP CH 2
0dBm
10.7MHz VPOS AGILENT VPOS
HP34401A

DC POWER DCPS 3V
SUPPLY DCPS 3V

07886-012
07886-009

(DCPS) AGILENT
AGILENT HP3366A
HP3366A

Figure 15. Test Circuit for IF RSSI Output vs. Input Power at IFHI and Supply Figure 19. Test Circuit for RSSI Power-Up Response (Figure 8)
Voltage, Ambient Temperature (Figure 5); IF RSSI Output vs. Input Power and
Temperature, 3 V Supply (Figure 6); and RSSI Error vs. Input Power (Figure 7)

FLUKE 6082A IF TEST BOARD TEKRONIX AGILENT

CH 1 P6201 HP54120A
FLUKE 6082A IF TEST BOARD TEKRONIX SYNTHESIZER
SYNTHESIZER P6201 FET DIGITAL
IFHI LMOP
COUPLER IFHI RSSI FET CH 2 PROBE OSCILLOSCOPE
PROBE 10.7MHz
10.7MHz 0dBm VPOS
0dBm MCL VPOS
ZDC-20-1

AGILENT
DCPS 3V DCPS 3V
07886-014

HP54120A
07886-016

DIGITAL
AGILENT OSCILLOSCOPE AGILENT
HP3366A HP3366A

Figure 16. Test Circuit for RSSI Pulse Response/RSSI Rise Time (Figure 9) Figure 20. Test Circuit for Limiter Rise and Fall Times (Figure 10)

AGILENT FLUKE 6082A MCL TEKTRONIX

HP54120A SYNTHESIZER ZDC-20-1 IF TEST BOARD P6201
FLUKE 6082A TEKRONIX DIGITAL
IF TEST BOARD FET
SYNTHESIZER P6201 OSCILLOSCOPE COUPLER IFHI RSSI PROBE
AGILENT
FET 10.7MHz HP8447A
IFHI LMOP CH 1 AGILENT
PROBE
10.7MHz HP8494A
PRUP CH 2 HP8495A DCPS 3V BPF CH 1
0dBm
VPOS AGILENT 280kHz BW
HP3366A 10.7MHz CF
TRIG
DCPS 3V TOKO SK107MK1-A0-10
AGILENT
07886-018

07886-020

AGILENT HP54120A
HP3366A DIGITAL
OSCILLOSCOPE

Figure 17. Test Circuit for Limiter Power-Up Response Time (Figure 11) Figure 21. Test Circuit for Limiter Phase Performance vs. Input Power at IFHI
(Figure 12) and Limiter RMS Jitter Performance vs. Input Power at IFHI (Figure 13)

Rev. C | Page 8 of 16
 AD608

THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF MIXER GAIN
strip with RSSI and hard-limited outputs (see Figure 22). The conversion gain of the mixer is the product of its trans-
MIXER conductance and the impedance seen at Pin MXOP. For a 330 Ω
The mixer is a doubly balanced, modified gilbert-cell mixer. Its parallel-terminated filter at 10.7 MHz, the load impedance is
maximum input level for linear operation is either ±56.2 mV, 165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
regardless of the impedance across the mixer inputs, or −15 dBm ±891 mV) centered on the midpoint of the supply voltage. For
for a 50 Ω input termination. The input impedance of the mixer other load impedances, the expression for the gain in decibels is
can be modeled as a simple parallel RC network; the resistance GdB = 20 log10(0.0961 RL)
and capacitance values vs. frequency are listed in Table 5. The where:
bandwidth from the RF input to the IF output at the MXOP pin GdB is the gain in decibels.
is −1 dB at 30 MHz and then rapidly decreases as frequency RL is the load impedance at Pin MXOP.
increases (see Figure 4).
The gain of the mixer can be increased or decreased by changing
RL. The limitations on the gain are the ±6 mA maximum output
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply.

3dB NOMINAL 110dB LIMITER GAIN

24dB MIXER GAIN INSERTION LOSS 90dB RSSI

IF INPUT 7 FULL-WAVE RSSI RSSI OUTPUT

±6mA MAX OUTPUT 11 20mV/dB
(±890mV INTO 165Ω) –75dBm TO RECTIFIER CELLS
+15dBm 2 0.2V TO 1.8V
RFHI 5 2MHz
LPF COM3 12
RF INPUT MIXER 10.7MHz IFHI
MXOP BAND-PASS VPS2
–95dBm TO 7 9 14 2.7V TO 5.5V
–15dBm 1 FILTER
BPF LMOP
DRIVER 330Ω 5-STAGE IF AMPLIFIER LIMITER
RFLO 6 330Ω (16dB PER STAGE)
15
OUTPUT
LO VMID 10nF 400mV p-p
FINAL
+

PREAMP 8 10
LIMITER
+ IFLO
100nF
MIDSUPPLY 100Ω
IF BIAS
13
+

18nF FDBK
BIAS ±50µA
AD608
VPS1 COM1 LOHI COM2 PRUP
1 2 3 4 16

2.7V TO LO INPUT CMOS LOGIC

5.5V –16dBm INPUT

07886-022
1–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
239.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.

Figure 22. Functional Block Diagram

Table 5. Mixer Input Impedance vs. Frequency

Frequency (MHz) Resistance (Ω) Capacitance (pF)
45 2800 3.1
70 2600 3.1
100 1900 3.0
200 1200 3.1
300 760 3.2
400 520 3.4
500 330 3.6

Rev. C | Page 9 of 16
AD608
IF FILTER TERMINATIONS limiter output drive is ± 200 mV (400 mV p-p) into a 5 kΩ load.
The AD608 was designed to drive a parallel-terminated 10.7 MHz In the absence of an input signal, the limiter output limits noise
band-pass filter (BPF) with a 330 Ω impedance. With a 330 Ω fluctuations, producing an output that continues to swing
parallel-terminated filter, Pin MXOP sees a 165 Ω termination, 400 mV p-p, but with random zero crossings.
and the gain is nominally 24 dB. Other filter impedances and OFFSET FEEDBACK LOOP
gains can be accommodated by either accepting an increase or Because the logarithmic amplifier is dc-coupled and has more
decrease in gain in proportion to the filter impedance or by than 110 dB of gain from the input to the limiter output, a dc
keeping the impedance seen by MXOP at a nominal 165 Ω (by offset at its input of even a few microvolts causes the output to
using resistive dividers or matching networks). Figure 23 shows a saturate. Therefore, the AD608 uses a low frequency feedback
simple resistive voltage divider for matching an assortment of loop to null the input offset. Referring to Figure 23, the loop
filter impedances, and Table 6 lists component values. consists of a current source driven by the limiter, which sends
THE LOGARITHMIC IF AMPLIFIER 50 μA current pulses to Pin FDBK. The pulses are low-pass filtered
The logarithmic IF amplifier consists of five amplifier stages by a π-network consisting of C1, R4, and C5. The smoothed dc
of 16 dB gain each, plus a final limiter. The IF bandwidth is voltage that results is subtracted from the input to the IF amplifier
30 MHz (−1 dB), and the limiting gain is 110 dB. The phase at Pin IFLO. Because this is a high gain amplifier with a feedback
skew is ±3° from −75 dBm to +5 dBm (approximately 111 μV p-p loop, care should be taken in layout and component values to
to 1.1 V p-p). The limiter output impedance is 200 Ω, and the prevent oscillation. Recommended values for the common IFs
of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table 6.

12dB NOMINAL 110dB LIMITER GAIN

24dB MIXER GAIN INSERTION LOSS 90dB RSSI
(ASSUMES 6dB IN FILTER)

BAND-PASS 7 FULL-WAVE 11 RSSI

FILTER RECTIFIER CELLS
RFHI 5 2MHz
R2 LPF 12 COM3
MIXER IFHI
MXOP
7 9 14 VPS2
BPF
DRIVER R3 5-STAGE IF AMPLIFIER 15 LMOP
RFLO 6 R1 (16dB PER STAGE)
LO VMID C5
FINAL
+

PREAMP 8 10
LIMITER
+ IFLO
100nF
MIDSUPPLY R4
IF BIAS
13
+

C1 FDBK
BIAS ±50µA
AD608
VPS1 COM1 LOHI COM2 PRUP
1 2 3 4 16

5V 47kΩ
C1 C2
1µF 100pF

LO INPUT CMOS LOGIC 07886-023

–16dBm INPUT

Figure 23. Applications Diagram for Common IFs and Filter Impedances

Table 6. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs
Filter Termination Resistor Offset-Null
Values 1 for 24 dB of Mixer Gain Feedback Loop Values
IF Filter Impedance R1 R2 R3 R4 C1 C5
450 kHz 2 1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF
455 kHz 1500 Ω 174 Ω 1330 Ω 1500 Ω 1000 Ω 200 nF 100 nF
6.5 MHz 1000 Ω 178 Ω 825 Ω 1000 Ω 100 Ω 18 nF 10 nF
10.7 MHz 330 Ω 330 Ω 0Ω 330 Ω 100 Ω 18 nF 10 nF
1
Resistor values were calculated so that R1 + R2 = ZFILTER and R1||(R2 + ZFILTER) = 165 Ω.
2
Operation at IFs of 450 kHz and 455 kHz requires use of an external low-pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz).

Rev. C | Page 10 of 16
 AD608
RSSI OUTPUT supply as a reference, but also causes the RSSI output and the
The logarithmic amplifier uses a successive-detection architecture. ADC output to track over power supply variations, reducing
Each of the five stages has a full-wave detector; two additional system errors and component costs.
high level detectors are driven by attenuators at the input to the POWER CONSUMPTION
limiting amplifiers, for a total of seven detector stages. Because The total power supply current of the AD608 is a nominal
each detector is a full-wave rectifier, the ripple component in 7.3 mA. The power is signal dependent, partly because the RSSI
the resulting dc is at twice the IF. The AD608 low-pass filter has output increases (the current is increased by 200 μA at an RSSI
a 2 MHz cutoff frequency, which is one decade below the 21.4 MHz output of +1.8 V), but mostly due to the IF consumption of the
ripple that results from a 10.7 MHz IF. band-pass filter when driven to ±891 mV, assuming a 4 dB loss
For operation at lower IFs, such as 450 kHz or 455 kHz, the in this filter and a peak input of +5 dBm to the log-IF amp. In
AD608 requires an external low-pass filter with a single pole addition, the power is temperature dependent because the
located at 90 kHz, a decade below the 900 kHz ripple frequency biasing system used in the AD608 is proportional to the
for these IFs. The RSSI range is from the noise level at approx- absolute temperature (PTAT).
imately −80 dBm to overload at +15 dBm and is specified for
TROUBLESHOOTING
±1 dB accuracy from −75 dBm to +5 dBm. The +15 dBm
maximum IF input is provided to accommodate band-pass The most common causes of problems with the AD608 are
filters of lower insertion loss than the nominal 4 dB for incorrect component values for the offset feedback loop, poor
10.7 MHz ceramic filters. board layout, and pickup of radio frequency interference (RFI),
which all cause the AD608 to lose the low end (typically below
DIGITIZING THE RSSI −65 dBm) of its RSSI output and cause the limiter to swing
In typical cellular radio applications, the RSSI output of the randomly. Both poor board layout and incorrect component
AD608 is digitized by an analog-to-digital converter (ADC). values in the offset feedback loop can cause low level oscillations.
The RSSI output of the AD608 is proportional to the power Pickup of RFI can be caused by improper layout and shielding
supply voltage, which not only allows the ADC to use the of the circuit.

Rev. C | Page 11 of 16
AD608

APPLICATIONS INFORMATION
Figure 24 shows the AD608 configured for operation in a digital Figure 25 shows the AD608 configured for narrow-band FM
system at a 10.7 MHz IF. The input and output impedance of the operation at a 450 kHz or 455 kHz with an external discriminator.
filter are parallel terminated using 330 Ω resistors, and the The IF filter has 1500 Ω input and output impedances—the
conversion gain is 24 dB. The RF port is terminated in 50 Ω; in input is matched via a resistive divider, and the output is
a typical application, the input is matched to a SAW filter using terminated in 1500 Ω. The discriminator requires a 1 V p-p
the impedance data provided in Table 5. drive from a 1 kΩ source impedance, which in Figure 25 is
provided by a Class A amplifier with a gain of 2.5.

VPOS
C1 SUPPLY
1µF 2.7V TO 5.5V
+ 1 VPS1 PRUP 16
R4 POWER-UP
47kΩ 3V CMOS
LO INPUT C2 2 COM1 LMOP 15
–16dBm 100pF LIMO
+

3 LOHI VPS2 14
R5 LIMITER
51.1Ω OUTPUT
4 COM2 FDBK 13 VPOS –1V
+ C7 ±200mV
R3
+

5 RFHI COM3 12 18nF

100Ω
RF INPUT C3
–95dBm 100pF 6 RFLO RSSI 11
+

TO C4 RSSI OUTPUT
–15dBm R6
51.1Ω 100pF 7 MXOP IFLO 10 +0.2V TO +1.8V
(20mV/dB)
8 VMID IFHI 9
AD608 C6 +
10nF
BIAS POINT 10.7MHz BPF Z = 330Ω
AT VPOS/2
OFFSET-CONTROL
LOOP FILTER
R1 R2
330Ω 330Ω

+ C5
BPF REVERSE 0.1µF BPF
TERMINATION TEMINATION
07886-024
IF BIAS POINT
DECOUPLING
Figure 24. Application at 10.7 MHz (the Band-Pass Filter Can Be a Toko SK107 or Murata SFE10.7)

JUMPER
PRUP

R16
+5V 47kΩ R13
GND 1 VPS1 R14 402Ω
PRUP 16
C1 C5 0.1µF 8.66kΩ R10
0.1µF 2 COM1 LMOP 15 Q1 F2
LOHI 3.3kΩ
R1 C2 C8 0.1µF AUDIO
3 LOHI VPS2 14 R12 C11 R8
51.1Ω 1nF R15
24.9kΩ 1kΩ 0.1µF CR1 1kΩ
4 COM2 FDBK 13 C10 R11
0.01µF 3.3kΩ
R6 C9 R9
RFHI 5 RFHI COM3 12 0.2µF R5 CR2 1kΩ
R2 1kΩ 200Ω
C3
51.1Ω 1nF 6 RFLO RSSI 11
C6 0.1µF RSSI
C4 7 MXOP IFLO 10
R3
1nF 374Ω 8 VMID IFHI 9
AD608 F1: TOKO HCFM2–455B
R7 R4 F2: MURATA CFY455S
1130Ω F1 1.5kΩ CR1, CR2: 1N60
Q1: 2N3906

C7
07886-025

0.1µF

Figure 25. Narrow-Band FM Application at 450 kHz or 455 kHz

Rev. C | Page 12 of 16
 AD608

OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)

16 9
4.00 (0.1575) 6.20 (0.2441)
1
3.80 (0.1496) 8 5.80 (0.2283)

1.27 (0.0500) 0.50 (0.0197)

BSC 45°
1.75 (0.0689) 0.25 (0.0098)
0.25 (0.0098) 8°
1.35 (0.0531)
0.10 (0.0039) 0°
COPLANARITY SEATING
0.10 0.51 (0.0201) 0.25 (0.0098) 1.27 (0.0500)
PLANE
0.31 (0.0122) 0.40 (0.0157)
0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

060606-A
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 26. 16-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD608AR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
AD608AR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
AD608ARZ 1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
AD608ARZ-RL1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
EVAL-AD608EBZ1 Evaluation Board
1
Z = RoHS Compliant Part.

Rev. C | Page 13 of 16
AD608

NOTES

Rev. C | Page 14 of 16
 AD608

NOTES

Rev. C | Page 15 of 16
AD608

NOTES

©1996–2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07886-0-2/09(C)

Rev. C | Page 16 of 16