a Dual, 16 MHz, Rail-to-Rail

FET Input Amplifier

AD823
FEATURES CONNECTION DIAGRAM
Single Supply Operation 8-Pin Plastic Mini-DIP
Output Swings Rail to Rail and
Input Voltage Range Extends Below Ground 8-Lead SOIC
Single Supply Capability from +3 V to +36 V
High Load Drive OUT1 1 8 +VS
Capacitive Load Drive of 500 pF, G = +1 –IN1 2 7 OUT2
Output Current of 15 mA, 0.5 V from Supplies
+IN1 3 6 –IN2
Excellent AC Performance on 2.6 mA/Amplifier
–VS 4 5 +IN2
–3 dB Bandwidth of 16 MHz, G = +1 AD823
350 ns Settling Time to 0.01% (2 V Step)
Slew Rate of 22 V/ms
Good DC Performance
800 mV Max Input Offset Voltage The AD823 is available over the industrial temperature range of
2 mV/8C Offset Voltage Drift –40°C to +85°C and is offered in both 8-pin plastic DIP and
25 pA Max Input Bias Current SOIC packages.
Low Distortion
–108 dBc Worst Harmonic @ 20 kHz
Low Noise RL = 100kΩ
CL = 50pF
16 nV/√Hz @ 10 kHz VS = +3V
No Phase Inversion with Inputs to the Supply Rails 3V

APPLICATIONS
Battery Powered Precision Instrumentation
Photodiode Preamps
Active Filters
12- to 16-Bit Data Acquisition Systems
Medical Instrumentation
GND

PRODUCT DESCRIPTION 500mV 200µs

The AD823 is a dual precision, 16 MHz, JFET input op amp
that can operate from a single supply of +3.0 V to +36 V, or
dual supplies of ± 1.5 V to ± 18 V. It has true single supply Figure 1. Output Swing, VS = +3 V, G = +1
capability with an input voltage range extending below ground
in single supply mode. Output voltage swing extends to within 2

50 mV of each rail for IOUT ≤ 100 µA providing outstanding out- 1

put dynamic range. 0

Offset voltage of 800 µV max, offset voltage drift of 2 µV/°C, –1

input bias currents below 25 pA and low input voltage noise
OUTPUT – dB

–2
provide dc precision with source impedances up to a Gigohm.
–3
16 MHz, –3 dB bandwidth, –108 dB THD @ 20 kHz and
22 V/µs slew rate are provided with a low supply current of –4
2.6 mA per amplifier. The AD823 drives up to 500 pF of direct –5
VS = +5V
G = +1
capacitive load as a follower, and provides an output current of
–6
15 mA, 0.5 V from the supply rails. This allows the amplifier to
handle a wide range of load conditions. –7

–8
This combination of ac and dc performance, plus the outstand- 1k 10k 100k 1M 10M
FREQUENCY – Hz
ing load drive capability results in an exceptionally versatile am-
plifier for applications such as A/D drivers, high-speed active
filters, and other low voltage, high dynamic range systems. Figure 2. Small Signal Bandwidth, G = +1

REV. 0
Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
AD823–SPECIFICATIONS (@ T = +25°C, V = +5 V, R = 2 kΩ to +2.5 V, unless otherwise noted)
A S L

AD823A
Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth, VO ≤ 0.2 V p-p G = +1 12 16 MHz
Full Power Response VO = 2 V p-p 3.5 MHz
Slew Rate G = –1, VO = 4 V Step 14 22 V/µs
Settling Time G = –1, VO = 2 V Step
to 0.1% 320 ns
to 0.01% 350 ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 1 kHz 1 fA/√Hz
Harmonic Distortion RL = 600 Ω to 2.5 V, VO = 2 V p-p, –108 dBc
f = 20 kHz
Crosstalk
f = 1 kHz RL = 5 kΩ –130 dB
f = 1 MHz RL = 5 kΩ –93 dB
DC PERFORMANCE
Initial Offset 0.2 0.8 mV
Max Offset Over Temperature 0.3 2.0 mV
Offset Drift 2 µV/°C
Input Bias Current VCM = 0 V to +4 V 3 25 pA
at TMAX 0.5 5 nA
Input Offset Current 2 20 pA
at TMAX 0.5 nA
Open-Loop Gain VO = 0.2 V to 4 V
RL = 2 kΩ 20 45 V/mV
TMIN to TMAX 20 V/mV
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range –0.2 to 3 –0.2 to 3.8 V
Input Resistance 1013 Ω
Input Capacitance 1.8 pF
Common-Mode Rejection Ratio VCM = 0 V to 3 V 60 76 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ± 100 µA 0.025 to 4.975 V
IL = ± 2 mA 0.08 to 4.92 V
IL = ± 10 mA 0.25 to 4.75 V
Output Current VOUT = 0.5 V to 4.5 V 16 mA
Short Circuit Current Sourcing to 2.5 V 40 mA
Sinking to 2.5 V 30 mA
Capacitive Load Drive G = +1 500 pF
POWER SUPPLY
Operating Range +3 +36 V
Quiescent Current TMIN to TMAX, Total 5.2 5.6 mA
Power Supply Rejection Ratio VS = +5 V to +15 V, TMIN to TMAX 70 80 dB
Specification subject to change without notice.

–2– REV. 0
 AD823
SPECIFICATIONS (@ TA = +25°C, VS = +3.3 V, RL = 2 kΩ to +1.65 V, unless otherwise noted)
AD823A
Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth, VO ≤ 0.2 V p-p G = +1 12 15 MHz
Full Power Response VO = 2 V p-p 3.2 MHz
Slew Rate G = –1, VO = 2 V Step 13 20 V/µs
Settling Time G = –1, VO = 2 V Step
to 0.1% 250 ns
to 0.01% 300 ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 1 kHz 1 fA/√Hz
Harmonic Distortion RL = 100 Ω, VO = 2 V p-p, f = 20 kHz –93 dBc
Crosstalk
f = 1 kHz RL = 5 kΩ –130 dB
f = 1 MHz RL = 5 kΩ –93 dB
DC PERFORMANCE
Initial Offset 0.2 1.5 mV
Max Offset Over Temperature 0.5 2.5 mV
Offset Drift 2 µV/°C
Input Bias Current VCM = 0 V to +2 V 3 25 pA
at TMAX 0.5 5 nA
Input Offset Current 2 20 pA
at TMAX 0.5 nA
Open-Loop Gain VO = 0.2 V to 2 V
RL = 2 kΩ 15 30 V/mV
TMIN to TMAX 12 V/mV
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range –0.2 to 1 –0.2 to 1.8 V
Input Resistance 1013 Ω
Input Capacitance 1.8 pF
Common-Mode Rejection Ratio VCM = 0 V to 1 V 54 70 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ± 100 µA 0.025 to 3.275 V
IL = ± 2 mA 0.08 to 3.22 V
IL = ± 10 mA 0.25 to 3.05 V
Output Current VOUT = 0.5 V to 2.5 V 15 mA
Short Circuit Current Sourcing to 1.5 V 40 mA
Sinking to 1.5 V 30 mA
Capacitive Load Drive G = +1 500 pF
POWER SUPPLY
Operating Range +3 +36 V
Quiescent Current TMIN to TMAX, Total 5.0 5.7 mA
Power Supply Rejection Ratio VS = +3.3 V to +15 V, TMIN to TMAX 70 80 dB
Specification subject to change without notice.

REV. 0 –3–
AD823–SPECIFICATIONS (@ TA = +25°C, VS = ±15 V, RL = 2 kΩ to 0 V, unless otherwise noted)

AD823A
Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth, VO ≤ 0.2 V p-p G = +1 12 16 MHz
Full Power Response VO = 2 V p-p 4 MHz
Slew Rate G = –1, VO = 10 V Step 17 25 V/µs
Settling Time G = –1, VO = 10 V Step
to 0.1% 550 ns
to 0.01% 650 ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 1 kHz 1 fA/√Hz
Harmonic Distortion RL = 600 Ω, VO = 10 V p-p, –90 dBc
f = 20 kHz
Crosstalk
f = 1 kHz RL = 5 kΩ –130 dB
f = 1 MHz RL = 5 kΩ –93 dB
DC PERFORMANCE
Initial Offset 0.7 3.5 mV
Max Offset Over Temperature 1.0 7 mV
Offset Drift 2 µV/°C
Input Bias Current VCM = 0 V 5 30 pA
VCM = –10 V 60 pA
at TMAX VCM = 0 V 0.5 5 nA
Input Offset Current 2 20 pA
at TMAX 0.5 nA
Open-Loop Gain VO = +10 V to –10 V
RL = 2 kΩ 30 60 V/mV
TMIN to TMAX 30 V/mV
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range –15.2 to 13 –15.2 to 13.8 V
Input Resistance 1013 Ω
Input Capacitance 1.8 pF
Common-Mode Rejection Ratio VCM = –15 V to +13 V 66 82 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ± 100 µA –14.95 to +14.95 V
IL = ± 2 mA –14.92 to +14.92 V
IL = ± 10 mA –14.75 to +14.75 V
Output Current VOUT = –14.5 V to +14.5 V 17 mA
Short Circuit Current Sourcing to 0 V 80 mA
Sinking to 0 V 60 mA
Capacitive Load Drive G = +1 500 pF
POWER SUPPLY
Operating Range +3 +36 V
Quiescent Current TMIN to TMAX, Total 7.0 8.4 mA
Power Supply Rejection Ratio VS = +5 V to +15 V, TMIN to TMAX 70 80 dB
Specification subject to change without notice.

–4– REV. 0
 AD823
ABSOLUTE MAXIMUM RATINGS 1 2.0
8-PIN MINI-DIP PACKAGE TJ = +150°C

MAXIMUM POWER DISSIPATION – Watts

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36 V
Internal Power Dissipation2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts 1.5

Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 0.9 Watts

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 1.2 V 1.0
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
8-PIN SOIC PACKAGE
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C 0.5
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTES 0
1
Stresses above those listed under “Absolute Maximum Ratings” may cause –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
permanent damage to the device. This is a stress rating only and functional AMBIENT TEMPERATURE – °C
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute Figure 3. Maximum Power Dissipation vs. Temperature
maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Pin Plastic Package: θJA = 90°C/Watt
8-Pin SOIC Package: θJA = 160°C/Watt

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD823AN –40°C to +85°C 8-Pin Plastic DIP N-8
AD823AR –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD823AR-REEL –40°C to +85°C SOIC on Reel SO-8

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD823 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0 –5–
AD823–Typical Characteristics
80 100

VS = +5V 90 VS = +5V
70
314 UNITS 317 UNITS
s = 40µV 80 s = 0.4pA
60
70
50
60
UNITS

UNITS
40 50

30 40

30
20
20
10
10

0 0
–200 –150 –100 –50 0 50 100 150 200 0 1 2 3 4 5 6 7 8 9 10
INPUT OFFSET VOLTAGE – µV INPUT BIAS CURRENT – pA

Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Input Bias Current

22 10k
VS = +5V
20 VS = +5V
–55°C TO +125°C
VCM = 0V
18 103 UNITS
1k
16

14 INPUT BIAS CURRENT – pA

100
UNITS

12

10
10
8

4 1

0 0.1
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 0 25 50 75 100 125
INPUT OFFSET VOLTAGE DRIFT – µV/°C TEMPERATURE – °C

Figure 5. Typical Distribution of Input Offset Voltage Drift Figure 8. Input Bias Current vs. Temperature

3 1k
VS = +5V VS = ±15V
2
INPUT BIAS CURRENT – pA

1 100
INPUT BIAS CURRENT – pA

0
10
–1

–2
1

–3

–4 0.1
–5 –4 –3 –2 –1 0 1 2 3 4 5 –16 –12 –8 –4 0 4 8 12 16
COMMON MODE VOLTAGE – Volts COMMON MODE VOLTAGE – Volts

Figure 6. Input Bias Current vs. Common-Mode Voltage Figure 9. Input Bias Current vs. Common-Mode Voltage

–6– REV. 0
 AD823
110 95

94 VS = +5V
RL = 2kΩ
100 93
OPEN-LOOP GAIN – dB

OPEN-LOOP GAIN – dB
VS = ± 2.5V 92
90
91

90
80
89

88
70

87

60 86
100 1k 10k 100k 500k –55 –25 5 35 65 95 125
LOAD RESISTANCE – Ω TEMPERATURE – °C

Figure 10. Open-Loop Gain vs. Load Resistance Figure 13. Open-Loop Gain vs. Temperature

1k 100 100

RL = 10kΩ
80 80
PHASE
100

PHASE MARGIN – Degrees

OPEN-LOOP GAIN – k V
V

OPEN-LOOP GAIN – dB
60 60
RL = 1kΩ

10 40 40
GAIN
RL = 100Ω
20 20
1
RL = 2kΩ
0 0
CL = 20pF

0.1 –20 –20

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 100 1k 10k 100k 1M 10M 100M
OUTPUT VOLTAGE – Volts FREQUENCY – Hz

Figure 11. Open-Loop Gain vs. Output Voltage, VS = ±2.5 V Figure 14. Open-Loop Gain and Phase vs. Frequency

–40 100

VS = +5V
–50 RL = 600Ω
INPUT VOLTAGE NOISE – nV/ √ Hz

–60
VS = +3V 30
VOUT = 2Vp-p
ALL
THD – dB

–70 RL = 100Ω OTHERS

–80 VS = ±15V
VOUT = 10Vp-p,
VS = ±2.5V VS = +3V,
RL = 600Ω 10
VOUT = 2Vp-p VOUT = 2Vp-p,
–90
RL = 1kΩ RL = 5kΩ

–100 VS = +5V
VOUT = 2Vp-p
RL = 5kΩ
–110 3
100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz

Figure 12. Total Harmonic Distortion vs. Frequency Figure 15. Input Voltage Noise vs. Frequency

REV. 0 –7–
AD823–Typical Characteristics
5 90
VS = ±15V
G = +1
4 CL = 20pF 80
RL = 2kΩ VS = +5V
3
CLOSED-LOOP GAIN – dB

2 70

CMRR – dB
60
0
+27°C –55°C 50
–1
+125°C
–2 40

–3
30
–4

–5 20
0.3 3.27 6.24 9.21 12.18 15.15 18.12 21.09 24.06 27.03 30 10 100 1k 10k 100k 1M 10M
FREQUENCY – MHz FREQUENCY – Hz

Figure 16. Closed Loop Gain vs. Frequency Figure 19. Common-Mode Rejection vs. Frequency

100 10

OUTPUT SATURATION VOLTAGE – Volts

VS = +5V
VS = +5V
GAIN = +1
OUTPUT RESISTANCE – Ω

10

VS – VOH
1.0 +25°C

VOL
0.1 +25°C
VOL
0.1 +25°C

0.01 0.01
100 1k 10k 100k 1M 10M 0.1 1 10 100
FREQUENCY – Hz LOAD CURRENT – mA

Figure 17. Output Resistance vs. Frequency, VS = 5 V, Figure 20. Output Saturation Voltage vs. Load Current
Gain = +1

10 10
OUTPUT STEP SIZE FROM 0V TO VSHOWN – Volts

VS = ±15V
8
CL = 20pF 1% 0.1% 0.01% +125°C
6 8
SUPPLY CURRENT – mA

+25°C
4

2 6
–55°C
0

–2 4

–4
1% 0.1% 0.01%
–6 2

–8

–10 0
100 200 300 400 500 600 700 0 5 10 15 20
SETTLING TIME – ns SUPPLY VOLTAGE – ±Volts

Figure 18. Inverter Settling Time vs. Output Step Size Figure 21. Quiescent Current vs. Supply Voltage

–8– REV. 0
 AD823
100 21

90 VIN RS
VS = +5V 18
POWER SUPPLY REJECTION – dB

80 CL

SERIES RESISTANCE – Ω
70 15
+PSRR
60 VS = +5V
12
50
9
40 –PSRR
fM = 45°
30 6
fM = 20°
20
3
10

0 0
100 1k 10k 100k 1M 10M 0 1 2 3 4 5 6 7 8 9 10
FREQUENCY – Hz CAPACITOR – pF 3 1000

Figure 22. Power Supply Rejection vs. Frequency Figure 25. Capacitive Load vs. Series Resistance

30 –30
RL = 2kΩ
–40 VS = +5V
G = +1
–50
OUTPUT VOLTAGE – Vp-p

–60
20

VS = ±15V CROSSTALK – dB –70

–80

–90
10
–100
VS = +5V –110

–120
VS = +3V
0 –130
10k 100k 1M 10M 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz

Figure 23. Large Signal Frequency Response Figure 26. Crosstalk vs. Frequency

VS = +3V
RL = 100kΩ
VIN = 2.9Vp-p
CL = 50pF
G = –1
VS = +3V
3V

GND 500mV 10µs

100k
500mV 200µs
+3V
100k
VIN = 2.9V p-p
VOUT
50Ω
Figure 24. Output Swing, VS = + 3 V, G = +1 100k 50pF

Figure 27. Output Swing, VS = +3 V, G = –1

REV. 0 –9–
AD823–Typical Characteristics
5V
RL = 300Ω
VS = ±15V
CL = 50pF
VIN = 20Vp-p
RF = RG = 2kΩ
G=1

500mV 200µs 20µs

5V
GND

+15V
Figure 28. Output Swing, VS = +5 V, G = –1
20kHz, 20Vp-p
604Ω 50pF
–15V

Figure 31. Output Swing, VS = ± 15 V, G = +1

5V
VS = +3V RL = 2kΩ
VIN = 100mV STEP CL = 50pF
G =+1

1.55V

1.45V

25mV 50ns 500mV 100ns

GND

Figure 29. Pulse Response, VS = +3 V, G = +1 Figure 32. Pulse Response, VS = +5 V, G = +1

5V
VS = +5V VS = +5V
G =+2 G = +1
RL = 2kΩ RL = 2kΩ
CL = 50pF CL = 470pF

500mV 100ns 50mV 200ns

GND

Figure 30. Pulse Response, VS = +5 V , G = +2 Figure 33. Pulse Response, VS = +5 V, G = +1, CL = 470 pF

–10– REV. 0
 AD823
RL = 100kΩ
CL = 50pF

10V

–10V

5V 500ns

Figure 34. Pulse Response, VS = ± 15 V, G = +1

THEORY OF OPERATION of 1 mV max and offset drift of 2 µV/°C are achieved through
This AD823 is fabricated on Analog Devices’ proprietary the use of Analog Devices’ advanced thin-film trimming
complementary bipolar (CB) process that enables the construc- techniques.
tion of pnp and npn transistors with similar fTs in the 600 MHz A “Nested Integrator” topology is used in the AD823 (see small-
to 800 MHz region. In addition, the process also features signal schematic shown in Figure 36). The output stage can be
N-channel JFETs, which are used in the input stage of the AD823. modeled as an ideal op amp with a single-pole response and a
These process features allow the construction of high frequency, unity-gain frequency set by transconductance gm2 and capacitor
low distortion op amps with picoampere input currents. This C2. R1 is the output resistance of the input stage; gm is the in-
design uses a differential-output input stage to maximize band- put transconductance. C1 and C5 provide Miller compensation
width and headroom (see Figure 35). The smaller signal swings for the overall op amp. The unity gain frequency will occur at
required on the S1P, S1N outputs reduce the effect of nonlinear gm/C5. Solving the node equations for this circuit yields:
currents due to junction capacitances and improve the distortion
performance. With this design harmonic distortion of better V OUT A0
than –91 dB @ 20 kHz into 600 Ω with VOUT = 4 V p-p on a =
single 5 volt supply is achieved. The complementary common- Vi  g  
( sR1[C1( A2 + 1)] + 1) ×  s  m2  + 1
emitter design of the output stage provides excellent load drive   C2  
without the need for emitter followers, thereby improving the
output range of the device considerably with respect to conven- where:
tional op amps. The AD823 can drive 20 mA with the outputs
A0 = gmgm2R2R1 (Open Loop Gain of Op Amp)
within 0.6 V of the supply rails. The AD823 also offers out-
standing precision for a high speed op amp. Input offset voltages A2 = gm2R2 (Open Loop Gain of Output Stage)

VCC
Q44
R42 R37 Q43 Q55 I6 A=1
VBE + 0.3V V1 I5
Q57
A=19

Q61 Q49
Q72 Q58
Q18
Q46 C2
J1 J6
VINP R44 R28

Q54 VOUT
Q21
VINN
S1P S1N Q62 Q60

VCC C1

Q48 VB

Q53 Q35

Q17
C6 I2 A=19
I1 R33 R43
I4 Q59
I3 Q56 Q52 A=1

VEE

Figure 35. Simplified Schematic

REV. 0 –11–
AD823
The first pole in the denominator is the dominant pole of the APPLICATION NOTES
amplifier, and occurs at about 18 Hz. This equals the input INPUT CHARACTERISTICS
stage output impedance R1 multiplied by the Miller-multiplied In the AD823, n-channel JFETs are used to provide a low
value of C1. The second pole occurs at the unity-gain band- offset, low noise, high impedance input stage. Minimum input
width of the output stage, which is 23 MHz. This type of archi- common-mode voltage extends from 0.2 V below –VS to 1 V
tecture allows more open loop gain and output drive to be less than +VS. Driving the input voltage closer to the positive
obtained than a standard two-stage architecture would allow. rail will cause a loss of amplifier bandwidth and increased
common-mode voltage error.
OUTPUT IMPEDANCE
The AD823 does not exhibit phase reversal for input voltages
The low frequency open loop output impedance of the
up to and including +VS. Figure 37a shows the response of an
common-emitter output stage used in this design is approxi-
AD823 voltage follower to a 0 V to +5 V (+VS) square wave
mately 30 kΩ. While this is significantly higher than a typical
input. The input and output are superimposed. The output
emitter follower output stage, when connected with feedback
polarity tracks the input polarity up to +VS—no phase reversal.
the output impedance is reduced by the open loop gain of the
The reduced bandwidth above a 4 V input causes the rounding
op amp. With 109 dB of open loop gain the output impedance
of the output wave form. For input voltages greater than +VS, a
is reduced to less than 0.2 Ω. At higher frequencies the output
resistor in series with the AD823’s plus input will prevent phase
impedance will rise as the open loop gain of the op amp drops;
reversal, at the expense of greater input voltage noise. This is il-
however, the output also becomes capacitive due to the integra-
lustrated in Figure 37b.
tor capacitors C1 and C2. This prevents the output impedance
from ever becoming excessively high (see Figure 17), which can
1V 2µs
cause stability problems when driving capacitive loads. In fact,
the AD823 has excellent cap-load drive capability for a high fre- 100
90
quency op amp. Figure 33 shows the AD823 connected as a fol-
lower while driving 470 pF direct capacitive load. Under these
conditions the phase margin is approximately 20°. If greater
phase margin is desired a small resistor can be used in series
with the output to decouple the effect of the load capacitance 10

from the op amp (see Figure 25). In addition, running the part GND 0%

at higher gains will also improve the capacitive load drive capa- 1V
bility of the op amp.

a. Response with RP = 0; VIN from 0 to VS

C1
S1N
1V 1V 10µs
gmVI R1
VOUT
100
S1P
+VS 90
C2
gmVI R1 C5
R2
gm2

10
GND 0%

Figure 36. Small Signal Schematic

1V

+5V
R
P

VIN
AD823
VOUT

b. VIN = 0 to +VS + 200 mV; VOUT = 0 to +VS; RP = 49.9 kΩ

Figure 37. AD823 Input Response

–12– REV. 0
 AD823
Since the input stage uses n-channel JFETs, input current dur- Figure 38 shows a schematic of an AD823 being used to drive
ing normal operation is negative; the current flows out from the both the input and reference input of an AD1672, a 12-bit
input terminals. If the input voltage is driven more positive than 3 MSPS single supply A/D converter. One amplifier is config-
+VS – 0.4 V, the input current will reverse direction as internal ured as a unity gain follower to drive the analog input of the
device junctions become forward biased. This is illustrated in AD1672 which is configured to accept an input voltage that
Figure 6. ranges from 0 to 2.5 V.
A current limiting resistor should be used in series with the in-
+5VA +5VD +5VD
put of the AD823 if there is a possibility of the input voltage ex-
ceeding the positive supply by more than 300 mV, or if an input +5VA
10µF 0.1 0.1 10 0.1µF
voltage will be applied to the AD823 when ± VS = 0. The ampli- 0.1µF 10µF
µF
28 19
µF µF

fier will be damaged if left in that condition for more than 10 +VCC +VDD
2 8 20
seconds. A 1 kΩ resistor allows the amplifier to withstand up to 1 21
REFOUT
AIN1
10 volts of continuous overvoltage, and increases the input volt- VIN
3
49.9Ω 22
AIN2
15
OTR
age noise by a negligible amount. 13
BIT1 (MSB)
14
AD823 12
Input voltages less than –VS are a completely different story. AD1672 BIT2
11
BIT3
The amplifier can safely withstand input voltages 20 volts below VREF
5 10
BIT4
7 23 9
the minus supply voltage as long as the total voltage from the (1.25V) 6 24
REFIN
8
BIT5
IN COM BIT6
positive supply to the input terminal is less than 36 volts. In 4 25
NCOMP2
26 7
NCOMP1 BIT7
addition, the input stage typically maintains picoamp level input 1k
6
BIT8
1k 5
currents across that input voltage range. 4
BIT9
BIT10
3
The AD823 is designed for 16 nV/√Hz wideband input voltage 27 BIT11
ACOM 2
BIT12 (LSB)
1
noise and maintains low noise performance to low frequencies
(refer to Figure 15). This noise performance, along with the 16
CLOCK REF
AD823’s low input current and current noise means that the D
COM COM
AD823 contributes negligible noise for applications with source 19 18
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz.
Figure 38. AD823 Driving Input and Reference of the
OUTPUT CHARACTERISTICS AD1672, a 12-Bit 3 MSPS A/D Converter
The AD823’s unique bipolar rail-to-rail output stage swings The other amplifier is configured as a gain of two to drive the
within 25 mV of the supplies with no external resistive load. The reference input from a 1.25 V reference. Although the AD1672
AD823’s approximate output saturation resistance is 25 Ω has its own internal reference, there are systems that require
sourcing and sinking. This can be used to estimate output satu- greater accuracy than the internal reference provides. On the
ration voltage when driving heavier current loads. For instance, other hand, if the AD1672 internal reference is used, the second
when driving 5 mA, the saturation voltage to the rails will be ap- AD823 amplifier can be used to buffer the reference voltage for
proximately 125 mV. driving other circuitry while minimally loading the reference
If the AD823’s output is driven hard against the output satura- source.
tion voltage, it will recover within 250 ns of the input returning The circuit was tested with a 500 kHz sine wave input that was
to the amplifier’s linear operating region. heavily low pass filtered (60 dB) to minimize the harmonic con-
A/D Driver tent at the input to the AD823. The digital output of the
The rail-to-rail output of the AD823 makes it useful as an A/D AD1672 was analyzed by performing an FFT.
driver in a single supply system. Because it is a dual op amp, it During the testing, it was observed that at 500 kHz, the output
can be used to drive both the analog input of the A/D along with of the AD823 cannot go below about 350 mV (operating with
its reference input. The high impedance FET input of the negative supply at ground) without seriously degrading the sec-
AD823 is well suited for minimally loading of high output im- ond harmonic distortion. Another test was performed with a
pedance devices. 200 Ω pull-down resistor to ground that allowed the output to
go as low as 200 mV without seriously affecting the second har-
monic distortion. There was, however, a slight increase in the
third harmonic term with the resistor added, but it was still less
than the second harmonic.

REV. 0 –13–
AD823
Figure 39 is an FFT plot of the results of driving the AD1672 +3V

with the AD823 with no pull-down resistor. The input ampli-

tude was 2.15 V p-p and the lower voltage excursion was 95.3kΩ 95.3k
0.1µF 0.1µF
350 mV. The input frequency was 490 kHz, which was chosen CHANNEL 1 3 8
+
to spread the location of the harmonics. 1µF 47.5k
1/2
AD823
1
MYLAR 2 500µF
The distortion analysis is important for systems requiring good
frequency domain performance. Other systems may require L
95.3k 4.99k
good time domain performance. The noise and settling time 10k
performance of the AD823 will provide the necessary informa- HEADPHONES
32Ω IMPEDANCE
tion for its applicability for these systems. 10k

R
1 4.99k

6 500µF
VIN = 2.15Vp-p 1/2
1µF 47.5k 7
G = +1 AD823 +
FI = 490kHz CHANNEL 2 5 4
MYLAR
15dB/DIV

4
Figure 40. 3 Volt Single Supply Stereo Headphone Driver
6 9 7
5
3 8 Second Order Low-Pass Filter
Figure 41 depicts the AD823 configured as a second order
Butterworth low-pass filter. With the values as shown, the cor-
ner frequency will be 200 kHz. The equations for component
selection are shown below:
R1 = R2 = user selected (typical values: 10 kΩ to 100 kΩ).
Figure 39. FFT of AD1672 Output Driven by AD823 1.414 0.707
C1( farads ) = ; C2 =
3 Volt, Single Supply Stereo Headphone Driver 2 πfcutoff R1 2 πfcutoff R1
The AD823 exhibits good current drive and THD+N perfor-
mance, even at 3 V single supplies. At 20 kHz, total harmonic
distortion plus noise (THD+N) equals –62 dB (0.079%) for a C2
+5V

300 mV p-p output signal. This is comparable to other single 56pF C3

0.1µF
R1 R2
supply op amps which consume more power and cannot run on 20k 20k
3 V power supplies. VIN
1/2
C1
In Figure 40, each channel’s input signal is coupled via a 1 µF AD823 VOUT
28pF
50pF
Mylar capacitor. Resistor dividers set the dc voltage at the non-
inverting inputs so that the output voltage is midway between
the power supplies (+1.5 V). The gain is 1.5. Each half of the C4
AD823 can then be used to drive a headphone channel. A 5 Hz 0.1µF
high-pass filter is realized by the 500 µF capacitors and the –5V
headphones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency Figure 41. Second Order Low-Pass Filter
range (20 Hz–20 kHz) are delivered to the headphones. A plot of the filter is shown below; better than 50 dB of high fre-
quency rejection is provided.

–14– REV. 0
 AD823
0 put at node C is then a full-wave rectified version of the input.
Node B is a buffered half-wave rectified version of the input.
Input voltage supply to ± 18 volts can be rectified, depending on
HIGH FREQUENCY REJECTION – dB

–10

VDB – VOUT the voltage supply used.

–20
R1 R2
100kΩ 100kΩ
–30

+VS
–40 0.01µF
A 6
8
3 7 C
A2
–50 1 5
VIN A1 1/2 FULL-WAVE
2 RECTIFIED OUTPUT
1/2 AD823
4
–60 AD823
1k 10k 100k 1M 10M 100M
FREQUENCY – Hz B
HALF-WAVE
RECTIFIED OUTPUT
Figure 42. Frequency Response of Filter
Single-Supply Half-Wave and Full-Wave Rectifiers
An AD823 configured as a unity gain follower and operated 2V 2V 200µs
with a single supply can be used as a simple half-wave rectifier.
100
The AD823’s inputs maintain picoamp level input currents even A 90

when driven well below the minus supply. The rectifier puts that
behavior to good use, maintaining an input impedance of over
1011 Ω for input voltages from 1 volt from the positive supply to B
20 volts below the negative supply.
10
The full- and half-wave rectifier shown in Figure 43 operates as C 0%

follows: when VIN is above ground, R1 is bootstrapped through 2V

the unity gain follower A1 and the loop of amplifier A2. This
forces the inputs of A2 to be equal, thus no current flows
through R1 or R2, and the circuit output tracks the input. When Figure 43. Single Supply Half- and Full-Wave Rectifier
VIN is below ground, the output of A1 is forced to ground. The
noninverting input of amplifier A2 sees the ground level output
of A1, therefore, A2 operates as a unity gain inverter. The out-

REV. 0 –15–
AD823
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

8 5

C2035–7.5–5/95
0.25
(6.35) 0.31
PIN 1
(7.87)
1 4

0.30 (7.62)
0.39 (9.91) MAX REF
0.035±0.01
(0.89±0.25)
0.165±0.01
(4.19±0.25)

0.125 0.18±0.03 0.011±0.003

(3.18) (4.57±0.76) (0.28±0.08)
MIN
15 °
0°
0.018±0.003 0.10 0.033
SEATING
(0.46±0.08) (2.54) (0.84)
PLANE
BSC NOM

8-Lead Plastic SOIC

(SO-8)

8 5
0.1574 (4.00)
0.1497 (3.80)
PIN 1
1 4 0.2440 (6.20)
0.2284 (5.80)

0.1968 (5.00) 0.0196 (0.50)

0.1890 (4.80) x 45 °
0.0099 (0.25)
0.0688 (1.75)
0.0098 (0.25)
0.0532 (1.35)
0.0040 (0.10)
8°
0.0500 0.0192 (0.49) 0.0098 (0.25) 0° 0.0500 (1.27)
(1.27) 0.0138 (0.35) 0.0160 (0.41)
BSC 0.0075 (0.19)

PRINTED IN U.S.A.

–16– REV. 0