Sistemas Digitales I

Carlos A. Angulo J.

OPERATORS
▪ BITWISE ▪ LOGICAL
The operations are performed on each bit of the bus. All buses The following logical operators are used in conditional
(output and inputs) must have same size. TRUE/FALSE statements to specify the condition for the
~ // NOT: Invert a single-bit signal or each bit in a bus operation.
& // AND two single bits or each bit between two buses
! // Not True
| // OR two single bits or each bit between two buses
&& // Both Inputs True
^ // XOR two single bits or each bit between two buses
|| // Either Input True
▪ ARITHMETIC == // Inputs Equal
+ // Addition != // Inputs Not Equal
- // Subtraction < // Less-than
<= // Less-than or Equal
▪ UNARY REDUCTION > // Greater-than
& // AND all bits in the busl >= // Greater-than or Equal
| // OR all bits in the busl

▪ BIT SWIZZLING
▪ COMPARATORS To select and to rearrange the elements of a vector.
== // Equal {A, B, C} // Concatenate “A”, “B” and “C” into a bus
!= // Not Equal {3{A}} // Replicate “A” 3 times
> // Greater-than {{5{A}}, B} // Replicate “A” 5 times and concatenate to “B”
>= // Greater-than or Equal A[4] // Select bit 4 of bus A
< // Less-than A[3:1] // Select bits 3, 2 and 1 (3 to 1) of bus A
<= // Less-than or Equal

RESERVED KEYWORDS https://www.csee.umbc.edu/portal/help/VHDL/verilog/reserved.html

always end ifnone not rnmos tri
and endcase incdir notif0 rpmos tri0
assign endconfig include notif1 rtran tri1
automatic endfunction initial or rtranif0 triand
begin endgenerate inout output rtranif1 trior
buf endmodule input parameter scalared trireg
bufif0 endprimitive instance pmos showcancelled unsigned
bufif1 endspecify integer posedge signed use
case endtable join primitive small vectored
casex endtask large pull0 specify wait
casez event liblist pull1 specparam wand
cell for library pulldown strong0 weak0
cmos force localparam pullup strong1 weak1
config forever macromodule pulsestyle_onevent supply0 while
deassign fork medium pulsestyle_ondetect supply1 wire
default function module rcmos table wor
defparam generate nand real task xnor
design genvar negedge realtime time xor
disable highz0 nmos reg tran
edge highz1 nor release tranif0
else if noshowcancelled repeat tranif1
 Sistemas Digitales I
Carlos A. Angulo J.

SYNTHESIS CONSTRUCTS
▪ CONTINUOUS ASSIGNMENT ▪ CONDITIONAL ASSIGNMENT
assign _wire = signal_or_value; assign _wire= 1bit_sel? signal_for_1: signal_for_0;

▪ INSTANTATION WITHOUT PARAMETER ▪ INSTANTATION WITH PARAMETER

submodule_name label ( submodule_name #(.parameter_name(value)) label (
.submodule_port (signal_or_value), .submodule_port (signal_or_value),
.submodule_port (signal_or_value) .submodule_port (signal_or_value)
); );

▪ GENERATE
genvar var;

generate
for (var_initialization; condition; step)
begin: label
statement or instantiation
end
endgenerate

▪ PROCEDURAL ASSIGNMENTS
Assignments made inside “always” procedural blocks. All variables on the left-hand side must be register data type.
◦ case PROCEDURAL STATEMENT
always @(event_list)
always @(event_list) case (expression)
case (expression) 1: statement_for_1;
0: statement_for_0; 2: statement_for_2;
1: statement_for_1; 6: statement_for_6;
2: statement_for_2; default: default_statement;
3: statement_for_3; endcase
4: statement_for_4;
5: statement_for_5; always @(event_list)
6: statement_for_6; case (expression)
7: statement_for_7; 0,2,4: statement_for_0_2_4;
default: default_statement; 3,7 : statement_for_3_7;
endcase 6 : statement_for_6;
default: default_statement;
endcase

◦ if PROCEDURAL STATEMENT
always @(event_list) always @(event_list)
if (condition) if (condition)
statement_for_true; statement;
else else if (condition)
statement_for_false; statement;
else
statement;
 Sistemas Digitales I
Carlos A. Angulo J.

SIMULATION CONSTRUCTS
$finish is a system task that ends simulation.
$monitor is a system task that outputs the value of the variables if they change. Only one $monitor task can be active at a time.

▪ $urandom ▪ $urandom_range(maxval, minval)

Returns a 32-bit pseudo-random number. Returns a pseudo-random number between minval and maxval.
If minval is omitted, the function shall return a value between 0 and maxval.

▪ LOOP STATEMENTS
There are several ways to create a looping statement within a Verilog
testbench. Each of these constructs must appear within an “initial” or
“always” block.
• initial: procedural block that executes once at start of simulation and stop.
This construct is not supported by the synthesis standard.
• always: procedural block that acts like a continuous loop.

◦ FOREVER LOOP ◦ WHILE LOOP

The statements are executed continuously. The statements are executed if the condition is
The forever loop is used to create an infinite loop. evaluated as true.
forever begin The while loop is a good way to create a conditional
statements; loop that will execute if a condition is met.
end while (condition) begin
statements;
end
◦ FOR LOOP
The statements are executed if the condition is evaluated as true. ◦ REPEAT LOOP
The for loop is used when a finite loop is desired, and it is necessary to key The statements are executed (X) times.
off the loop variable. Requires a loop variable declaration. A repeat loop is used to perform an action a finite
integer loop_var; number of times and the loop variable is not needed
for the function.
for (loop_var=initial_value; condition; step) repeat (X) begin
begin statements;
statements; end
end

The testbench must include the following statements to display the results of the simulation in gtkwave:
initial begin
$dumpfile("ARCHIVO.vcd");
$dumpvars;
end