3 Cmpe140 Isa2 S17

CMPE140
Computer Architecture & Design

Instruction Set Architecture & Language (2)
Donald Hung
(www.sjsu.edu/people/donald.hung/)
Professor
Computer Engineering Department
San Jose State University
[Partially adopted from Harris & Harris’ Digital Design and Computer Architecture]
CMPE140 Instruction Set Architecture & Language (2).1 Donald Hung, © 2017
Computer Hardware Structural Abstraction
The processor (CPU) is the core of a computer.
Processor PowerPC Processor

SRAM
Controller
SRAM Memory
(CPU) I-Cahe D-Cahe
PLB
Arbiter Processor Local Bus (PLB)
PLB-to-OPB OPB-to-PLB DMA

Bridge Bridge Controller Interconnect
OPB
Arbiter On-Chip Peripheral Bus (OPB)
USB Host Ethernet OPB-PCI

UART
Controller MAC Bridge I/O Components
Memory
Computers use memories to store information:
 Instructions – form the program to be executed
 Data – operands needed by the program
Why not just use registers?
 Too expensive for the amount of information
needs to be stored
 Recall: registers – fast but expensive
memories – slow but cheap
Memory Access
 The MIPS (and other RISC processors) uses

separate memories to store information:
- instruction memory (IM) stores instructions (program)
- data memory (DM) stores data (operands)
This is known as the “Harvard Architecture”.
 How to access the memories?

Processors must issue physical addresses, each points
to a memory location. The 32-bit MIPS always use 32-
bit addresses for memory access. All MIPS instructions
are 32-bit wide.
Memory Access (continued)
 The MIPS uses a special-purpose register
named PC (program counter) for IM access
(read only)
- the PC’s content is the physical address of a memory
location (in the IM) where the current instruction is
stored
 The MIPS uses the “base addressing” method

for DM access (read and write)
- the physical address of an operand in DM is formed by
base address + a constant offset
where the base address is in one of MIPS’ general-
purpose register, and the offset is calculated from
information embedded in MIPS’ memory access (‘load’
and ‘store’) instructions (more on this later).
What “Load” and “Store” Mean
 The words Load and Store are used for two
different kind of communications between the
MIPS processor and its DM
- Load means data transfer from DM to the processor
- Store means data transfer from the processor to DM
 The 32-bit MIPS has load and store instructions

for 32-bit (word), 16-bit (half-word) and 8-bit
(byte) data transfers.
- due to time limitation, we will mostly discuss word-
sized load/store instruction in class.
“Word Addressable” and “Byte Addressable” Memories
 Word Addressable Memory

- in the DM, each memory location pointed by a physical
address contains word-sized (32-bit) data
 Byte Addressable Memory
- in the DM, each memory location pointed by a physical
address contains byte-sized (8-bit) data
 MIPS and most processors are Byte Addressable
- i.e., a physical address points to a byte in DM, thus a
32-bit word stored in the DM corresponds to 4
consecutive addresses.
Big-Endian and Little-Endian Memory
 How to store wide data in memory
 Little-endian: byte numbers start at the little end, i.e., the
lowest address stores the LSB
 Big-endian: byte numbers start at the big end, i.e., the
lowest address stores the MSB
Big-Endian Little-Endian
Byte Word Byte
Address Address Address
C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
MIPS Load Instructions
 Load Word mnemonic: lw

 Operation: Rdest  M[Rbase + offset]
 Example of a complete lw instruction:
lw $s3, 4($0)
operation: $s3  M[$0 + 4]
 MIPS also has load byte (lb) and load halfword
(lh) instructions.
MIPS Store Instructions
 Store Word mnemonic: sw

 Operation: M[Rbase + offset]  Rsource
 Example of a complete sw instruction:
sw $s3, 4($0)
operation: M[$0 + 4] $s3
MIPS also has store byte (sb) and store halfword
(sh) instructions.
MIPS Endianess
 MIPS (and many other processors) follow the Big

Endian rule. For a word transfer (lw or sw), the
physical address formed by Rbase + offset is the
lowest address that corresponds to the MSB of the
word to be transferred.
 As an example, if addresses 4, 5, 6, 7 in DM stores
data 0x12, 0x34, 0x56 and 0x78 respectively,
executing the instruction below
lw $s3, 4($0)
will load register $s3 with the contents 0x12345678.
Data Alignment in Memory
 MIPS (and most processors) require data wider

than a byte to be “aligned” in DM, e.g., the
starting address of a halfword must be multiple
of 2, and the starting address of a word must be
multiple of 4.
 Therefore, physical addresses for a word
transfer must have 0’s for its two least significant
bits (word-aligned), and physical addresses for a
halfword transfer must have a 0 for its least
significant bit (halfword-aligned).
Big- and Little-Endian Example
• Suppose $t0 initially contains 0x23456789. After the
following program is run on a big-endian system, what
value does $s0 contain? In a little-endian system?
sw $t0, 0($0)
lb $s0, 1($0)
Big-Endian Little-Endian
Word
Byte Address 0 1 2 3 Address 3 2 1 0 Byte Address
Data Value 23 45 67 89 0 23 45 67 89 Data Value
MSB LSB MSB LSB
Answer:
Big-endian: 0x00000045; Little-endian: 0x00000067

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CMPE140

Computer Architecture & Design

Processor PowerPC Processor

PLB-to-OPB OPB-to-PLB DMA

USB Host Ethernet OPB-PCI

 The MIPS (and other RISC processors) uses

 How to access the memories?

 The MIPS uses the “base addressing” method

 The 32-bit MIPS has load and store instructions

 Word Addressable Memory

 Load Word mnemonic: lw

 Store Word mnemonic: sw

 MIPS (and many other processors) follow the Big

 MIPS (and most processors) require data wider

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