EEPC-301: MICROPROCESSORS AND

INTERFACING

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23

INTERNAL ARCHITECTURE

 The functional block diagram of 8085A is shown in fig 1.1

 It consists of five essential blocks.

(1) Arithmetic Logic Section

(2) Register Section

(3) The Interrupt Control Section

(4) Serial I/O Section

(5) The Timing And Control Unit

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 2

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 3
 There is an internal bi-directional data bus of 8-bit wide. This bus is used to transfer data and
instructions among various internal registers.
 All the internal registers which transfer data to the internal bus are tri-state registers. Higher
order address bus (A15-A8) and time-multiplexed lower order address data bus (AD7-AD0)
are the external buses and used to interface peripherals and memory chips to CPU.
 Address buffer and address/data buffers isolate the internal data bus from the external address
bus and address/data bus and drive the external address bus and address/data bus. The CPU can
send the address of desired memory locations and I/O chip through these buffers.
 The 8-bit internal data bus is also connected to the address/data buffers. The bi-directional arrows
indicate a tri-state connection that allows the address/data buffer to send or receive data from the
8-bit internal data bus.
 In the output mode the information on the data bus is loaded into the 8-bit data latch that drives
the address/data bus output buffer. The output buffers are floated during input or non transfer
operations.
 During the input mode, data from the external bus is transferred over the internal data bus to
internal register.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 4

(1) ARITHMETIC & LOGIC SECTION:
This section consists of:
(a) Accumulator:
 Arithmetic and/or logic operations on one or two operations are the basic data
transformations implemented in a μρ one of these two operands is always in the
accumulator.
 Accumulator is an 8-bit register accessible to the user is connected to the 8-bit internal
data bus. The bi-directional arrow between the accumulator and the bus indicates a tri-
state connection that allows the accumulator to send or receive data.
 In addition, it has a two state 8-bit output. The content of the accumulator is always
available at this two state output as one of the operands for the ALU. The contents of the
accumulator can be manipulated through instructions.
 The result of arithmetic/ logical operations carried out by ALU is also stored back in the
accumulator.
 In other words, it accumulates the result of the operation, hence, the name accumulator.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 5

(b) Temporary registrar (TR):
 This is an 8-bit register not accessible to the user. It is used by the processor for internal
operations.
 The second operand as and when necessary is loaded in to this register by the
microprocessor before the desisted operation takes placed in the ALU.
 The temporary register has 8-btis two state output. The second operand is always available at
this output.

(c) Arithmetic Logical Unit (ALU):

 ALU is a combination logic block which performs the desired operation on the two operands.
The contents of the accumulator and the temporary register are the inputs to the ALU.
 This is governed by the control signals generated by the timing and control unit. The various
arithmetic and logical operations that can be performed by ALU are:
 Binary addition, subtraction, increment and decrement,
 Logical AND, OR and EX-OR,
 Complement,
 Rotate left of right.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 6

 The result of the operation is, in general, stored back in accumulator. In subtraction
operation, the content of the temporary register is subtracted from the content of the
accumulator and is stored back in the accumulator.
 In many applications it is appropriate to represent data in binary coded decimal (BCD)
form. The result on any operation on BCD should also be in BCD form.
 The ALU contains additional logic to adjust result of addition operations where the
operands are interpreted as BCD data.

(d) Flags register:

 The ALU influences a number of flip flops called flags which store information related to
the results of arithmetic and logical operations. Taken together this flags constitute a
flag register.
 Flag register is an 8-bit register accessible to the user through instruction. Each bit in
the flag register has a specific function. Only 5 bits out of 8 bits are used as shown
below:

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 7

 The three crossed bit are redundant bits and not used. They can be either ‘0’ or ‘1’ but
normally they are forced to be zero. The other five bits are affected as a result of
execution of an instruction.
 All instructions do not affect these flags e.g. data transfer operation do not affect these
flags. The meaning and the effect of these flags are as follows.
CY (Carry) Flag bit:
 This particular bit is SET (=1) if there is a carry from the MSB position during an addition
operation or if there is a borrow during the subtraction operation otherwise the flag is
reset (=0).
 The processor, by design, does the subtraction operation also by taking 2’s complement
of one operand and adding it to another operand.
P (Parity) Flag bit:
 The parity flag test for the number of ‘1’s in the accumulator.
 If the accumulator holds on an even number of 1’s, it is said that even parity exists and
the parity flag is set to ‘1’. However, if the accumulator holds an odd number of ‘1’ it is
called odd parity and the parity flag is reset to ‘0’.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 8

AC (Auxiliary Carry) Flag bit:
 This bit is set if there is a carry from b3 bit to b4 bit of accumulator during addition
operation otherwise it is reset. The AC flag is useful for BCD arithmetic and is used in a
particular instruction known as DAA (Decimal Adjust Accumulator).
Z (Zero) Flag bit:
 Zero flag bit is SET if the result of an operation is zero, otherwise it is RESET.
Sign Flag bit:
 The sign flag is set to the condition of the most significant bit (MSB) of the accumulator
following the execution of arithmetic or logical operation.
 These instructions use the MSB of the data (result) to represent the sign of the number
contained in the accumulator.
 A set sign flag represents a negative number, where as a reset flag means a positive
number.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 9

(2) REGISTER SECTION:
General Purpose Registers:
 There are six 8-bit general purpose registers designated as B, C, D, E, H and L. All these
registers are accessible to the user. It means their contents can be read without
destroying it or some new data can be written into it through instructions.
 These registers constitute a register array like a small on-chip RAM with addressable
memory location.
 Internal control signals select the register for a read or write operation. This means that
the CPU can either load a register from the 8-bit internal data bus or output the register
content to the internal 8-bit data bus. Data can also be transferred or exchanged among
registers.
 In an instruction, these six registers along with the accumulator (A) is identified by a 3-
bit code designated either SSS or DDD.
 Whenever SSS is used, it corresponds to source register and whenever DDD is used, it
corresponds to destination register.
 The address codes used for these internal registers are as follows.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 10

 Note: In the above codes (110) is assigned to memory pointer or M-register. Whenever it is
used for SSS or DDD it means a specific register pair (H,L) together forms a 16 bit register
known as memory address register (MAR) or M- pointer. In other words, whenever M is used
in an instruction, it is assumed the 16-bit address of memory location, being referred, is
available in (H,L) register pair.

PROGRAM COUNTER:
 This is a 16-bit register accessible to the user. It is a special purpose register and it always
contains the address of the next instruction to be fetched from the program memory and
executed by the CPU in a program sequence.
 Thus the program counter keeps the track of the program execution in which instructions are
to be executed next.
Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 11
STACK POINTER REGISTER:
 The stack is a storage area of the processor.
 It consists of number of sequential and RWM locations in which microprocessor saves
the internal register contents during subroutine calls and interrupts so that they will not
be changed or destroyed by a subroutine.
 8085A μ𝑝 can address directly 64K memory locations. This is known as directly
addressable memory space starting from the address 0000H to FFFFH.
 This entire memory area is usually divided by the user into program area, data area and
stack area.
 It is for the user to see that program area and data area do not overlap with that of stack
memory area.
 The size of the stack memory area depends upon the application.
 For example, the user for a particular process control operation may decide to reserve
memory space starting from 2600H to 2700H as the stack memory space. This is shown
in fig. in next slide.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 12

 The stack pointer is a 16-bit register accessible to the user. It
is required to refer any memory location of the stack. It
contains the address of the top of stack into which last data is
put or written.
 Writing data into a stack is called a PUSH operation and
reading data from a stack is called a POP operation. In the
figure shown 2700H is known as the bottom of the stack.
 Now, let us suppose that while calling a subroutine it
becomes necessary to save the contents of (B,C) register
pair and (D,E) register pair as they are to be used in the
subroutine.
 The process of saving the content of a register is known as
push operation. The push operation is performed at the
beginning of a subroutine to save register contents and the
instruction for pushing the contents of the internal register is
PUSH e.g. PUSH B.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 13

 The meaning of the instruction PUSH B is to push the
contents of (B,C) register pair on to the stack so that it
can be saved there till it is restored. PUSH B operation
affects the stack and stack pointer as follows:
 Since the stack pointer always holds the address of
the last byte of data pushed onto the stack, therefore,
when PUSH B instruction is executed, the stack
pointer is decremented by 1 and the contents of the
(B) register are copied onto the stack at that address.
 The stack pointer is decremented again, and the
contents of the (C) register are copied to that
address.
 Just after the execution of the PUSH B instruction, the
situation is shown in fig.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 14

 Similarly, to store the contents of (D,E) register pair
PUSH D instruction is used. The meaning of this
instruction is push the contents of the (D,E) pair onto
the stack to save them there as shown in figure just
after the execution.

 Since the contents of (B,C) & (D,E) register pairs are

stored at the top of the stack, these registers are now
available for further computation in the subroutine.
 At a later stage of execution of the program after
utilizing B, C, D, E registers, there may be a need to
restore the original contents to the respective
registers.
 E.g. at the end of the subroutine, the data is restored
to the proper register.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 15

 The restoration of the contents is a READ operation from
the stack and is known as POP operation. A POP register
instruction copies the stored data from the stack back
into the indicated register pair. Just before the
execution of POP instruction, let us say the situation is as
shown below:
 Note that registers (B), (C), (D) and (E) have some
different contents because these registers are used in
the subroutine.
 To restore the contents of (B,C) register pair, POP B
instruction is used. Whenever this instruction is
executed, the contents from the top of the stack are read
and written into the (B,C) register pair. To restore the
contents of (D,E) register pair POP D instruction is used.
 The question is in which sequence these instructions
are to be executed so that the contents are restored
properly. The obvious sequence in POP D first & then
POP B i.e., the data must be popped off in the reverse
order from which it was pushed. This type of stack is
called Last-in-First-out (LIFO) memory.
Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 16
 Just after the execution of POP D & POP B instructions, the situation is as shown in
figure:

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 17

 From this whole discussion, following points emerge:
1. The stack pointer always points to the top of the stack up to which it is full with relevant
data.
2. Storing or saving the data from the registers on stack is known as PUSH operation.
3. The restoring or reading data from the stack onto certain internal registers is known as
POP operation.
4. The stack operates on Last-in-first-out (LIFO) basis.
5. The stack pointer can be initialized to the bottom of the stack but bottom of the stack
cannot be utilized to store any useful data.
6. It is for the user to see that the program area does not overlap with stack area.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 18

W-Z Registers:
 (W) and (Z) are two 8-bit temporary registers not accessible to the user. They are
exclusively used for the internal operation by the microprocessor.
 These registers are used either to store 8-bit of information in each (W) and (Z) registers
or a 16-bit data in (W,Z) register pair with lower order 8-bits in (Z) and higher-order 8-
bits in (W) register.

Increment-Decrement Address Latch:

 It is another 16-bit internal register latch available in the register section for internal
operations and is not accessible to the user. The address latch serves two functions.
 First, it selects an address to be sent out from the program counter, from the stack
pointer, or from one of the 16-bit register pairs.
 Second, it latches this address onto the address lines for the required time.
 The 16-bit addresses from 8085A allow the microprocessor up to 216 memory locations
through A15-A8 and AD7-AD0 lines.
 An increment/decrement register allows the contents of any of the 16-bit registers to be
incremented or decremented.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 19

Instruction Register & Instruction Decoder:
 The first word of an instruction is the operation code, i.e., binary code for that
instruction. Therefore, firstly μ𝑝 fetches the instruction from the memory. The op-code
representing the instruction to be executed is fetched from the (program) memory
location pointed to by (PC) and loaded into the instruction register (IR).
 The IR passes this op-code to the instruction decoder which interprets this op-code
appropriately in order to decide what operation needs to be done for executing this
instruction. The instruction decoder tells the control unit the type of instruction to be
executed; the number of machine cycles necessary to execute the instruction etc.
 In response, the control unit generates all the necessary control signals which go into
the different internal block of the microprocessor.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 20

(3) THE INTERRUPT CONTROL SECTION:
 Sometimes it is necessary to interrupt the execution of the main program to answer a
request from an I/O device. For instance, an I/O device may send an interrupt signal to
interrupt control unit to indicate that data is ready for input.
 The μ𝑝 temporarily stops what it is doing, inputs the data and then returns to what it was
doing. To enable the processor to service the device requesting service through
interrupt, processor accepts and issues control signals through interrupt control section.

(4) SERIAL I/O CONTROL:

 Sometimes, I/O devices work with serial data rather than parallel. In this case, the serial
data stream from an input device must be converted to 8-bit parallel data before the
computer can use it.
 Likewise the 8-bit data out of a processor must be converted to serial form before a
serial output device can use it.
 The SID (Serial Input Data) input is where serial data enters the 8085A. The SOD (Serial
Output Data) output is where the serial data leaves the 8085A.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 21

(5) TIMING AND CONTROL SECTION:
 The timing and control section supervise the complete operation of the 𝜇𝑝.
 The on-chip clock oscillator which produces the internal clock is a part of this section.
The timing and control section also has a state generator circuit to generate 10 different
states (will discuss later in syllabus).
 State generator is a multi-mode counter. The next state of the state generator from the
present state is decided by many of the control signals input like READY, HOLD,
interrupt control signals - TRAP, RST7.5, RST6.5, RST5.5 and INTR.
 In each state this section generates many control signals for executing the instruction
fetched.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 22