Ec8461 Circuit Design and Simulation Lab

Sri Shanmugha College of Engineering and Technology
Approved by AICTE, New Delhi and Affiliated to Anna University,

Chennai
Accredited by NAAC and NBA (ECE/CSE/MECH)
Pullipalayam, Sankari, Salem (Dt.)
Department of Electronics and Communication Engineering
EC8461 - CIRCUITS AND SIMULATION INTEGRATED LABORATORY
LAB MANUAL
REGULATION : 2017
Prepared by
(M.SARANYA, AP/ECE)
1
EC8461 - Circuits and Simulation Integrated Laboratory LPTC
0042
LIST OF EXPERIMENTS
DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS

1. Series and Shunt feedback amplifiers-Frequency response, Input and output
impedance calculation
2. RC Phase shift oscillator and Wien Bridge Oscillator
3. Hartley Oscillator and Colpitts Oscillator
4. Single Tuned Amplifier
5. RC Integrator and Differentiator circuits
6. Astable and Monostable multivibrators
7. Clippers and Clampers
SIMULATION USING SPICE (Using Transistor):

1. Tuned Collector Oscillator
2. Twin -T Oscillator / Wein Bridge Oscillator
3. Double and Stagger tuned Amplifiers
4. Bistable Multivibrator
5. Schmitt Trigger circuit with Predictable hysteresis
6. Analysis of power Amplifiers.
TOTAL: 45 PERIODS
2
Course outcomes:
CO 1 Analyze various types of feedback amplifiers
CO 2 Design oscillators, tuned amplifiers
CO 3 Design wave-shaping circuits.
CO 4 Design multi vibrators
Design and simulate feedback amplifiers, oscillators, tuned

CO 5 amplifiers, wave-shaping circuits and multivibrators using
SPICE Tool.
CO PO, PSO Mappings

Course Program Outcomes PSO
Code and
CO
Course
name 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
EC8461 CO 1 3 2 2 2 3 2 - - 3 3 - 1 3 3 3
Circuits CO 2 3 2 2 2 3 2 - - 3 2 - 2 3 3 3
And CO 3 3 2 2 2 3 2 - - 2 3 - 2 3 3 3
Simulation
CO 4 3 2 2 3 3 2 - - 3 3 - 3 3 3 3
Integrated
Laboratory CO 5 3 2 3 3 3 2 - - 3 2 - 2 3 3 3
Average 3 2 2 2.4 3 2 - - 3 3 - 2 3 3 3
3
CONTENTS
Page
Sl. No. Components of the
Experiment No.
DESIGN EXPERIMENTS
1.a Current series feedback amplifier
1.b Voltage shunt feedback amplifier
2.a RC phase shift oscillator
2.b Wein- Bridge oscillator
3.a Hartley’s oscillator
3.b Colpitt’s oscillator
4 Single Tuned Oscillator
5 RC Integrator and Differentiator circuits
6.a Astable Multivibrator
6.b Monostable Multivibrator
7 Clippers and Clampers
SIMULATION USING SPICE EXPERIMENTS
9 Tuned Collector oscillator
10 Wein-Bridge Oscillator
11 Double and Stagger tuned Amplifier
12 Bistatble Multivibrator
13 Schmitt Trigger circuit with Predictable hysteresis
14 Analysis of power amplifier
CONTENT BEYOND SYLLABUS
15 Twin -T Oscillator Using SPICE
16 Voltage and Current Time Base Generators
4
Ex. No.: 1.a CURRENT SERIES FEEDBACK AMPLIFER
Date:
AIM:
To design a negative feedback amplifier and to draw its frequency
response.
APPARATUS REQUIRED:
S.No EQUIPMENTS RANGE QUANTIT Y
1 Function generator (0-1)MHz 1

2 CRO (0-20)MHz 1
3 Resistors 1.5 K, 6KΏ, Each one
2K, 14k,
2.3K, 10K
4 Power supply (0-30V) 1
5 Transistors BC 107 1
6 Capacitors 28F, 1
10F,720F
Design examples:
VCC= 15V, IC=1mA, AV= 30, fL= 50Hz, S=3, hFE= 100, hie= 1.1KΏ
Gain formula is,
AV= - hFE RLeff / hie
Assume, VCE = VCC / 2 (transistor in active region)
VCE = 15 /2=7.5V
VE = VCC / 10= 15/10=1.5V
Emitter resistance is given by, re =26mV/ IE
Therefore re =26 Ώ
hie= hfe re
hie =2.6KΏ
(i) To calculate RC:

Applying KVL to output loop,
VCC= IC RC + VCE+ IE RE ------ (1)
Where RE = VE / IE (IC= IE)
RE = 1.5 / 1x10-3= 1.5KΏ
From equation (1),
RC= 6KΏ
5
(ii) To calculate RB1&RB2:
Since IB is small when compared with IC,
IC ~ I E
VB= VBE + VE= 0.7 + 1.5=2.2V
VB= VCC (RB2 / RB1+ RB2)------ (2)
S=1+ (RB / RE)
RB= 2KΏ
We know that RB= RB1|| RB2
RB= R B1RB2/ RB1+RB2 --------- (3)
Solving equation (2) & (3),
Therefore,
RB1 = 14KΏ
From equation (3), RB2= 2.3KΏ
(iii) To find input coupling capacitor (Ci):

XCi = (hie|| RB) / 10
XCi = 113
XCi= 1/ 2пf Ci
Ci = 1 / 2пf XCi
Ci = 1/ 2X3.14X 50 X 113=28µf
(iv)To find output coupling capacitor (CO):

XCO= (RC || RL) / 10, (Assume RL= 10KΏ)
XCO= 375
XCO= 1/ 2пf CO
CO = 1/ 2x 3.14x 50 x 375=8µf =10 µf
(v) To find Bypass capacitor (CE):

(Without feedback)
XCE = {(RB+hie / 1+ hfe) || RE}/ 10
XCE = 4.416
CE= 1 / 2пf XCE
CE = 720 µf
Design with feedback:

To design with feedback remove the bypass capacitor (CE).
Assume RE = 10KΏ
6
CIRCUIT DIAGRAM:
WITHOUT FEED BACK:
WITH FEEDBACK:
7
MODEL TABULATION:
Without feedback:
Vi=
Frequency Output Voltage Gain = 20 log(V0/Vi) (dB)
Sl. No Gain = V0/Vi
(Hz) (V0) (volts)
With feedback:
Vi=
Frequency Output Voltage Gain = 20 log(V0/Vi)
Sl. No Gain = V0/Vi (dB)
(Hz) (V0) (volts)
MODEL GRAPH:
8
THEORY
Negative feedback in general increases the bandwidth of the transfer function

stabilized by the specific type of feedback used in a circuit. In Voltage series
feedback amplifier, consider a common emitter stage with a resistance R’ connected
from emitter to ground. This is a case of voltage series feedback and we expect the
bandwidth of the trans resistance to be improved due to the feedback through R’. The
voltage source is represented by its Norton’s equivalent current source Is=Vs/Rs.
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Set VCC = 10V; set input voltage using audio frequency oscillator.
3. By varying audio frequency oscillator take down output frequency
oscillator voltage for difference in frequency.
4. Calculate the gain in dB
5. Plot gain Vs frequency curve in semi-log sheet.
6. Repeat the steps 1 to 6 with feedback
7. Compare this response with respect to the amplifier without feedback.
RESULT:
Thus current series feedback amplifier is designed and studied
its performance.
9
Ex. No.: 1.b VOLTAGE SHUNT FEEDBACK AMPLIFIER
Date:
AIM:
To design and study frequency response of voltage shunt feedback amplifier.
APPARATUS REQUIRED:
Components Range Quantity
S.No
Signal generator (0-30)MHz 1
CRO (0-20)V 1
1.
Regulated Power Supply (0-30)V 1
Resistor 3k, 1.1 1

k,5k
2.5
2. k,1k,
Capacitor 66F, 1
30F,58 µf
Transistors BC 107 1
Bread board - 1
3. Connecting Wires Single strand As required
DESIGN PROCEDURE:
Given specifications:
VCC= 10V, IC=1.2mA, AV= 30, fI = 1 kHz, S=2, hFE= 150, β=0.4
The feedback factor, β= - 1/RF= +1/0.4=2.5KΏ

The voltage gain is given by,
AV= -hfe (RC|| RF) / hie
h ie = β re
re = 26mV / IE = 26mV / 1.2mA = 21.6
hie = 150 x 21.6 =3.2K
Apply KVL to output loop,
VCC= IC RC + VCE+ IE RE ----- (1)
Where VE = IE RE (IC= IE)
VE= VCC / 10= 1V
Therefore RE= 1/1.2x10-3=0.8K= 1KΏ
10
VCE= VCC/2= 5V
From equation (1), RC= 3 KΏ
(ii) To calculate R1&R2:

S=1+ (RB/RE)
RB= (S-1) RE= R1 || R2 =1KΏ
RB= R 1R2 / R1+ R2 ------- (2)
VB= VBE + VE = 0.7+ 1= 1.7V
VB= VCC R2 / R1+ R2 ----- -- (3)
Solving equation (2) & (3),
R1= 5 KΏ & R2= 1.1KΏ
(iii) To calculate Resistance:

Output resistance is given by,
RO= RC || RF
RO= 1.3KΏ
input impedance is given by,
Ri = (RB|| RF) || hie = 0.6KΏ
Trans-resistance is given by,
Rm= -hfe (RB|| RF)( RC || RF) / (RB|| RF)+ hie
Rm= 0.06KΏ
AC parameter with feedback network:
(i) Input Impedance:

Rif = Ri /D (where D= 1+β Rm)
Therefore D = 25
Rif= 24
Input coupling capacitor is given by,
Xci= Rif / 10= 2.4 (since XCi << Rif)
Ci = 1/ 2пfXCi =66µf
(ii) Output impedance:

ROf= RO/ D = 52
Output coupling capacitor:
XCO= Rof /10= 5.2
CO = 1/ 2пfXCO= 30µf
(iii) Emitter capacitor:

XCE << R’E = R’/10
R’E= RE|| {( hie +RB) / (1+hfe)}
XCE= 2.7
Therefore CE= 58µf
11
WITHOUT FEED BACK
CIRCUIT DIAGRAM:
+10V
R1 RC 3K
5K C1
VCC
1n
Rs Ci
Q1
1k 66uf
5V Vi R2 R5
CE
1.1K 1k
58uf
WITH FEED BACK
CIRCUIT DIAGRAM
12
MODEL TABULATION:
Without feedback:
Vi=
Sl. No Gain = V0/Vi
(Hz) (V0) (volts) (dB)
With feedback:
Vi=
Sl. No Gain = V0/Vi
(Hz) (V0) (volts) (dB)
MODEL GRAPH:
13
THEORY:
Negative feedback in general increases the bandwidth of the transfer function
stabilized by the specific type of feedback used in a circuit. In Voltage shunt
feedback amplifier, consider a common emitter stage with a resistance R’ connected
from collector to base. This is a case of voltage shunt feedback and we expect the
bandwidth of the Trans resistance to be improved due to the feedback through R’.
The voltage source is represented by its Norton’s equivalent current source Is=Vs/Rs.
PROCEDURE:

2. Set VCC = 10V; set input voltage using audio frequency oscillator.
3. By varying audio frequency oscillator take down output frequency
oscillator voltage for difference in frequency.
4. Calculate the gain in dB
5. Plot gain Vs frequency curve in semi-log sheet.
6. Repeat the steps 1 to 6 with feedback
7. Compare this response with respect to the amplifier without feedback.
RESULT:
Thus voltage shunt feedback amplifier is designed and studied its

performance.
14
Ex. No.: 2.a
Date: RC PHASE SHIFT OSCILLATOR
AIM:
To design a RC phase shift oscillator and to find the frequency of

oscillation
APPARATUS REQUIRED:
S. No RANGE QUANT ITY

Components
1 Resistors 7.5k,1.4 k
4.8K,1.2K, 1each, 3
19K, 6.5K
2 Power supply (0-30)V 1
3 Transistor BC107 1
4 Capacitors 1.3f , 2.1f, 1,1,3
1.3f, 0.01F
5 CRO (0-30)MHz 1
6 Bread board - 1
Design Example:
Specifications:
VCC = 12V, ICq =1mA, =100, Vceq = 5V, f=1 KHz, S=10, C=0.01 µf,
hfe= 330, AV= 29
Design:
(i) To find R:
Assume f=1 KHz, C=0.01µf

f=1/2∏ RC 6
R=1/2x3.14 6 x1x103x0.01x10-6=6.5KΩ
Therefore R=6.5KΩ
(ii) To find RE & RC:
VCE = VCC /2 = 6V
15
re= 26mV / IE= 26
hie = hfe re= 330 x 26= 8580
On applying KVL to output loop,
VCC=ICRC + VCE + IERE ----- (1)
VE = IE RE
RE = VE / IE =1.2/ 10-3 =1.2K
From equation (1), 12= 10-3(RC+ 1200) +6= RC=
4800=4.8K
(iii) To calculate R1 & R2:
VBB= VCC R2 / R1+ R2 ------ (2)

VB= VBE +VE = 0.7+12 =1.9V
From equation (2), 1.9= 12 R2 / R1+ R2
R2 / R1+ R2= 0.158 --------- (3)
S = 1+ RB / RE= RB = 1.2K
RB =R1 || R2
0.15R1= 1.2x10-3=7.5K
R2 =0.158 R1 + 0.158 R2, R2= 1.425K
(iv) To calculate Coupling capacitors:
(i) XCi= {[hie + (1+hfe) RE] || RB }/ 10 = 0.12K

XCi= 1 / 2∏ f Ci == 1.3f
(ii) XCO= RLeff / 10 [ AV = - hfe RLeff / hie]
RLeff = 0.74K, XCO=0.075 K
XCO= 1 / 2∏ f CO , CO = 2.1f
(iii) XCE= RE / 10 = 1.326 f
XCE = 1 / 2∏ f CE=49.27f
(iv) Feed back capacitor, XCF = Rf / 10
Cf = 0.636f = 0.01f
16
CIRCUIT DIAGRAM:
MODEL GRAPH:
TABULATION:
S.NO Amplitude Time Period (ms)
17
THEORY:
The low frequencies RC oscillators are more suitable. Tuned circuit is not
an essential APPARATUS REQUIRED for oscillation. The essential APPARATUS
REQUIRED is that there must be a 180o phase shift around the feedback network and
loop gain should be greater than unity. The 180o phase shift in feedback signal can be
achieved by suitable RC network.
PROCEDURE:
2. Set VCC = 15V.
3. For the given supply the amplitude and time period is measured from CRO.
4. Frequency of oscillation is calculated by the formula f=1/T
5. Amplitude Vs time graph is drawn.
RESULT:
Thus the RC-phase shift oscillator is designed and constructed for the
given frequency.
18
Ex. No.: 2.b
Date: WEIN- BRIDGE OSCILLATOR
AIM:
To design a Wein-bridge oscillator using transistors and to find the
frequency of oscillation.
APPARATUS REQUIRED:
S.No APPARATUS RANGE QUANTITY
REQUIRED
1 Resistors
2 Power supply 5V 1
4 Capacitors
5 CRO 1
6 Bread board 1
DESIGN EXAMPLE:
Assume f=1 KHz, C=0.1µf
f = 1/ 2∏RC
R= 1/2∏fC
R =1/2x3.14x1x103x0.1x103
R= 1.59KΩ
To calculate R1:
R1= 10R
R1 =10x1.5K
R1 =15.9KΩ
To calculate Rf (Feedback resistor):
Rf = 2R1
Rf = 2(15.9x103) =31.8KΩ ≈ 33KΩ
19
THEORY:
Generally in an oscillator, amplifier stage introduces 180o phase shift and
feedback network introduces additional 180o phase shift, to obtain a phase shift of
360o around a loop. This is a condition for any oscillator. But Wein bridge oscillator
uses a non-inverting amplifier and hence does not provide any phase shift during
amplifier stage. As total phase shift requires is 0o or 2n radians, in Wein bridge
type no phase shift is necessary through feedback. Thus the total phase shift around a
loop is 0o. The output of the amplifier is applied between the terminals 1 and 3,
which are the input to the feedback network. While the amplifier input is supplied
from the diagonal terminals 2 and 4, which is the output from the feedback network.
Thus amplifier supplied its own output through the Wein bridge as a feedback
network.
The two arms of the bridge, Componentsly R1, C1 in series and R2, C2 in
parallel are called frequency sensitive arms. This is because the components of these
two arms decide the frequency of the oscillator. Advantage of Wein bridge oscillator
is that by varying the two-capacitor values simultaneously, by mounting them on the
common shaft, different frequency ranges can be provided.
PROCEDURE:
2. Set VCC = 5V.
20
CIRCUIT DIAGRAM
MODEL GRAPH:
MODEL TABULATION:
RESULT:
Thus the Wein – bridge oscillator is designed for the given frequency
of oscillation.
21
Ex. No.: 3.a HARTLEY’S OSCILLATOR
Date:
AIM:
To design and construct a Hartley oscillator at the given operating frequency.
APPARATUS REQUIRED:
S.No RANGE QUANTITY

EQUIPMENTS
1 Resistors
2 RPS (0-30)V 1
4 Capacitors
5 Inductor 10mH 2
6 CRO 30MHz 1
7 Bread board - 1
Design Example:
Design of feed back Network:

Given L1= L2=10mH, f=20 KHz, VCC=12V, IC=3mA, S=12
f = 1/2∏ (L1+ L2)C
C= 3.2nf
Amplifier design:
(i) Selection of RC:

Gain formula is,
AV= - hfe RLeff / hie
Assume VCE=VCC/2 (Transistor active)
VCE= 12/2= 6V
VE=IERE= VCC/10=1.2V
VCC=ICRC + VCE + IERE
22
RC= (VCC- VCE -IERE) / IC
Therefore RC = 1.6K=2 K
(ii) Selection of RE:

IC= IE=3mA
RE= VE/IE
RE= 1.2 / 3x10-3=400 =1K
(iii) Selection of R1 & R2:
Stability factor S=12
S=1+ (RB/ RE)
12=1+ (RB/1x103)
RB=11K
Using potential divider rule,
RB=R1R2 / R1+R2 & VB= (R2/ R1+R2) VCC
RB /R1= R2/ R1+R2
Therefore RB/R1= VB/VCC
VB=VBE+ VE= 0.7+1.2=1.9V=2V
R1= (VCC/ VB )RB
R1= (12/2)x 11x103=66K=100K
VB/VCC =R2 / R1+R2
2/ 12=R2 / 100x103+R2
(100x103)+R2=R2/0.16=19K
R2=19K=22 K
(iv)Output capacitance (CO):

XCO=RC/10=2x103/10=200
1/2∏fCO=200
CO=1/2x3.14x20x103x200
23
CO=0.039=0.01µf
(v) Input capacitance (Ci):

XCin= RB/10=11x103/10=1.1x103
1/2∏fCin=1.1x103
Cin=1/2x3.14x20x103x1.1x103
Cin= 0.007=0.01µf
(vi) By pass Capacitance (CE):

XCE=RE/10=1x103/10=100
1/2∏fCE=100
CE= 1/2x3.14x20x103x100
CE = 0.079µf = 0.1µf
THEORY:
Hartley oscillator is very popular and is commonly used as
local oscillator in radio receivers. The collector voltage is applied to the collector
through inductor L whose reactance is high compared with X2 and may therefore be
omitted from equivalent circuit, at zero frequency, however capacitor Cb acts as an
open circuit.
PROCEDURE:
2. Set VCC = 12V.
5. Verify it with theoretical frequency, f= 1/2∏ ( (L1+ L2)C ) Amplitude Vs time

graph is drawn.
24
CIRCUIT DIAGRAM:
MODEL GRAPH:
MODEL TABULATION:
RESULT:
Thus the Hartley oscillator is designed and constructed for the given frequency.
25
Ex. No.: 3.b.
Date: COLPITT’S OSCILLTOR
AIM:
To design and construct a Colpitt’s oscillator at the given operating

Frequency.
APPARATUS REQUIRED:
S.No EQUIPME NTS RANG E QUANTI TY
1 Resistors
2 RPS (0-30)V 1
4 Capacitors
5 Inductor 10mH 1
6 CRO 30MHz 1
7 Bread board - 1
Design of feedback Network:

Given C1= 0.1 F, L=10mH, f=20 KHz, VCC=12V,IC=3mA, S=12
C1 + C2
f = 1/2∏ , C2= 0.01F
LC1C2
Amplifier design:
(i)Selection of RC:
Gain formula is,
AV= - hfe RLeff / hie
Assume VCE=VCC/2 (Transistor active)
VCE= 12/2= 6V
VE=IERE= VCC/10=1.2V
VCC=ICRC + VCE + IERE
RC= (VCC- VCE -IERE) / IC
Therefore RC= 1.6K=2 K
(ii) Selection of RE:
IC= IE=3mA
RE= VE/IE= 1K
(iii) Selection of R1 & R2:
Stability factor S=12
S=1+(RB/ RE)
12=1+ (RB/1x103)=11k
Using potential divider rule,
26
RB=R1R2 / R1+R2 & VB= (R2/ R1+R2) VCC
RB /R1= R2/ R1+R2
Therefore RB/R1= VB/VCC
VB=VBE+ VE= 0.7+1.2=1.9V=2V
R1= (VCC/ VB ) RB=66K=100K
VB/VCC =R2 / R1+R2
2/ 12=R2 / 100x103+R2
R2=19K=22 K
(iv) Output capacitance (CO):
XCO=RC/10=2x103/10=200
1/2∏fCO=200
CO=1/2x3.14x20x103x200=0.039=0.01µf
(v) Input capacitance (Ci):
XCin= RB/10=11x103/10=1.1x103
1/2∏fCin=1.1x103
Cin=1/2x3.14x20x103x1.1x103=0.0101µf
(vi) By pass Capacitance (CE):
XCE=RE/10=1x103/10=100
1/2∏fCE=100
CE= 1/2x3.14x20x103x100=0.079µf = 0.1µf
THEORY:
Colpitt’s oscillator is very popular and is commonly used as local
oscillator in radio receivers. The collector voltage is applied to the collector through
inductor L whose reactance is high compared with X2 and may therefore be omitted
from equivalent circuit, at zero frequency; The circuit operates as Class C. the
tuned circuit determines basically the frequency of oscillation.
PROCEDURE:

2. Set VCC = 12V.
3. For the given supply the amplitude and time period is
measured from CRO.
5 .Amplitude Vs time graph is drawn.
27
CIRCUIT DIAGRAM:
FIG 8.1
MODEL GRAPH:
MODEL TABULATION:
RESULT:
Thus the Collipit’s oscillator is designed and constructed for the given
frequency.
28
Ex. No.:4
Date: SINGLE TUNED AMPLIFIER
AIM:
To design a single tuned amplifier and to draw its frequency response.
APPARATUS REQUIRED:
S.No EQUIPMENTS RANGE QUANTITY

1 Resistors
2 RPS (0-30)V 1
4 Capacitors
5 CRO (0-30)MHz 1
6 Function generator (0-10)MHz 1
7 Bread board - 1
DESIGN EXAMPLE:
Given specifications
Vcc = 12V, β = 100, Ic = 1mA, L=1mH, f=2 KHz, S= [2-10]
Assume, VCE = VCC / 2=6V
VE = VCC / 10 =1.2V
To calculate C:
F = 1/ 2∏ LC
Therefore C=0 .6μf

To calculate RE:
VE= IE RE (IC= IE)
RE = VE / IE= 1.2 / 1x10-3 = 1.2K
Assume S= 10, S= 1+ (RB / RE)
Therefore RB= 10K
To find R1 & R2:
RB = R1 || R2
RB= R1 R2 / R1+ R2 -------------- (1)
VB= VCC x (R2 / R1+ R2) -------- (2)
29
CIRCUIT DIAGRAM:
MODEL GRAPH:
30
TABULATION:
FREQUENCY Vin (V) OUTPUT Gain = 20log(Vo/Vin) dB

VO(V)
THEORY:
The single tuned amplifier selecting the range of frequency the resistance load
replaced by the tank circuit. Tank circuit is nothing but inductors and capacitor in
parallel with each other. The tuned amplifier gives the response only at particular
frequency at which the output is almost zero. The resistor R 1 and R2 provide potential
diving biasing, Re and Ce provide the thermal stabilization. This it fixes up the
operating point.
PROCEDURE:
1. Connections are given as per the circuit diagram
2. By varying frequency, amplitude is noted down
3. Gain is calculated in dB
4. Frequency response curve is drawn.
RESULT:
Thus the class – c single tuned amplifier is designed and frequency response
is plotted.
31
Ex. No.: 5
Date: INTEGRATOR AND DIFFERENTIATOR
AIM:
To design and construct a differentiator and integrator circuit.
APPARATUS REQUIRED:
S.No
Function (0-30)MHz 1
generator
1. CRO (0-20)V 1
Resistor 1 k 1
2.
Capacitor 1 uf 1
Bread board - 1
3. Connecting Wires Single As required
strand
THEORY:
Differentiator:
Differentiator is a circuit which differentiates the input signal, it allows high
order frequency and blocks low order frequency. If time constant is very low it acts
as a differentiator. In this circuit input is continuous pulse with high and low value.
Integrator:
In a low pass filter when the time constant is very large it acts as a integrator.
In this the voltage drop across C will be very small in comparison with the drop
across resistor R. So total input appears across the R.
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set the signal voltage.
3. Observe the output waveform.
4. Sketch the output waveform.
32
INTEGRATOR:
CIRCUIT DIAGRAM:
MODEL TABULATION:
S.NO Amplitude(V) Time(ms)
MODEL GRAPH:
33
DIFFERENTIATOR
CIRCUIT DIAGRAM:
MODEL TABULATION:
S.NO Amplitude(V) Time(ms)
MODEL GRAPH:
RESULT:
Thus the integrator and differentiator are constructed and output waveform
observed and readings were tabulated
34
Ex. No.: 6.a EMITTER COUPLED ASTABLE MULTIVIBRATOR
Date:
AIM:
To design an Emitter coupled Astable multivibrator and study the output
waveform.
APPARATUS REQUIRED:
1 Resistors
2 RPS (0-30)V 1
4 Capacitors
5 CRO (0-30)MHz 1
6 Bread board - 1
DESIGN EXAMPLE:
VCC= 10V; hfe = 100; f=1 KHz; I c = 2mA; Vce (sat) = 0.2v;
To design RC:
R ≤ hFE RC
RC= VCC- VC2 (Sat) / IC= 4.9 k
Since R ≤ hFE RC
Therefore R≤ 100 x 4.7 x103=490 k  470 k
To Design C:
Since T= 1.38RC
1x10-3=1.38x 490x103x C
Therefore C=0.01F
THEORY:
The astable multivibrator generates square wave without any external
triggering pulse. It has no stable state, i.e., it has two quasi- Stable states. It switches
35
back and forth from one stable state to other, remaining in each state for a time
depending upon the discharging of a capacitive circuit. When supply voltage + Vcc is
applied, one transistor will Conduct more than the other due to some circuit
imbalance.
PROCEDURE:
2. Set VCC = 5V.
3. For the given supply the amplitude and time period is measured
from CRO.
36
CIRCUIT DIAGRAM
MODEL GRAPH:
37
TABULATION:
S.NO Amplitude(V) Time period(msec)
RESULT:
Thus the astable multivibrator is designed and output waveform is
plotted
38
Ex. No.: 6.b MONOSTABLE MULTIVIBRATOR
Date:
AIM:
To design and test the performance of Monostable multivibrator for the given
frequency
APPARATUS REQUIRED:

1 Resistors
2 RPS (0-30)V 1
4 CRO (0-30)MHz 1
5 Capacitor 3.2nf 1
25pf 1
6 Bread board - 1
DESIGN EXAMPLE:
VCC= 12V; hfe = 200; f=1 KHz; I c = 2mA; Vce (sat) = 0.2v; VBB= - 2V,
RC = VCC - Vce (sat) / IC
RC = 12 – 0.2 / 2x10-3=5.9KΩ
(ii) To calculate R:
IB2(min)=IC2 / hfe= 2x10-3 / 200 = 10µ A
Select IB2 > IB1(min) (say 25µ A)
Then R = VCC – V BE (sat) / IB2
Therefore R= 12-0.7/25x10-6=452KΩ
(iii) To calculate C:
T=0.69RC
1x10-3= 0.69x452x103xC
C=3.2nf
39
To calculate R1 & R2:
VB1= {(VBB R1/ R1 +R2) + (VCE (sat) R2 / R1+R2)}
Since Q1 is in off state, VB1 ≤ 0
Then (VBB R1/ R1 +R2) = (VCE (sat) R2 / R1+R2)
VBB R1 = VCE (sat) R2
2 R1 = 0.2 R2
Assume R1=10KΩ, then R2=100 KΩ
Consider, C1= 25pf (commutative capacitor)
THEORY:
The monostable multivibrator has one stable state when an external trigger
input is applied the circuit changes its state from stable quasi stable state. And then
automatically after some time interval the circuit returns back to the original normal
stable state. The time T is dependent on circuit components.
The capacitor C1 is a speed-up capacitor coupled to base of Q2 through C.
Thus DC coupling in bistable multivibrator is replaced by a capacitor coupling. The
resistor R at input of Q2 is returned to VCC. The value of R2, V BB are chosen such that
transistor Q1 is off by reverse biasing it. Q2 is on. This is possible by forward
biasing Q2 with the help of VCC and resistance R. Thus Q2-ON and Q1-OFF is
normal stable state of circuit.
PROCEDURE:
2. Give a negative trigger input to Q2.
3. Note the output of transistor Q2 and Q1.
4. Find the value of Ton and Toff.
40
CIRCUIT DIAGRAM:
MODEL GRAPH:
41
TABULATION:
S.NO Amplitude(V) Time period (msec)
RESULT:
Thus the monostable multivibrator is designed and the performance is tested.
42
Ex. No.: 7
Date: CLIPPER AND CLAMPER CIRCUITS
AIM:
To construct and design the clipper and clamper circuits using diodes.
APPARATUS REQUIRED:

S.No
Function (0-30)MHz 1
generator
1. CRO (0-20)V 1
Diode IN4007 1
2. Resistor 1k 1
Capacitor 1uf 2
Bread board - 1
3. Connecting Wires Single As required
strand
DESIGN PROCEDURE:
Given f=1 kHz,
T=t=1/f=1x10-3 sec=RC
Assume, C=1uF
Then, R=1KΩ
43
POSITIVE CLIPPER
CIRCUIT DIAGRAM:
MODEL TABULATION:
S.NO SIGNAL AMPLITUDE Time (ms)
1 Input
2 Output
MODEL GRAPH:
44
NEGATIVE CLIPPER:
CIRCUIT DIAGRAM:
MODEL TABULATION:
1 Input
2 Output
MODEL GRAPH:
45
CLAMPER CIRCUIT:
POSITIVE CLAMPER CIRCUIT DIAGRAM:
Vin=5V
MODEL TABULATION:
1 Input
2 Output
MODEL GRAPH:
46
NEGATIVE CLAMPER CIRCUI DIAGRAM:
Vin=5V
MODEL TABULATION:
1 Input
2 Output
MODEL GRAPH:
47
THEORY
CLIPPER:
A Clipper is a circuit that removes either the positive or negative part of a
waveform. For a positive clipper only the negative half cycle will appear as output.
CLAMPER:
A Clamper circuit is a circuit that adds a dc voltage to the signal. A positive
clamper shifts the ac reference level upto a dc level.
WORKING:
During the positive half cycle, the diode turns on and looks like a short circuit
across the output terminals. Ideally, the output voltage is zero. But practically, the
diode voltage is 0.7 V while conducting.
On the negative half cycle, the diode is open and hence the negative half cycle
appear across the output.
APPLICATION:
• Used for wave shaping

• To protect sensitive circuits
PROCEDURE:
1. Connect as per the circuit diagram.
2. Set the signal voltage (say 5V, 1 KHz) using signal generator.
3. Observe the output waveform using CRO.
4. Sketch the output waveform.
RESULT:
Thus the output waveform for Clipper and clamper was observed and its
readings are tabulated.
48
SIMULATION USING PSPICE
49
Ex. No.: 9
Date: TUNED COLLECTOR OSCILLATOR
AIM:
To simulate a tuned collector oscillator using PSPICE.
APPARATUS REQUIRED:
1. PC
2. PSPICE software
THEORY:
Tuned collector oscillation is a type of transistor LC oscillator where the tuned
circuit (tank) consists of a transformer and a capacitor is connected in the collector
circuit of the transistor. Tuned collector oscillator is of course the simplest and the
basic type of LC oscillators. The tuned circuit connected at the collector circuit
behaves like a purely resistive load at resonance and determines the oscillator
frequency. The common applications of tuned collector oscillator are RF oscillator
circuits, mixers, frequency demodulators, signal generators etc.,
PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and them in
the work space.
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms.
50
CIRCUIT DIAGRAM:
`
MODEL GRAPH:
RESULT:
Thus the tuned collector oscillator is simulated using PSpice.
51
Ex. No.: 10 WEIN BRIGE OSCILLATOR
Date:
AIM:
To simulate voltage and current time base circuits by using PSPICE.
APPARATUS REQUIRED:
1. PC
2. PSPICE software
THEORY:
Generally in an oscillator, amplifier stage introduces 180 o phase shift and

feedback network introduces additional 180o phase shift, to obtain a phase shift of
360o around a loop. This is a condition for any oscillator. But Wein bridge oscillator
uses a non-inverting amplifier and hence does not provide any phase shift during
amplifier stage. As total phase shift requires is 0o or 2n radians, in Wein bridge
type no phase shift is necessary through feedback. Thus the total phase shift around a
loop is 0o. The output of the amplifier is applied between the terminals 1 and 3,
which are the input to the feedback network. While the amplifier input is supplied
from the diagonal terminals 2 and 4, which is the output from the feedback network.
Thus amplifier supplied its own output through the Wein bridge as a feed back
network.
PROCEDURE:
2. Select the parts required for the circuit from the parts menu and place them in
the work space
5. Simulate the circuit and observe the corresponding output waveforms
52
7.5 CIRCUIT DIAGRAM:
MODEL GRAPH:
RESULT:
Thus the Wein Bridge Oscillator is simulated using Pspice.
53
Ex. No.: 11
Date: DOUBLE AND STAGGERED TUNED AMPLIFIER
AIM:
To simulate double and staggered tuned amplifiers.
APPARATUS REQUIRED:
1. PC
2. PSPICE software
THEORY:
A double-tuned amplifier is a tuned amplifier with transformer coupling

between the amplifier stages in which the inductances of both the primary and
secondary windings are tuned separately with a capacitor across each. The scheme
results in a wider bandwidth than a single tuned circuit would achieve. There is a
critical value of transformer coupling coefficient at which the frequency response of
the amplifier is maximally flat in the pass band and the gain is maximum at
the resonant frequency. Designs frequently use a coupling greater than this (over-
coupling) in order to achieve an even wider bandwidth at the expense of a small loss
of gain in the centre of the pass band. Staggered tuning is a technique used in the
design of multi-stage tuned amplifiers whereby each stage is tuned to a slightly
different frequency. In comparison to synchronous tuning (where each stage is tuned
identically) it produces a wider bandwidth at the expense of reduced gain.
It also produces a sharper transition from the passband to the stopband. Both
staggered tuning and synchronous tuning circuits are easier to tune and manufacture
than many other filter types. The function of stagger-tuned circuits can be expressed
as a rational function and hence they can be designed to any of the major filter
responses such as Butterworth and Chebyshev. The poles of the circuit are easy to
54
manipulate to achieve the desired response because of the amplifier buffering
between stages.
PROCEDURE:
2. Select the parts required for the circuit from the parts menu and place
them in the work space
55
CIRCUIT DIAGRAM:
DOUBLE TUNNED AMPLIFIER
MODEL GRAPH:
DOUBLE TUNNED AMPLIFIER
RESULT:
Thus the double and staggered tuned amplifier is simulated.
56
Ex. No.: 12
Date: BI-STABLE MULTIVIBRATOR
AIM:
To simulate an Bi-stable multivibrator using PSPICE.
APPARATUS REQUIRED:
1. PC
2. PSPICE software
THEORY:
Bi- stable multivibrator contains two stable states and no quasi states. It
requires two clock or trigger pulses to change the states. It is also called as flip flop,
scale of two toggle circuit, trigger circuit. It is used in digital operations like
counting, storing data’s in flip flops and production of square waveforms.
PROCEDURE:
57
CIRCUIT DIAGRAM:
MODEL GRAPH:
RESULT:
Thus the Bi-stable multivibrator is simulated using PSpice.
58
Ex. No.: 13
Date: SCHMITT TRIGGER CIRCUIT WITH PREDICTABLE
HYSTERESIS
AIM:
To simulate Schmitt Trigger circuit with Predictable hysteresis.
APPARATUS REQUIRED:
1. PC
2. PSPICE software
THEORY:
A Schmitt trigger is a comparator circuit with hysteresis, implemented by

applying positive feedback to the input of an amplifier. It is an active circuit which
converts an analog input signal to a digital output signal. The circuit is Componentsd
a "trigger" because the output retains its value until the input changes sufficiently to
trigger a change. In the non-inverting configuration, when the input is higher than a
certain chosen threshold, the output is high. When the input is below a different
(lower) chosen threshold, the output is low, and when the input is between the two
levels, the output retains its value. This dual threshold action is called hysteresis and
implies that the Schmitt trigger possesses memory and can act as a bistable
circuit (latch or flip-flop). There is a close relation between the two kinds of circuits:
a Schmitt trigger can be converted into a latch and a latch can be converted into a
Schmitt trigger.
Schmitt trigger devices are typically used in signal conditioning applications to

remove noise from signals used in digital circuits, particularly mechanical switch
bounce. They are also used in closed loop negative feedback configurations to
implement relaxation oscillators, used in function generators and switching power
supplies.
59
PROCEDURE:
60
CIRCUIT DIAGRAM:
MODEL GRAPH:
RESULT:
Thus the Schmitt trigger is simulated using PSpice.
61
Ex. No.: 14
Date: ANALYSIS OF POWER AMPLIFIER
AIM:
To design and test the performance of power amplifier.
APPARATUS REQUIRED:
S.No QUIPMENTS RANGE QUANTITY
1 Resistors
2 RPS (0-30)V 1
4 CRO (0-30)MHz 1
5 Capacitor 3.2nf 1
25pf 1
6 Bread board - 1
DESIGN EXAMPLE:
VCC= 12V; hfe = 200; f=1 KHz; I c = 2mA; Vce (sat) = 0.2v; VBB= - 2V,
RC = VCC - Vce (sat) / IC
RC = 12 – 0.2 / 2x10-3=5.9KΩ
(ii) To calculate R:
IB2(min)=IC2 / hfe= 2x10-3 / 200 = 10µ A
Select IB2 > IB1(min) (say 25µ A)
Then R = VCC – V BE (sat) / IB2
Therefore R= 12-0.7/25x10-6=452KΩ
(iii) To calculate C:
T=0.69RC
62
1x10-3= 0.69x452x103xC
C=3.2nf
To calculate R1 & R2:
VB1= {(VBB R1/ R1 +R2) + (VCE (sat) R2 / R1+R2)}
Since Q1 is in off state ,VB1 ≤ 0
Then (VBB R1/ R1 +R2) = (VCE (sat) R2 / R1+R2)
VBB R1 = VCE (sat) R2
2 R1 = 0.2 R2
Assume R1=10KΩ, then R2=100 KΩ
Consider, C1= 25pf (commutative capacitor)
THEORY:
An electronic amplifier is used for increasing the power of a signal. It does this
by taking energy from a power supply and controlling the output to match the input
signal shape but with a larger amplitude. In this sense, an amplifier may be
considered as modulating the output of the power supply.
PROCEDURE:
2. Give a negative trigger input to Q2.
3. Note the output of transistor Q2 and Q1.
4. Find the value of Ton and Toff.
63
CIRCUIT DIAGRAM:
MODEL GRAPH:
64
TABULATION:
S.NO Amplitude(V) Time

period(msec)
RESULT:
Thus the Power amplifier is designed and the performance is tested.
65
Ex. No.: 15
Date: VOLTAGE AND CURRENT TIME BASE CIRCUITS
AIM:
To simulate voltage and current time base circuits by using PSPICE.
APPARATUS REQUIRED:
1. PC
2. PSPICE software
THEORY:
A time base generator, or timebase, is a special type of function generator, an

electronic circuit that generates a varying voltage to produce a particular waveform.
Time base generators produce very high frequency sawtooth waves specifically
designed to deflect the beam in cathode ray tube (CRT) smoothly across the face of
the tube and then return it to its starting position.
Time bases are used by radar systems to determine range to a target, by

comparing the current location along the time base to the time of arrival of radio
echoes. Analog television systems using CRTs had two time bases, one for deflecting
the beam horizontally in a rapid movement, and another pulling it down the screen 60
times per second.Oscilloscopes often have several time bases, but these may be more
flexible function generators able to produce many waveforms as well as a simple
time base.
PROCEDURE:
66
CIRCUIT DIAGRAM:
VOLTAGE TIME BASE CIRCUIT
CURRENT TIME BASE CIRCUIT
67
MODEL GRAPH:
CURRENT TIME BASE CRCUIT
RESULT:
Thus the Voltage and Current time base circuits are simulated using Pspice.
Ex.No: 16 TWIN T OSCILLATOR
AIM:
To simulate the TWIN-T Oscillator using ORCAD PSPICE software.
SOFTWARE REQUIRED:
ORCAD PSPICE
PROCEDURE:
1. Draw the circuit as per the circuit diagram.
2. Create a edit simulation title.
3. Select the type of analysis.
4. Create a new simulation file.
5. Simulate the file.
CIRCUIT DIAGRAM:
V1 R1
3.3k
9
Q1
Q2N3904
C1 R5
50n 100
V
R2 R3
18k
C3 18k
47n
C4 C2
0V
22n 22n
R4
1.5k
0A
OUTPUT:
NETLIST:
*Libraries:
* Local Libraries :
* From [PSPICE NETLIST] section of pspiceev.ini file:
.lib "nom.lib"
*Analysis directives:
.TRAN 0 100s 0
.PROBE
.INC "twinteee-SCHEMATIC1.net"
**** INCLUDING twinteee-SCHEMATIC1.net ****
* source TWINTEEE
Q_Q1 N00024 N00042 0
Q2N3904 R_R1 N000051 N00024

3.3k
R_R2 N00042 N00031 18k
R_R3 N00031 N00024 18k
R_R4 0 N00039 1.5k
R_R5 N00292 0 100
C_C1 N00031 N00292 50n
C_C2 N00039 N00024 22n
C_C3 0 N00031 47n
C_C4 N00042 N00039 22n
V_V1 N000051 0 9
73

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Sri Shanmugha College of Engineering and Technology

Approved by AICTE, New Delhi and Affiliated to Anna University,

Department of Electronics and Communication Engineering

EC8461 - CIRCUITS AND SIMULATION INTEGRATED LABORATORY

DESIGN AND ANALYSIS OF THE FOLLOWING CIRCUITS

SIMULATION USING SPICE (Using Transistor):

CO 3 Design wave-shaping circuits.

CO 4 Design multi vibrators

Design and simulate feedback amplifiers, oscillators, tuned

CO PO, PSO Mappings

S.No EQUIPMENTS RANGE QUANTIT Y

1 Function generator (0-1)MHz 1

(i) To calculate RC:

(iii) To find input coupling capacitor (Ci):

(iv)To find output coupling capacitor (CO):

(v) To find Bypass capacitor (CE):

Design with feedback:

WITHOUT FEED BACK:

Negative feedback in general increases the bandwidth of the transfer function

Resistor 3k, 1.1 1

(i) To calculate RC:

(ii) To calculate R1&R2:

(iii) To calculate Resistance:

AC parameter with feedback network:

(i) Input Impedance:

(ii) Output impedance:

(iii) Emitter capacitor:

WITH FEED BACK

1. Connect the circuit as per the circuit diagram.

Thus voltage shunt feedback amplifier is designed and studied its

To design a RC phase shift oscillator and to find the frequency of

S. No RANGE QUANT ITY

Assume f=1 KHz, C=0.01µf

(ii) To find RE & RC:

(iii) To calculate R1 & R2:

VBB= VCC R2 / R1+ R2 ------ (2)

(iv) To calculate Coupling capacitors:

(i) XCi= {[hie + (1+hfe) RE] || RB }/ 10 = 0.12K

(iv) Feed back capacitor, XCF = Rf / 10

S.NO Amplitude Time Period (ms)

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 15V.

4. Frequency of oscillation is calculated by the formula f=1/T

5. Amplitude Vs time graph is drawn.

S.NO Amplitude Time Period (ms)

S.No RANGE QUANTITY

Design of feed back Network:

(i) Selection of RC:

(ii) Selection of RE:

(iv)Output capacitance (CO):

(v) Input capacitance (Ci):

(vi) By pass Capacitance (CE):

1. Connect the circuit as per the circuit diagram.

2. Set VCC = 12V.

4. Frequency of oscillation is calculated by the formula f=1/T

5. Verify it with theoretical frequency, f= 1/2∏ ( (L1+ L2)C ) Amplitude Vs time

S.NO Amplitude Time Period (ms)

To design and construct a Colpitt’s oscillator at the given operating

S.No EQUIPME NTS RANG E QUANTI TY

INCLUDING twinteee-SCHEMATIC1.net