Unit 5

Field Programmable Gate Arrays (FPGAs)

In 1985, a company called Xilinx introduced a completely new idea: combine the
user control and time to market of PLDs with the densities and cost benefits of gate
arrays. Customers liked it – and the FPGA was born. Today Xilinx is still the number-
one FPGA vendor in the world.

An FPGA is a regular structure of logic cells (or modules) and interconnect, which is
under your complete control. This means that you can design, program, and make
changes to your circuit whenever you wish.

With FPGAs now exceeding the 10 million gate limit (the Xilinx Virtex™-II FPGA is
the current record holder), you can really dream big.

1.1.1 FPGA Architecture

 Channel Based Routing

 Post Layout Timing
 Tools More Complex than CPLDs
 Fine Grained
 Fast register pipelining

Figure 1.4 Field Programmable Gate

Array Logic (FPGA)
There are two basic types of FPGAs: SRAM-based reprogrammable (Multi-time
Programmed MTP) and (One Time Programmed) OTP. These two types of FPGAs
differ in the implementation of the logic cell and the mechanism used to make
connections in the device.

The dominant type of FPGA is SRAM-based and can be reprogrammed as often as

you choose. In fact, an SRAM FPGA is reprogrammed every time it’s powered up,
because the FPGA is really a fancy memory chip. That’s why you need a serial
PROM or system memory with every SRAM FPGA.

Figure 1.5 Types of FPGA

In the SRAM logic cell, instead of conventional gates, an LUT determines the output
based on the values of the inputs. (In the “SRAM logic cell” diagram above, six
different combinations of the four inputs determine the values of the output.) SRAM
bits are also used to make connections.

OTP FPGAs use anti-fuses (contrary to fuses, connections are made, not “blown,”
during programming) to make permanent connections in the chip. Thus, OTP FPGAs
do not require SPROM or other means to download the program to the FPGA.
However, every time you make a design change, you must throw away the chip! The
OTP logic cell is very similar to PLDs, with dedicated gates and flip-flops.

Table 1.1: Comparison between OTP FPGA and MTP FPGA

Property OTP FPGA MTP FPGA
Lower (current flows in
Speed Higher (current flows in wire)
transistors)
Size smaller Larger
Power Consumption Lower Higher
Working Environment
Radiation hardened NO radiation hardened
(Radiation)
Design Cycle Programmed once only Many times
Price Almost the same Almost the same
Less (2 Chips, FPGA &
Reliability More (single Chip)
PROM)
Security More secure Less secure
Complex Programmable Logic Devices (CPLDs)
Complex programmable logic devices (CPLDs) extend the density of SPLDs.
The concept is to have a few PLD blocks or macrocells on a single device with a general-purpose
interconnect in-between. Simple logic paths can be implemented within a single block. More
sophisticated logic requires multiple blocks and uses the general-purpose interconnect in-between to
make these connections.
1.1.3.1 CPLD Architecture
Central, Global Interconnect
Simple, Deterministic Timing
Easily routed
PLD Tools and only interconnect
Wide, fast complex gating

Logic Device (CPLD) 

CPLDs are great at handling wide and complex gating at blistering speeds – 5
nanoseconds, for example, which is equivalent to 200 MHz. The timing model for CPLDs is easy to
calculate so before starting your design you can calculate your input-to-output speeds.
Why use a CPLD?
CPLDs enable ease of design, lower development costs, and more product revenue for your money, and
the opportunity to speed your products to market.
1.2.1 Ease of Design: CPLDs offer the simplest way to implement a design. Once a design has been
described, by schematic and/or HDL entry, you simply use CPLD development tools to optimize, fit, and
simulate the design. The development tools create a file that is used to customize (that is, program) a
standard off-the-shelf CPLD with the desired functionality. This pro- vides an instant hardware prototype
and allows the debugging process to begin.
If modifications are needed, you can enter design changes into the CPLD
development tool, and re-implement and test the design immediately.
Lower Development Costs: CPLDs offer very low development costs.
Because CPLDs are re-programmable, you can easily and very inexpensively
change your designs. This allows you to optimize your designs and continue to add new features to
enhance your products. CPLD development tools are relatively inexpensive (or in the case of Xilinx, free).
Traditionally, designers have had to face large cost penalties such as rework, scrap, and development
time. With CPLDs, you have flexible solutions, thus avoiding many traditional design pitfalls.
More Product Revenue: CPLDs offer very short development cycles, which means your products get
to market quicker and begin generating revenue sooner. Because CPLDs are re-programmable,
products can be easily modified using ISP over the Internet. This in turn allows you to easily introduce
additional features and quickly generate new revenue. (This also results in an expanded time for
revenue).
Thousands of designers are already using CPLDs to get to market quicker and stay in the market
longer by continuing to enhance their products even after they have been introduced into the field.
CPLDs decrease TTM and extend TIM.
Reduced Board Area: CPLDs offer a high level of integration (that is, a large number of system gates
per area) and are available in very small form factor packages. This provides the perfect solution for
designers whose products which must fit into small enclosures or who have a limited amount of circuit
board space to implement the logic design.
Cost of Ownership: Cost of Ownership can be defined as the amount it costs to maintain, fix, or
warranty a product.
 For instance, if a design change requiring hardware rework must be made to a few prototypes, the cost
might be relatively small. However, as the number of units that must be changed increases, the cost can
become enormous.
Because CPLDs are re-programmable, requiring no hardware rework, it costs much less to make
changes to designs implemented using them. Therefore cost of ownership is dramatically
reduced.
Don’t forget that the ease or difficulty of design changes can also affect opportunity costs.
Engineers who spend time fixing old designs could be working on introducing new products and
features ahead of the competition.
There are also costs associated with inventory and reliability. PLDs can reduce inventory
costs by replacing standard discrete logic devices. Standard logic has a predefined function. In a
typical design, lots of different types have to be purchased and stocked. If the design is changed,
there may be excess stock of superfluous devices. This issue can be alleviated by using PLDs.
You only need to stock one device; if your design changes, you simply reprogram. By utilizing one
device insteadof many, your board reliability will increase by only picking and placing one device
instead of many.

Reliability can a lso be increased by using ultra-low-power CoolRunner CPLDs. Theirlower heat
dissipation and lower power operation leads to decreased FIT.

Types of FPGAs Based on Applications:

Field Programmable Gate Arrays are classified into three types based on applications such as Low-end FPGAs,
Mid-range FPGAs and high-end FPGAs.
Low End FPGAs:

These types of FPGAs are designed for low power consumption, low logic density and low complexity per chip.
Examples of low end FPGAs are Cyclone family from Altera, Spartan family from Xilinx, fusion family from
Microsemi and the Mach XO/ICE40 from Lattice semiconductor.

Mid Range FPGAs:

These types of FPGAs are the optimum solution between the low-end and high- end FPGAs and these are
developed as a balance between the performance and the cost. Examples of Mid range FPGAs are Arria from
Altera, Artix-7/Kintex-7 series from Xlinix, IGL002 from Microsemi and ECP3 and ECP5 series from Lattice
semiconductor.

High End FPGAs:

These types of FPGAs are developed for logic density and high performance. Examples of High end FPGAs are a
Stratix family from Altera, Virtex family from Xilinx, Speedster 22i family from Achronix, and ProASIC3 family from
Microsemi.

Xilinx FPGA Architecture:

FPGA, which stands for field-programmable gate array, can be used to solve any computable issue. It is an
integrated circuit that may be customized after manufacturing by a client or a designer. To be more specific,
FPGAs (Field Programmable Gate Arrays) are semiconductor devices that consist of a matrix of CLBs or
customizable logic blocks linked by programmable interconnects.

Here, in this article, we will discuss the FPGAs also known as Field Programmable Gate Arrays, their work, and
Architecture. This post will also introduce you to Xilinx. Xilinx is considered a leading company in this field. it
offers comprehensive solutions including FPGA devices, powerful software, and configurable, ready-to-use IP
cores for the marketplace and variety of applications.

Xilinx FPGAs are well known for running a standard embedded operating system, such as Linux or VxWorks. And
implementing processor peripherals in programmable logic. The FPGA families Virtex-II Pro, Virtex-4, Virtex-5, and
Virtex-6, which have up to two embedded IBM PowerPC cores, are specially made for system-on-chip (SoC)
designers.
FPGAs Architecture

FPGAs from Xilinx are hybrid computation systems with Block RAMs, programmable fabric, DSP Slices, and PCI
Express support. Just Because all of these compute resources can be accessed at the same time, they enable
scalability and pipelining of applications throughout the entire platform. SD Accel is a Xilinx utility that allows
OpenCL programs to target and enable these computational resources.

Components : The basic structure of FPGAs is made of the following components:

1. A look-up table or LUT: This component is responsible for performing logic operations.
2. Flip-Flop: The result of the LUT is stored in this register element.
3. Wires: These are the elements that connect the elements.
4. I/O pads: These physical ports allow data to enter and exit the FPGA.

Here, the basic architecture of FPGA is shown in the following image which is an outcome of integrating these
pieces.

FPGA components

The main features of modern FPGA structure are combined with extra computational and data storage blocks to
enhance the device’s computational density and efficiency. Here, some additional points are given below to
understand the concept better.
1. Embedded memories for distributed data storage
2. PLLs or Phase-locked loops for driving the FPGA fabric at different clock rates
3. High-speed serial transceivers
4. Off-chip memory controllers
5. Multiply-accumulate block

Here, in modern FPGA design, the combination of these pieces is shown in the image, allowing the FPGA to
implement any software method that is executing on a processor.

Applications:

FPGAs are a suitable match for a variety of markets due to their working nature and programmability. In this field,
Xilinx is considered the most trusted company, which offers the most detailed and effective solutions including
FPGA devices, configurable and powerful software ready-to-use IP cores for applications like Aerospace,
Automotive systems, Broadcast and Pro-AV, Defence, consumer electronics, Data centers, industrials, and high
data storage related applications and so on.

Here, we’ve tried to describe some of the most common applications for FPGAs, which are listed below:
1. Automotive: The Xilinx Automotive platform is essential in powering highly advanced AD modules, which
are progressively demanding better performance and capacity to enable high-speed data processing, pre-
processing, distribution (DAPD), and computation acceleration.
2. FPGA-Based ASIC Prototyping: FPGA-based ASIC prototyping enables quick and precise SoC system
modeling and embedded software verification. It provides high-performance FPGAs for better design
verification. Also, reduce the amount of board area required and the intricacy of the board. It gives a versatile
I/O solution to enable the creation of a single device. And Provide advanced debugging, simulation
acceleration, and interactive design tweaking
3. Aerospace and Defence: Xilinx provides commercial, defense, and space-grade system-level solutions to
the aerospace and defense industries, including industry-leading FPGA, SoC, and ACAP devices, sophisticated
IP solutions, and the next generation of design tools.
4. Medical: The Virtex FPGA and Spartan® FPGA families can be used to address a variety of processing,
display, and I/O interface needs in diagnostic, monitoring, and therapeutic applications.
5. Consumer Electronics: The Xilinx Solution provides Cost-effective and energy-efficient technologies that
enable system-on-chip (SoC) designs, High bandwidth and throughput to accommodate expanding
interconnect standards as well as Internet-enabled applications.
6. Broadcast & Professional AV: With Broadcast-focused Design Platforms and solutions for high-end
professional broadcast systems, you can adapt to changing requirements faster and extend product life cycles.
Xilinx platforms can quickly adapt to new audio and video technologies, provide access to AV-over-IP networks
with lossy and lossless codecs as needed, and integrate multimedia pipelines with the most cutting-edge
AI/ML approaches in cost-effective devices.
7. Data Center: Xilinx FPGAs are best for massively parallel data processing. This functionality reduces the
total cost of ownership of edge computing devices while increasing performance by lowering latency. Artificial
intelligence developments, increasingly complex workloads, and the availability of unstructured data require
rapid data center evolution. With customized computing, storage, and networking acceleration, the Xilinx
platform is enabling the evolution.
8. Computing and Data Storage solutions: Because of customizable Data-paths and storage structures, as
well as a powerful developer toolset, Xilinx FPGA enhanced applications can enable efficient hardware and
software implementations with the flexibility to adapt to new requirements without sacrificing performance or
energy efficiency.
9. Wired and wireless Communications: In both wired and wireless communications, FPGA chips are
employed. They are utilized in backplanes in wired communications and cellular base stations in wireless
communications. FPGAs are now employed in networking solutions and to address WiMAX, 5G/6G,
and HSDPA requirements.
10. Industrial: For a wide range of applications such as industrial imaging and surveillance, industrial
automation, and Xilinx FPGAs and focused design platforms for Industrial, Scientific, and Medical allows
greater flexibility, faster time-to-market, and lower total non-recurring engineering costs.
11. Security: From access control to surveillance and safety systems, Xilinx has solutions to all the changing
needs of security applications.

FPGAs are being used in devices for quite a long time; they are the most cost-effective solutions, with higher
performance and programmability, because of their productivity, they are being used in a wide range of
applications.

Xilinx is at the top of this industry because of its great quality and low-cost devices. Xilinx provides complete and
reliable solutions regarding FPGA devices and the wide range of devices offered by Xilinx
Xilinx XC 3000:
Features:
•Complete line of four related Field Programmable Gate Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
•Ideal for a wide range of custom VLSI design tasks
-Replaces TTL, MSI, and other PLD logic
-Integrates complete sub-systems into a single package
-Avoids the NRE, time delay, and risk of conventional masked gate arrays
•High-performance CMOS static memory technology
-Guaranteed toggle rates of 70 to 370 MHz, logic delays from 7 to 1.5 ns
-System clock speeds over 85 MHz
-Low quiescent and active power consumption
•Flexible FPGA architecture
-Compatible arrays ranging from 1,000 to 7,500 gate complexity
-Extensive register, combinatorial, and I/O capabilities
-High fan-out signal distribution, low-skew clock nets
-Internal 3-state bus capabilities
-TTL or CMOS input thresholds
-On-chip crystal oscillator amplifier
•Unlimited reprogrammability
-Easy design iteration
-In-system logic changes
•Extensive packaging options
-Over 20 different packages
-Plastic and ceramic surface-mount and pin-grid- array packages
-Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options
•Ready for volume production
-Standard, off-the-shelf product availability
-100% factory pre-tested devices
Complete Development System
-Schematic capture, automatic place and route
-Logic and timing simulation
-Interactive design editor for design optimization
-Timing calculator
-Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others
Additional XC3100A Features:
•Ultra-high-speed FPGA family with six members
-50-85 MHz system clock rates
-190 to 370 MHz guaranteed flip-flop toggle rates
-1.55 to 4.1 ns logic delays
•High-end additional family member in the 22 X 22 CLB array-size XC3195A device
•8 mA output sink current and 8 mA source current
•Maximum power-down and quiescent current is 5 mA
•100% architecture and pin-out compatible with other XC3000 families
•Software and bitstream compatible with the XC3000, 7
XC3000A, and XC3000L families
XC3100A combines the features of the XC3000A and XC3100 families:
•Additional interconnect resources for TBUFs and CE inputs
•Error checking of the configuration bitstream
•Soft startup holds all outputs slew-rate limited during initial power-up
•More advanced CMOS process
Low-Voltage Versions Available
•Low-voltage devices function at 3.0 - 3.6 V
•XC3000L - Low-voltage versions of XC3000A devices
•XC3100L - Low-voltage versions of XC3100A devices
Introduction:
XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density,
digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed
of a configuration program store plus three types of config- urable elements: a perimeter of I/O Blocks (IOBs), a
core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA
is shown in Figure 2. The development system provides schematic capture and auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The
design editor is used for interactive design optimization, and to compile the data pattern that represents the
configuration program.
The FPGA user logic functions and interconnections are determined by the configuration program data stored in
internal static memory cells. The program can be loaded in any of several modes to accommodate various system
requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of
program data at power-up. The companion XC17XX Serial Configu- ration PROMs provide a very simple serial
configuration program storage in a one-time programmable package.
The XC3000 Field Programmable Gate Array families pro- vide a variety of logic capacities, package styles,
tempera- ture ranges and speed grades.
XC3000 Series Overview:
There are now four distinct family groupings within the XC3000 Series of FPGA devices:
•XC3000A Family
•XC3000L Family
•XC3100A Family
•XC3100L Family
All four families share a common architecture, develop- ment software, design and programming methodology,
and also common package pin-outs. An extensive Product Description covers these common aspects.
Detailed parametric information for the XC3000A, XC3000L, XC3100A, and XC3100L product families is then
provided. (The XC3000 and XC3100 families are not recommended)
Here is a simple overview of those XC3000 products cur- rently emphasized:
•XC3000A Family — The XC3000A is an enhanced version of the basic XC3000 family, featuring additional
interconnect resources and other user-friendly enhancements.
•XC3000L Family — The XC3000L is identical in architecture and features to the XC3000A family, but operates at a
nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power
applications.
•XC3100A Family — The XC3100A is a
performance-optimized relative of the XC3000A family. While both families are bitstream and footprint
compatible, the XC3100A family extends toggle rates to 370 MHz and in-system performance to over 80 MHz. The
XC3100A family also offers one additional array size, the XC3195A.
XC3100L Family — The XC3100L is identical in architectures and features to the XC3100A family, but operates at a
nominal supply voltage of 3.3V
Improvements in the XC3000A and XC3000L Families:
The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family:
The XC3000A and XC3000L families have additional inter- connect resources to drive the I-inputs of TBUFs driving
horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two
additions result in more efficient and faster designs when horizontal Longlines are used for data bussing.
During configuration, the XC3000A and XC3000L devices check the bit-stream format for stop bits in the
appropriate positions. Any error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device starts up in user mode, the first activation of the
outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce
when all out-puts are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in the
XC3000 fam- ily, determined by the individual configuration option.
Improvements in the XC3100A and XC3100L Families
Based on a more advanced CMOS process, the XC3100A and XC3100L families are architecturally-identical,
perfor- mance-optimized relatives of the XC3000A and XC3000L families. While all families are footprint
compatible, the XC3100A family extends achievable system performance beyond 85 MHz

X7068

Configurable Logic Block:

The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks arranged in 8
rows and 8 columns. The development system is used to compile the configuration data which is to be loaded
into the internal configuration memory to define the operation and interconnection of each block. User definition
of CLBs and their interconnecting networks may be done by auto- matic translation from a schematic-capture
logic diagram or optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops, and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input (K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect resources adjacent to the blocks. Each CLB also has
two outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from the function F or G outputs of the combinatorial logic,
or the block input, DI. Both flip-flops in each CLB share the asyn- chronous RD which, when enabled and High, is
dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the
configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops’
present states and inhibits response to the data-in or combinatorial function inputs on a CLB. The user may
enable these control inputs and select their sources. The user may also select the clock net input (K), as well as its
active sense within each CLB. This programmable inversion eliminates the need to route both phases of a clock
signal throughout the device.

0
 Each CLB includes a combinatorial logic section, two flip-flops and a
program memory controlled multiplexer selection of function. It has the
following:
- five logic variable inputs A, B, C, D, and E
- a direct data in DI
- an enable clock EC
- a clock (invertible) K
- an asynchronous direct RESET RD
- two outputs X and Y

Flexible routing allows use of common or individual CLB clocking.

The combinatorial-logic portion of the CLB uses a 32 by 1 look-up table to implement
Boolean functions. Variables selected from the five logic inputs and two internal
block flip-flops are used as table address inputs. The combinato- rial propagation
delay through the network is independent of the logic function generated and is
spike free for single input variable changes. This technique can generate two
independent logic functions of up to four variables each as shown in Figure 6a, or a
single function of five variables as shown in Figure 6b, or some functions of seven
variables as shown in Figure 6c. Figure 7 shows a modulo-8 binary counter with
parallel enable. It uses one CLB of each type. The partial functions of six or seven
variables are imple- mented using the input variable (E) to dynamically select
between two functions of four different variables. For the two functions of four
variables each, the independent results (F and G) may be used as data inputs to
either flip-flop or either logic block output. For the single function of five variables
and merged functions of six or seven vari- ables, the F and G outputs are identical.
Symmetry of the F and G functions and the flip-flops allows the interchange of CLB
outputs to optimize routing efficiencies of the networks interconnecting the CLBs
and IOBs.

Programmable Interconnect:
Programmable-interconnection resources in the Field Pro- grammable Gate Array
provide routing paths to connect inputs and outputs of the IOBs and CLBs into logic
net- works. Interconnections between blocks are composed of a two-layer grid of
metal segments. Specially designed pass transistors, each controlled by a
configuration bit, form pro- grammable interconnect points (PIPs) and switching
matri- ces used to implement the necessary connections between selected metal
segments and block pins.The development system provides automatic routing of
these interconnections. Interactive routing is also available for design optimization.
The input of the CLBs or IOBs are multiplexers which can be pro-grammed to select
an input network from the adjacent interconnect segments. Since the switch
connections to block inputs are unidirectional, as are block outputs,they are usable
) only for block input connection and not for routing.
 Three types of metal resources are provided to accommo- date various network
interconnect requirements.
•General Purpose Interconnect
•Direct Connection
•Longlines (multiplexed busses and wide AND gates)

6a. Combinatorial Logic Option FG generates two func- tions of four variables each.
One variable, A, must be common to both functions. The second and third variable
can be any choice of B, C, QX and QY. The fourth vari- able can be any choice of D or
E.
6b. Combinatorial Logic Option F generates any function of five variables: A, D, E and
two choices out of B, C, QX, QY.
6c. Combinatorial Logic Option FGM allows variable E to select between two
functions of four variables: Both have common inputs A and D and any choice out of
B, C, QX and QY for the remaining two variables. Option 3 can then implement some
functions of six or seven variables.

I/O Block:
Each user-configurable IOB shown in Figure 4, provides an interface between the
external package pin of the device and the internal user logic. Each IOB includes both
regis- tered and direct input paths. Each IOB provides a program- mable 3-state
output buffer, which may be driven by a registered or direct output signal.
Configuration options allow each IOB an inversion, a controlled slew rate and a high
impedance pull-up. Each input circuit also provides input clamping diodes to provide
electrostatic protection, and circuits to inhibit latch-up produced by input currents.
Each IOB includes input and output storage elements and I/O options
selected by configuration memory cells. A choice of two clocks is
available on each die edge. The polarity of each clock line (not each flip-
flop or latch) is programmable. A clock line that triggers the flip-flop on
the rising edge is an active Low Latch Enable (Latch transparent) signal
and vice versa. Passive pull-up can only be enabled on inputs, not on
outputs. All user inputs are programmed for TTL or CMOS thresholds.

The input-buffer portion of each IOB provides threshold detection to translate

external signals applied to the pack- age pin to internal logic levels. The global input-
buffer threshold of the IOBs can be programmed to be compatible with either TTL or
CMOS levels. The buffered input signal drives the data input of a storage element,
which may be configured as either a flip-flop or a latch. The clocking polarity
(rising/falling edge-triggered flip-flop, High/Low transparent latch) is programmable
for each of the two clock lines on each of the four die edges. Note that a clock line
driving a rising edge-triggered flip-flop makes any latch driven by the same line on

)
 the same edge Low-level trans- parent and vice versa (falling edge, High
transparent). All Xilinx primitives in the supported schematic-entry pack- ages,
however, are positive edge-triggered flip-flops or High transparent latches. When
one clock line must drive flip-flops as well as latches, it is necessary to compensate
for the difference in clocking polarities with an additional inverter either in the flip-
flop clock input or the latch-enable input. I/O storage elements are reset during
configuration or by the active-Low chip RESET input. Both direct input (from IOB pin
I) and registered input (from IOB pin Q) sig- nals are available for interconnect.
For reliable operation, inputs should have transition times of less than 100 ns and
should not be left floating. Floating CMOS input-pin circuits might be at threshold
and produce oscillations. This can produce additional power dissipation and system
noise. A typical hysteresis of about 300 mV reduces sensitivity to input noise. Each
user IOB includes a programmable high-impedance pull-up resistor, which may be
selected by the program to provide a constant High for otherwise undriven package
pins. Although the Field Pro- grammable Gate Array provides circuitry to provide
input protection for electrostatic discharge, normal CMOS han- dling precautions
should be observed.
Flip-flop loop delays for the IOB and logic-block flip-flops are short, providing good
performance under asynchro- nous clock and data conditions. Short loop delays
minimize the probability of a metastable condition that can result from assertion of
the clock during data transitions. Because of the short-loop-delay characteristic in
the Field Program- mable Gate Array, the IOB flip-flops can be used to syn- chronize
external signals applied to the device. Once synchronized in the IOB, the signals can
be used internally without further consideration of their clock relative timing, except
as it applies to the internal logic and routing-path delays.
IOB output buffers provide CMOS-compatible 4-mA source-or-sink drive for high
fan-out CMOS or TTL- com- patible signal levels (8 mA in the XC3100A family). The
net- work driving IOB pin O becomes the registered or direct data source for the
output buffer. The 3-state control signal (IOB) pin T can control output activity. An
open-drain output may be obtained by using the same signal for driving
theoutput and 3-state signal nets so that the buffer output is enabled only for a
Low.
Configuration program bits for each IOB control features such as optional output
register, logic signal inversion, and 3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 4 control the following options.

) •Logic inversion of the output is controlled by one configuration program bit per
IOB.
 •Logic 3-state control of each IOB output buffer is determined by the states of
configuration program bits that turn the buffer on, or off, or select the output
buffer 3-state control interconnection (IOB pin T). When this IOB output control
signal is High, a logic one, the buffer is disabled and the package pin is high
impedance. When this IOB output control signal is Low, a logic zero, the buffer is
enabled and the package pin is active. Inversion of the buffer 3-state control-logic
sense (output enable) is controlled by an additional configuration program bit.
•Direct or registered output is selectable for each IOB. The register uses a positive-
edge, clocked flip-flop. The clock source may be supplied (IOB pin OK) by either of
two metal lines available along each die edge. Each of these lines is driven by an
invertible buffer.
•Increased output transition speed can be selected to improve critical timing.
Slower transitions reduce capacitive-load peak currents of non-critical outputs and
minimize system noise.
•An internal high-impedance pull-up resistor (active by default) prevents
unconnected inputs from floating.
Unlike the original XC3000 series, the XC3000A, XC3000L, XC3100A, and XC3100L
families include the Soft Startup feature. When the configuration process is fin-
ished and the device starts up in user mode, the first activa- tion of the outputs is
automatically slew-rate limited. This feature avoids potential ground bounce when
all outputs are turned on simultaneously. After start-up, the slew rate of the
individual outputs is determined by the individual configuration option.

Summary of I/O Options

• Inputs
- Direct
- Flip-flop/latch
- CMOS/TTL threshold (chip inputs)
- Pull-up resistor/open circuit
• Outputs
- Direct/registered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable (inverse)

XC 4000X:
) System featured Field-Programmable Gate Arrays
 -SelectRAMTM memory: on-chip ultra-fast RAM with
-synchronous write option
-dual-port RAM option
-Abundant flip-flops
-Flexible function generators
-Dedicated high-speed carry logic
-Wide edge decoders on each edge
-Hierarchy of interconnect lines
-Internal 3-state bus capability
-Eight global low-skew clock or signal distribution networks
•System Performance beyond 80 MHz
•Flexible Array Architecture
•Low Power Segmented Routing Architecture
•Systems-Oriented Features
-IEEE 1149.1-compatible boundary scan logic support
-Individually programmable output slew rate
-Programmable input pull-up or pull-down resistors
-12 mA sink current per XC4000E output
•Configured by Loading Binary File
-Unlimited re-programmability
•Read Back Capability
-Program verification
-Internal node observability
•Backward Compatible with XC4000 Devices
•Development System runs on most common computer platforms
-Interfaces to popular design environments
-Fully automatic mapping, placement and routing
-Interactive design editor for design optimization
Low-Voltage Versions Available:
•Low-Voltage Devices Function at 3.0 - 3.6 Volts
•XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices
Additional XC4000X Series Features:
•High Performance — 3.3 V XC4000XL
•High Capacity — Over 180,000 Usable Gates
•5 V tolerant I/Os on XC4000XL
•0.35 m SRAM process for XC4000XL
•Additional Routing Over XC4000E
-almost twice the routing capacity for high-density designs
•Buffered Interconnect for Maximum Speed Blocks
•Improved VersaRingTM I/O Interconnect for Better Fixed
-Fully PCI compliant (speed grades -2 and faster)
Pinout Flexibility
12 mA Sink Current Per XC4000X Output
•Flexible New High-Speed Clock Network
) -Eight additional Early Buffers for shorter clock delays
 -Virtually unlimited number of clock signals
•Optional Multiplexer or 2-input Function Generator on Device Outputs
•Four Additional Address Bits in Master Parallel Configuration Mode

)
 Introduction:
XC4000 Series high-performance, high-capacity Field Pro- grammable Gate Arrays
(FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost,
long development cycle, and inherent risk of a conventional masked gate array.
The result of thirteen years of FPGA design experience and feedback from thousands
of customers, these FPGAs com- bine architectural versatility, on-chip Select-RAM
memory with edge-triggered and dual-port modes, increased speed, abundant
routing resources, and new, sophisticated software to achieve fully automated
implementation of complex, high-density, high-performance designs.
XC4000E and XC4000X SeriesCompared to the XC4000:
For readers already familiar with the XC4000 family of Xil- inx Field Programmable
Gate Arrays, the major new fea- tures in the XC4000 Series devices are listed in this
section. The biggest advantages of XC4000E and XC4000X devices are significantly
increased system speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000X devices also offer many new routing
features, including special high-speed clock buffers that can be used to capture input
data with minimal delay.
Any XC4000E device is pinout- and bitstream-compatible with the corresponding
XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new features, an XC4000E
bitstream cannot be loaded into an XC4000 device.
XC4000X Series devices are not bitstream-compatible with equivalent array size
devices in the XC4000 or XC4000E families .however equivalent array size devices
such as the XC4025,XC4025E,XC4028EX, and XC4028XL,are pinout-compatible.
Improvements in XC4000E and XC4000X:
Increased System Speed
XC4000E and XC4000X devices can run at synchronous system clock rates of up to 80
MHz, and internal perfor- mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both device processing and
system architecture. XC4000 Series devices use a sub-micron multi-layer metal
process. In addition, many architectural improvements have been made, as
described below.
The XC4000XL family is a high performance 3.3V family based on 0.35 SRAM
technology and supports system speeds to 80 MHz.
PCI Compliance
XC4000 Series -2 and faster speed grades are fully PCI compliant. XC4000E and
XC4000X devices can be used to implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati- cally. Some parameters,
such as the delay on the carry chain through a single CLB (TBYP), have improved by
asmuch as 50% from XC4000 values. See “Fast Carry Logic” on page 18 for more
information.
Select-RAM Memory: Edge-Triggered, Synchro- nous RAM Modes
The RAM in any CLB can be configured for synchronous, edge-triggered, write
) operation. The read operation is not affected by this change to an edge-triggered
write.
 Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with
simultaneous Read/Write.
The function generators in each CLB can be configured as either level-sensitive
(asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM,
edgetriggered (synchronous) dual-port RAM, or as combinational logic.
Configurable RAM Content:
The RAM content can now be loaded at configuration time,so that the RAM starts up
with user-defined data
H- Function generator:
Incurrent XC40000series devices,the H function generator is more versatile than im
the original XC4000.Its input can come not only from the F and G function generators
but also from up to three of the four control input lines. The H function generator
can thus be totally or partially independent of the other two function generators,
increasing the maximum capacity of the device.
IOBClockEnable:
The two flipflops in each IOB have a common clock enable input,which through
configuration can be activated individually for the input or output flip-flop or both.
This clock enable operates exactly like the EC pin on the XC4000CLB.This new
feature makes the IOBs more versatile, and avoids the need for clock gating.
OutputDrivers:
The output pull-up structure defaults to a TTL-liketotem-pole. This driver is an n-
channel pulltransistor,pulling to a voltage one transistor threshold below Vcc, just
like the XC4000family outputs.Alternatively,XC4000Series devices can be globally
configured with CMOS out-puts,with p-channel pull-up transistors pulling to
Vcc.Also,the configurable pull-up resistor in the XC4000 Series is a p-channel
transistor that pulls to Vcc, whereas in the original XC4000 family it is an n-channel
transistor that pulls to a voltage one transistor threshold below Vcc.