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Analysis of WISTRON OEM

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52 views13 pages

Analysis of WISTRON OEM

Uploaded by

Kyaw Thet Naing
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Laptop Chip Level Repair Guide 261

Chapter 11

Analysis of WISTRON OEM


Laptop Mainboard Circuit

The circuit and sequence of Wistron are not too many features, it can also be
said that its feature is quite satisfactory. The RTC circuit is similar to those of
the Quanta, the batter}' is usually not chargeable; the power-on sequence is the
Intel 'standard sequence. This chapter is not much introduced the RTC circuit
and the power-on sequence. Mainly, to explain the protective isolation and the
standby circuit.Then.as Wistron HBLJ16-1.2 an example to analyze the
protective isolation and the standby circuit.

11.1: Analysis of Wistron HBU16-1.2 Protective


Isolation Circuit
Insert the adapter, producing AD_JK, added to the S pole of U1, though the
partial pressure of R2 and RI produced the low level of 6.3V, control U1
conducted and produced AD+ (when inserted the adapter. because EC is no
power, AD_OFF is low level; only when the system program control forced to
discharged the battery, then EC will send the high level of AD_OFF), is shown
in figure 11-1.

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Figure 11-1: The screenshot of AD+ production circuit


AD+ produced the small current common point DCBATOUT through U2 body
diode, 18.3V, is shown in figure 11-2.

Figure 11-2: The production of the small current common point


AD+ is added to the G pole of U7, makes it cut off, the battery is isolated, is
shown in figure 11-3.

Figure 11-3: The screenshot of the battery isolation circuit

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AD+ supplies the power to DCIN of the charge chip U44 (MAX8731) and
divides into the voltage to ACIN, is shown in figure 11-4.

Figure 11-4: The screenshot of DCIN and ACIN circuit


When DCIN is power on, U44 outputs 5.4V MAX8731_LDO from LDO pin is
shown in figure11-5. About the figure 11-6, is the relationship between DCIN
and LDO of MAX8731 internal block diagram.

Figure 11-5: LDO output

Figure 11-6: The internal principle diagram of LDO production

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In the data manual of MAX8731, the screenshot of the electrical characteristic


description about DCIN effective value is shown in figure 11-7. DCIN effective
value is 8-26V, the under-voltage lockout value is 7.4V (typical value).

Figure 11-7: The screenshot of the electrical characteristic description about


DCIN threshold value in the data manual of MAX8731
MAX8731_LDO supplies the power to VCC pin through R204, is shown in
figure 11-8.

Figure 11-8: The circuit screenshot of LDO supply power to VCC


When VCC is power on, 4.096V reference voltage REF produced by the
MAX8731 internal, is shown in figure 11-9.
The ACOK pin definition is: AC Detect Output. This open-drain output is high
impedance when ACIN is greater than REF/2. The ACOK output remains low
when the MAX8731 is powered down. Connect a 10kΩ pull up resistor from
VCC to ACOK.
ACIN compared with the half of REF in the internal, when ACIN is greater than
REF/2(2.048V), ACIN open drain output, is shown in figure 11-10.

Figure 11-9: The internal principle diagram of the production of MAX8731


reference voltage

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Figure 11-10: The screenshot of ACOK output principle of MAX8731


As long as AD+ voltage is higher than 17.767V,ACIN will be greater than
2.048V,ACOK Will open drain output ACAV_IN, is shown in figure 11-11.The
calculation process is shown in figure 11-12.

Figure 11-11: The screenshot of ACOK output ACAV_IN

ACAV_IN is divided into the voltage by MAX8731_LDOto be 3.3V high level


by MAX873l_LDO. Through Q3 to produce the low level of AD_IN# to EC (as
the adapter test signal of EC), is shown in figure 11-13.
The other path controls 3-4 pin conducted of U3, makes R183 grounded. The
small current common point through R182 and R183 to form partial pressure,
and produces about 6V voltage to send to 4 pin (G pole) of U2, the S pole of U2
is 18.3V.the G pole is 6.1V,U2 channel is fully opened, AD+ directly flows to
the common point, producing the large current common point, is shown in
figure 11-14.

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Figure 11-12: The screenshot of AD+ threshold value calculation

Figure 11-13: The screenshot of the adapter test signal production of EC

Figure 11-14: The screenshot of the large current common point production
circuit

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11.2: Analysis of Wistron HBU 16-1.2 Standby


Circuit
After the common point voltage DCBATOUT producing, input to supply the
power to VIN of the standby chip U30.is shown in figure 11-15.

Figure 11-15: The circuit diagram of VIN supply power to U30


The standby chip is using TPS51125. When it got VIN, because ENO is grounded
through 820K resistance, set the linear voltage opened automatically, but close VCLK, is
shown in figure 11-16.

Figure 11-16: The screenshot of TPS51125 circuit

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According to TPS51125, working principle analyzed in the 9.2.2 section. After


TPS51125 getting VIN and ENO, the chip outputs +3VL, and renamed to be
+3VL_KBC, is shown in figure 11-17. +3VL_KBC is supplied to EC as the
standby voltage, is shown in figure 11-18.

Figure 11-18: The screenshot of EC standby power supply


After EC getting power supply, to supply the voltage to X2, crystal oscillator starts,
and sends to EC standby clock 32.768 kHz, is shown in figure 11-19.

Figure 11-19: EC standby clock circuit

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+3VL_KBC pulled up VCC_POR#, as the standby reset of EC, is shown in


figure 11-20.

Figure 11-20: The principle of EC reset production


After the standby condition of EC being satisfied, reads ROM (U25) through
SPI bus of 86,87,90,92 pin (shown in figure 11-21).ROM circuit is shown in
figure 11-22.the power supply of U25 is also came from +3VL_ KBC.

Figure 11-21: SPI bus pin of EC

Figure 11-22: The screenshot of U25 circuit

After EC reading the program normally, will configured their pin. Then EC
identifies the adapter insert test signal AD_IN# of 93 pin, is shown in figure 11-
23.
EC detects that the low level of the adapter is inserted an indication signal, then
sends automatically the high level of PWR_S5_EN, is shown in figure 11-24.

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Figure 11-23: The adapter test signal of EC

Figure 11-24: E sends PWR_D5_EN


PWR_S5_EN controls Q42 conduction, Q40 and Q41 will cut off, is shown in figure
11- 25. 51125_ENTRIP1 and 51125_ENTRIP2 are cannot grounded directly, it just can
be grounded through R498 and R508.

Figure 11-25: The screenshot of the circuit controlled by PWR_S5_EN

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51125_ENTRIP1 and 51225_ENTRIP2 connected to 1 pin and 6 pin of


TPS51125. According to the pin definition of TPS51125 in the 9.2.12 section, it
can open chip through the resistance grounded and as an over-current threshold
value setting. TPS51125 outputs two paths of PWM power supply, is shown
in figure 11-27: 3D3V_PWR, 5V_PWR, through isolation point respectively to
rename to be +3VALW and +5VALW.

Figure 11-26: The screenshot of 1 pin and 6 pin of TPS51125

Figure 11-27: The screenshot of the circuit of 3D3V_PWR and 5V_PWR


renamed

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+3VALW and +5VALW supply respectively to VCCSUS3_3 and V5REF_SUS


of the South bridge; as the South bridge standby voltage, is shown in figure 11-
28 and figure 11- 29.

Figure 11-28: 3.3V standby voltage of the South Bridge

Figure 11-29: 5V standby voltage of the South Bridge

EC delayed send PM_RSMRST#, is shown in figure 11-30.

Figure 11-30: EC sends PM_RSMRST#

PM_RSMRST# is converted to be RSMRST#_SB, is shown in figure 11-31.

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Figure 11-31: PM_RSMRST# renamed to be RSMRST#_SB

RSMRST#_SB is sent to the South Bridge, is shown in figure 11-32.

Figure 11-32: RSMRST#_SB is sent to the South Bridge

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