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VLSI Testing &Testability

(ECT 624)
(M Tech VLSI Design)

Course File
(2019-20 Odd Semester)

Department of Electronics and Communication Engineering


Malaviya National Institute of Technology, Jaipur
Jaipur-India, 302017

VLSI Testing &Testability


COURSE FILE

Program : Master of Technology


Specialisation : ECE/ VLSI Design
Course Code : ECT 624

Approved By

HoD
Electronics and CommunicationEngineering
CONTENTS
SYLLABUS
REFERENCES
COURSE OUTCOMES
COURSE OUTCOME EVALUATION

2
SYLLABUS (Module wise)
Specialisation: UG/ VLSI Design Code: ECT306, ECT 624
Subject: VLSI Testing &Testability Credits: L-T-P: 3-0-0
Total Theory Periods: 36 Total Tutorial Periods: 00
Marks: 100, 30 in Mid-Term, 50 in End-Term, 20 marks assignment

Syllabus
UNIT 1. Introduction to Digital Testing: Introduction, Test process and Test economics,-
Functional vs. Structural Testing Defects, Errors, Faults and Fault Modeling (mainly stuck at fault
modeling), Fault Equivalence, Fault Dominance, Fault Collapsing and Checkpoint Theorem
UNIT 2. Fault Simulation and Testability Measures: Circuit Modelling and Algorithms for Fault
Simulation, Serial Fault Simulation, Parallel Fault Simulation, Deductive Fault Simulation,
Concurrent Fault Simulation, Combinational SCOAP Measures and Sequential SCOAP Measures
UNIT 3. Combinational Circuit Test Pattern Generation: Introduction to Automatic Test Pattern
Generation (ATPG) and ATPG Algebras, Standard ATPG Algorithms, D-Calculus and D-Algorithm,
Basics of PODEM and FAN
UNIT 4. Sequential Circuit Testing and Scan Chains: ATPG for Single-Clock Synchronous
Circuits, Use of Nine-Valued Logic and Time-Frame Expansion Methods, Complexity of Sequential
ATPG, Scan Chain based Sequential Circuit Testing, Scan Cell Design, Design variations of Scan
Chains, Sequential Testing based on Scan Chains, Overheads of Scan Design, Partial-Scan Design
UNIT 5. Built in Self test (BIST): Introduction to BIST architecture BIST Test Pattern
Generation, Response Compaction and Response Analysis, Memory BIST, March Test, BIST with
MISR, Neighbourhood Pattern Sensitive Fault Test, Transparent Memory BIST

Prerequisites:
ECT202 Switching theory or equivalent
Course plan
Module Contents for delivery No. of Marks Mode of delivery
no. lectures
1. Introduction to VLSI design flow and need of VLSI testing. 7 MT Choke and Talk, PPT
Physical Faults and their modeling; Stuck at Faults, Bridging ET
Faults; Fault collapsing; Fault Simulation: Deductive, Parallel,
and Concurrent Fault Simulation. Critical Path Tracing
2. ATPG for Combinational Circuits: D-Algorithm, Boolean 6 MT Choke and Talk, PPT
Differences, PODEM Random, Deterministic and Weighted ET
Random Test Pattern Generation; Aliasing and its effect on
Fault Coverage.
3. PLA Testing, Cross Point Fault Model and Test Generation. 6 MT Choke and Talk, PPT
Memory Testing- Permanent, Intermittent and Pattern ET
Sensitive Faults, Marching Tests; Delay Faults.
4. ATPG for Sequential Circuits: Time Frame Expansion ; 7 MT Choke and Talk, PPT
Controllability and Observability Scan Design, BILBO , ET
Boundary Scan for Board Level Testing ; BIST and Totally self
checking circuits
5. System Level Diagnosis & repair- Introduction; Concept of 8 MT Choke and Talk, PPT
Redundancy, Spatial Redundancy, Time Redundancy, Error ET
Correction Codes. Latest trends in VLSI Testing and Testability

REFERENCES

3
Text Books:
Abramovici, M., Breuer, M. A. and Friedman, A. D. Digital systems testing and testable
design. IEEE press (Indian edition available through Jayco Publishing house), 2001.
Bushnell and Agarwal, V. D. VLSI Testing. Kluwer.
Agarwal, V. D. and Seth, S. C. Test generation for VLSI chips. IEEE computer society press.
Hurst, S. L. VLSI testing: Digital and mixed analog/digital techniques. INSPEC/IEE, 1999.

Other References:
https://nptel.ac.in/courses/106103116/handout/mod7.pdf
http://ece-research.unm.edu/jimp/vlsi_test/slides/html/overview1.htm
http://www.cs.uoi.gr/~tsiatouhas/CCD/Section_8_1-2p.pdf
Latest journal papers for recent trends in VLSI Testing and Testability

COURSE OUTCOMES
(And their mapping with Modules/Units, POs)
CO1 To able to grasp core concept of digital system testing and testability. PO1, PO9
(Knowledge, Understanding)
CO2 To understand how a faulty circuit may cause PO2, PO7, PO8
disasters and affect the nature as well as society.
(Affective, Analyze)
CO3 To understand fault detection using different fault simulation PO1,PO2, PO3,PO5
techniques. (Skill, Evaluate)
CO4 To develop ability to design algorithms for PO1, PO2, PO3, PO4,PO5, PO8,
automatic test generation for combinational PO10, PO12
circuits, sequential circuits, PLAs and memory.
(Skill/Affective, Create)
CO5 To apply probabilistic approaches for random test generation. (Skill, PO1, PO2, PO3, PO4, PO6, PO8,
Apply) PO11, PO12,
CO6 To apply different redundancy based fault tolerance techniques to PO1, PO2, PO3, PO4, PO5, PO6,
increase circuit reliability. (Skill/Affective, Analyze) PO8,
CO7 To design BIST for a CUT in Verilog (HDL) and implement ATPG PO1, PO2, PO4, PO5, PO6, PO8,
algorithms in C/C++/MATLAB. (Skill, Create) PO9, PO13
.

Mapping of COs with Modules/Units

CO-> CO1 CO2 CO3 CO4 CO5 CO6 CO7


1 √ √
2 √ √ √
Modul
3 √ √ √ √
e/Unit
4 √ √
5 √ √

Mapping of COs with POs

Pos
CO
1 2 3 4 5 6 7 8 9 10 11 12 13
s

4
CO
√ √
1
CO
√ √ √
2
CO
√ √ √ √
3
CO
√ √ √ √ √ √ √ √
4
CO
√ √ √ √ √ √ √ √
5
CO
√ √ √ √ √ √ √
6
CO
√ √ √ √ √ √ √ √
7
COURSE OUTCOME EVALUATION
(To be modified later.)

4.1 (2018-19)

Mid Term Test


MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY JAIPUR - 302017
B.TECH, V Semester, Mid Term, September 2019

Branch: Electronics and Communication Engineering


Subject code and Title: ECT306, VLSI Testing and Testability
Date: 01/10/2019 Time: 12:00 PM -01:30 PM Maximum Marks: 30

Note: 1. All questions are compulsory, marks are written in front of each question
2. Answer to the point
3. Write legibly , make the graphs/diagrams as neat and clean as possible
Course Outcomes:
CO1 To able to grasp core concept of digital system testing and testability. (Knowledge)
CO2 To understand how a faulty circuit may cause disasters and affect the nature as well as society.
(Attitude & Value)
CO3 To understand fault detection using different fault simulation techniques. (Skill)
CO4 To develop ability to design algorithms for automatic test generation for combinational circuits,
sequential circuits, PLAs and memory. (Skill)
CO5 To apply probabilistic approaches for random test generation. (Skill)
CO6 To apply different redundancy based fault tolerance techniques to increase circuit reliability. (Skill)
CO7 To design BIST for a CUT in Verilog and implement ATPG algorithms in C/C++/MATLAB. (Skill)

1.a. i) What is the testing process in digital circuits? Why, where and when is it used
?
ii) What are the defective circuit disadvantages? (if a fault is there what
financial/environmental/social loss can be faced)
iii) Enlist types of faults.
iv) What is the difference between defect, error and fault?
v) What will be the reject rate of a PCB with 50 chips, each having 90% fault
coverage and 90% yield ?

5
Explain following with example-
Fault equivalence
Fault dominance
Fault Collapsing
Checkpoint theorem

What are different fault simulation techniques? Describe


the following with example-
Parallel fault simulation
Deductive fault simulation

Calculate observability at each branch in the below


circuit-

i) What is ATPG? What are different things to complete


the Automated testing of a chip?
ii) What are different test generation methods? Describe
a)truth table based and b) Boolean difference based
method with below circuit example fault at a line is s-a-0
fault.

6
Use ATPG D -algorithm for the following circuit with
input line b is having s-a-1 fault.

Module 1: 11 Marks
Module 2: 11 Marks
Module 3: 08 Marks

End Term Examination:


Unit 1: 5 marks-Q1
Unit 2: 5 Marks-Q2
Unit 3: 8 Marks-Q3
Unit 4: 16 Marks-Q4
Unit 5: 16 Marks-Q5

4.2 (2019-20)

CO CO CO4 CO5
2 3

7
Tot Avg(Q2+Q4)= Avg(Q5 A
al 16/20 )= v
10/20 g
(
Q
6
)
=
1
0
/
2
0
Thi 80% 80% 3
s is 0
the %
per
cen
tag
e
ach
ieve
me
nt
of
CO
s

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