Dac Annd Adc

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Digital to Analog Converter

Introduction

Analog to Digital to
Digital Analog
Analog Digital Analog
System output
input Converter Converter

 A digital system is a combination of devices designed to manipulate


logical information or physical quantities that are represented in digital
form; that is, the quantities can take on only discrete values.
b7
R-2R Ladder Network: Thevenin Resistance
Analog to Digital Converter
(ADC)
ADC: A Parallel Comparator Type
3-bit parallel ( flash) ADC:

The voltage VA is compared simultaneously


with the reference voltages by using parallel
comparators.

The reference voltage VR is divided into


eight ranges; six of these ranges encompass
an interval VR/7. The other two ranges, at the
ends, extend over the interval VR/14.
When analog input is anywhere in the lowest range from 0 to Vo/14
then ADC output is to be 000 and corresponding DAC output will be 0
volt. Quantization error will be Vo/14.

If input voltage is within the range Vo/14 < VA < 3Vo/14 then ADC will
be 001 and corresponding DAC output will be 2Vo/14 volt. Quantization
error will be Vo/14.

If input voltage is within the range 13Vo/14 < VA < Vo then ADC will be
111 and corresponding DAC output will be Vovolt. Quantization error
will be Vo/14.

So quantization error will be equal to Vo/14, no matter where in the


range the input falls
Sampling of Input Signal
Dual-Slope ADC

-
This shows that the output of the counter is proportional to the analog voltage Va.
The count recorded in the counter is numerically equal to analog voltage Va if VR =
2N.

This type of ADC is often used in digital voltmeters-because of its good conversion
accuracy and low cost. The disadvantage of the dual slope ADC is its slow speed.
Consider an object of unknown weight in the range 0 to 1 kg. Suppose that
a balance and a set of known weights of 1/2, 1/4 and 1/8 kg are available.
These known weights are to be used in a succession of trails to determine
the unknown weight (Wa).

We continue to try weights,


successively smaller by a
factor of 2. If a weight is
finally obtained, it is
represented by a 1 and if
removed then, by a 0. The
complete process is shown
in figure.
Successive Approximation ADC
The basic principle of this converter is that the unknown analog input voltage is
approximated against an n-bit digital value by trying one bit at a time, beginning
with the MSB.

 The conversion time is maintained constant in successive approximation type


ADC and it is proportional to the number of bits in the digital output.

 The functional block diagram of successive approximation type ADC is shown in


figure. The circuit employs a successive approximation register (SAR) which
finds the required value of each successive bit by trial and error method.
The output of the SAR is fed to an n-bit DAC. The analog output
equivalent of the DAC is applied to the noninverting input of the
comparator, while the other input of the comparator is connected with
the unknown analog input voltage VA under conversion.

The comparator output is used to activate the successive approximation


logic of SAR.

 When the start command is applied, the SAR sets the MSB, while other
bits are made zero, so that trail code becomes 1 followed by zeros.

 The time required to perform the calculation is the sum of (i) the time
required for resetting SAR before performing the conversion and (ii) the
time required for performing the conversion. So for an n-bit
successive approximation ADC, total number of clock pulses required
for the conversion is (n+1) cycles.
3-bit Successive Approximation ADC
Counting ADC

The counter type ADC is very simple and needs less hardware. This is suitable for
digitizing applications with high resolution. But conversion time is very long,
variable and proportional to the amplitude of the analog input voltage. The
average conversion time is 2n-1 times the clock period, which can be very long
For longer value of n.
Tracking ADC

In practice, the analog input voltage is within 1 LSB of variable reference voltage
leading to oscillation between two adjacent digital values. This can be eliminated
by adjusting the comparator in such a way that the comparator output line will not
reach high unless the analog input voltage is higher than the variable reference
Voltage by ½ LSB.
6. Format: An ADC can usually be obtained for any standard code:
unipolar binary, ones complement, and 2’s complement.
Thank You

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