IPCC LABORATORY MANUAL

DIGITAL SYSTEM DESIGN USING VERILOG

[BEC302]

DEPARTMENT
OF
ELECTRONICS AND TELECOMMUNICATION ENGINEERING
 SIR M VISVESVARAYA INSTITUTE OF TECHNOLOGY
Krishnadevaraya Nagar, Off Internation Airport Road, Bengaluru – 64

DEPARTMENT OF
ELECTRONICS AND TELECOMMUNICATION ENGINEERING

DIGITAL SYSTEL DESIGN USING VERILOG

LABORATORY MANUAL
ACADEMIC YEAR 2023 – 24

SUBJECT : DIGITAL SYSTEM DESIGN USING VERILOG

SUBJ. CODE : BEC302
SEMESTER : 3rd Sem
PREPARED BY : FAIZ MOHAMMAD KAROBARI Assistant Professor
REVIEWED BY : Dr. E. Kavitha Professor & Head of the Department, ETE, Sir. MVIT.
 15.09.2023

Digital System Design using Verilog Semester 3

Course Code BEC302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory/Practical
Course objectives:
This course will enable students to:
 To impart the concepts of simplifying Boolean expression using K-map techniques and Quine-
McCluskey minimization techniques.
 To impart the concepts of designing and analyzing combinational logic circuits.
 To impart design methods and analysis of sequential logic circuits.
 To impart the concepts of Verilog HDL-data flow and behavioural models for the design of digital
systems.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
 Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
 Show Video/animation films to explain the different concepts of Linear Algebra & Signal
Processing.
 Encourage collaborative (Group) Learning in the class.
 Ask at least three HOTS (Higher order Thinking)questions in the class, which promotes
critical thinking.
 Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
 Topics will be introduced in a multiple representation.
 Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
 Discuss how every concept can be applied to the real world-and when that's possible, it
helps improve the students' understanding.
 Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and
have discussions on the topic in the succeeding classes.
 Give Programming Assignments.
MODULE-1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,
Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine-
McCluskey Minimization
Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1).
MODULE-2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)
(Section5.1to5.7 ofText2)
MODULE-3

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Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flip-

flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous
Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using
clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2)
MODULE-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description.(Section2.1to2.2(only Verilog) of Text3)
MODULE-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (onlyVerilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)

PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)

Sl.N Experiments
1 To simplify the given Boolean expressions and realize using Verilog program
2 To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder
6 To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator
7 To realize using Verilog Behavioral description:
Flip-flops: a)JK type b)SR type c)T type and d)D type
8 To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.
Demonstration Experiments (For CIE only–not to be included for SEE)
Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing
experiments.
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor
in the specified direction (by N steps).
10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
its working.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.
2. Analyze and design for combinational logic circuits.
3. Analyze the concepts of Flip Flops(SR, D,T and JK) and to design the synchronous sequential
circuits using Flip Flops.
4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using
Verilog descriptions.

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Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50)
and for the SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). The
student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks out of 100)
in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination)
taken together.
The IPCC means the practical portion integrated with the theory of the course. CIE marks for the
theory component are 25 marks and that for the practical component is 25 marks.
CIE for the theory component of the IPCC
 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests
(Two Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
 Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for
the theory component of IPCC (that is for 25 marks).
 The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of
IPCC.
CIE for the practical component of the IPCC
 15 marks for the conduction of the experiment and preparation of laboratory record, and 10
marks for the test to be conducted after the completion of all the laboratory sessions.
 On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
 The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks
of all experiments’ write-ups are added and scaled down to 15 marks.
 The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
 Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
 The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.

SEE for IPCC

Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks

The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion
will have a CIE component only. Questions mentioned in the SEE paper may include questions
from the practical component.
 The minimum marks to be secured in CIE to appear for SEE shall be 10 (40% of maximum
marks-25) in the theory component and 10 (40% of maximum marks -25) in the practical
component. The laboratory component of the IPCC shall be for CIE only. However, in SEE,
the questions from the laboratory component shall be included. The maximum of 04/05 sub-

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questions are to be set from the practical component of IPCC, the total marks of all questions
should not be more than 20 marks.
 SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to
qualify for the SEE. Marks secured will be scaled down to 50.
 The student is declared as a pass in the course if he/she secures a minimum of 40% (40 marks
out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester
End Examination) taken together.
Suggested Learning Resources:
Books
1. Digital Logic Applications and Design by John MYarbrough,Thomson Learning,2001.
2. Digital Principles and Design by Donald DGivone,McGrawHill, 2002.
3. HDL Programming VHDL and Verilog by Nazeih M Botros, 2009 reprint, Dream techpress.
ReferenceBooks:
1. Fundamentals of logic design, by Charles H Roth Jr., Cengage Learning
2. Logic Design, by Sudhakar Samuel, Pearson/Sanguine, 2007
3. Fundamentals of HDL,by Cyril PR, Pearson/Sanguine2010
Web links and Video Lectures (e-Resources):

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Programming Assignments/Mini Projects can be given to improve programming skills.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

INTRODUCTION TO VERILOG HDL

Verilog HDL is one of the most common hardware description language [HDL]
used by integrated circuit diagrams. The other one is VHDL. HDL allows the design to be
simulated earlier in the design cycle in order to correct or experiment with different
conditions of architecture. Design described in HDL are technology independent, easy to
design and debug and are usually more reliable than schematic particularly for large
circuit.

Verilog can be used to describe designs at low level of abstraction:

1. Algorithmic level [much like ‘C’ with if, case and logic statements]
2. Register Transfer level [RTL use registers connected by Boolean equations]
3. Gate level [Interconnected AND, NAND, OR Gates, etc.]
4. Switch level [The switches are MOS transistors inside gates]

More recently, Verilog is used as an input for synthesis programs which will generate
a GATE level description for the circuit.

TYPICAL DESIGN FLOW

• Specifications describe abstractly the functionality, interface and overall
architecture of a digital circuit to be designed.
• A behaviour description is then created to analyse the design in terms of
functionality, performance, compliance to standards and other high level issues.
• The behaviour description is manually converted to an RTL description in an
HDL. The designer has to describe the data flow that will implement the desired
digital circuit.
• Logic synthesis tools convert the RTL description to a Gate-level netlist. A Gate-
level netlist is a description of the circuit in terms of gates and connection
between them. Logic synthesis tools ensure that the gate-level netlist meets
timing, area and power specifications.
• Gate-level netlist is an input to an automatic place and route, which create a
layout. The layout is verified and fabricated on a chip.
• Designing at RTL level has shrunk the design cycle time from years to a few
months. It is possible to do many design iterations in a short period of time.
GIGO: garbage input garbage output

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

FLOW CHART

Fig. Typical Design Flow

PROCUDURE
Xilinx ISE Design Suite is one of most popular software tools used to synthesize
HDL code. This tool includes many steps. To make user feel comfortable with the tool
the steps are given below –
• Double click on Project navigator. (Assumed icon is present on desktop).
• Select NEW PROJECT in FILE MENU. Enter following details as per your
convenience.
Project name : sample
Project location : C:\example Top level module: HDL

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

• In NEW PROJECT dropdown Dialog box, Choose your appropriate device

specification. Example is given below:
Device family : Spartan 6
Device : XC6SLX4
Package : TQG144
Speed : -3
TOP Level Module : HDL Synthesis Tool : XST
Simulation : ISE Simulator (VHDL/Verilog)
• In Design Tab (panel) window right click on specification (xc6slx4-3tqg144),
select the new source, select source-type as ‘Verilog Module’, type the module
name, click next to Enter the input and output port and modes. Click next and
finish the initial Project preparation. This will create Verilog source file.
• Double click on the Verilog Source File displayed in the Design Tab to open the
program editor and type the implementation part of the program.
• Double click on synthesis. If error occurs, edit and correct Verilog code.
• Change the source from Implementation to Simulation (Behavioral) in Design Tab
(panel) window, right click on specification (xc6slx4-3tqg144), select the new
source, select source-type as ‘Verilog Test fixure’, type the module name, click
next and finish the initial preparation for test bench. This will create Verilog Test
Bench source file.
• Double click on the Verilog Test Bench Source File displayed in the Design Tab
to open the program editor and type the test bench part of the program.
• Double click on Simulate ‘Behavioral check syntax’ to check for error and then
Double Click on ‘Simulate Behavioral Model’ to generate the waveform.
• Right click on sample. Verilog in source window, select new source.
Select source : Implementation constraints file.
Filename : sample
This will create sample .UCF constraints file.
• Double click on Edit constraint (Text) in process window. Edit and enter pin
constraints with syntax:
NET “NETNAME” LOC = “PIN NAME”
• Double click on Implement, which will carry out translate, mapping, place and

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

route of your design. Also, generate program file by double clicking on it, intern
that will create .bit file.
• Connect JTAG cable between your kit and parallel pot of your computer.
• Double click on configure device and select mode in which you want to configure
your device. For ex: select slave serial mode in configuration window and finish
your configuration.
• Right click on device and select ‘program’. Verify your design giving appropriate
inputs and check for the output.
• Also, verify the actual working of the circuit using pattern generator & logic
analyzer.

Fig. Sample Testbench Waveform

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

PROCEDURE TO DOWNLOAD ONTO FPGA

1. Create a UCF (User Constraints File).
2. Click on UCF file and choose assign package pins option as shown in the figure
below.

3. Assign the package pins as shown in fig below –

4. Save the file.

5. Click on the module and choose configure device option.
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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

6. The following icon will be displayed.

7. Right click on the icon and select program option.

8. Program succeeded message will be displayed.
9. Make connections to main board and daughter boards (before configuring), give
necessary inputs from DIP SWITCH and observe the output on LEDs.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 1
Boolean Expression
AIM:

To simplify the given Boolean expressions and realize using Verilog program.

̅𝑩
𝑭(𝑨, 𝑩, 𝑪) = 𝑨 ̅𝑪
̅+𝑨
̅ 𝑩𝑪
̅+𝑨
̅ 𝑩𝑪 + 𝑨𝑩
̅𝑪̅ + 𝑨𝑩
̅𝑪

TRUTH TABLE:

Table 1.1. Truth Table for the given function

INPUTS OUTPUT

A B C F

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 0

K – MAP SIMPLIFICATION:

SIMPPLIFIED BOOLEAN EXPRESSION:

𝑭 = 𝑨𝑪 + (𝑨 ⨁ 𝑩)

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE

module boolexp (F, A, B, C);

output F;
input A, B, C;
assign F = (A & C) | (A ^ B);
endmodule

TEST BENCH CODE

module boolexp_tb;
reg A, B, C;
wire F;
boolexp uut (.A(A), .B(B), .C(C), .F(F));
initial
begin
A = 0; B = 0; C = 0;
#100
A = 0; B = 0; C = 1;
#100
A = 0; B = 1; C = 0;
#100
A = 0; B = 1; C = 1;
#100
A = 1; B = 0; C = 0;
#100
A = 1; B = 0; C = 1;
#100
A = 1; B = 1; C = 0;
#100
A = 1; B = 1; C = 1;
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

RESULT:
The given Boolean expression is realized and simulated using Verilog. Simulated results
are verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 2 (a)
Half Adder
AIM:

To realize Half Adder circuits using Verilog data flow description.

THEORY:

It is a type of Adder which adds two binary bits and producers to outputs sum and
carry respectively. The two inputs are A and B. The output carry is designed as C and the
normal output is designed as S which is the sum.
Stimulus can be written with respect to the truth table given aside for logic gates
using half adder.

DIAGRAM:

Fig. 2.1. Block Diagram of Half Adder

Fig. 2.2. Gate-level Diagram of Half Adder

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TRUTH TABLE:

Table 2.1. Truth Table of Half Adder

INPUTS OUTPUTS
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VERILOG CODE

module halfadder (s, c, a, b);

output s, c;
input a, b;
assign s = a ^ b;
assign c = a & b;
endmodule

TEST BENCH CODE

module halfadder_tb;
reg a, b;
wire s, c;
halfadder uut (.a(a), .b(b), .s(s), .c(c));
initial
begin
a = 0; b = 0;
#100
a = 0; b = 1;
#100
a = 1; b = 0;
#100
a = 1; b = 1;
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TEST BENCH WAVEFORM:

Fig. 2.3. Output Waveform of half adder generated by Isim Simulator

RESULT:
The half adder is realized and simulated using Verilog. Simulated results are verified with
the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 2 (b)
Full Adder
AIM:

To realize Full Adder circuits using Verilog data flow description.

THEORY:

Full Adder is the adder that adds three inputs and produces two outputs. The first
two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM. The C-OUT
is also known as the majority 1’s detector, whose output goes high when more than one
input is high.

DIAGRAM:

Fig. 2.4. Block Diagram of Full Adder

TRUTH TABLE:

Table 2.2. Truth Table of Full Adder

a b cin sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE

module full_adder_d (
input a, b, cin,
output sum, carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a);
endmodule

TEST BENCH CODE

module full_adder_tb;
reg a, b, cin;
wire sum, carry;

full_adder_s uut (a, b, cin, sum, carry);

initial begin
a = 0; b = 0; cin = 0;
#10
a = 0; b = 0; cin = 1;
#10
a = 0; b = 1; cin = 0;
#10
a = 0; b = 1; cin = 1;
#10
a = 1; b = 0; cin = 0;
#10
a = 1; b = 0; cin = 1;
#10
a = 1; b = 1; cin = 0;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

#10
a = 1; b = 1; cin = 1;
end

endmodule

TEST BENCH WAVEFORM:

Fig. 2.5. Output Waveform of Full adder generated by Isim Simulator

RESULT:
The full adder is realized and simulated using Verilog. Simulated results are verified with
the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 2 (c)
Half Subtractor
AIM:

To realize Half Subtractor circuits using Verilog data flow description.

THEORY:

It is a type of Subtractor which Subtract two binary bits and producers to outputs
difference and borrow respectively. The two inputs are A and B. The output borrow is
designed as B and the normal output is designed as D which is the difference.
Stimulus can be written with respect to the truth table given aside for logic gates
using half subtractor.

DIAGRAM:

Fig. 2.6. Block Diagram of Half Subtractor

Fig. 2.7. Gate-level Diagram of Half Subtractor

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TRUTH TABLE:

Table 2.1. Truth Table of Half Subtractor

INPUTS OUTPUTS
P Q D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

VERILOG CODE

module half_subtractor(input P, Q, output D, B);

assign D = P ^ Q;
assign B = ~P & Q;
endmodule

TEST BENCH CODE

module tb_top;
reg P, Q;
wire D, B;

half_subtractor hs (P, Q, D, B);

initial begin
P = 0; Q = 0;
#1;
P = 0; Q = 1;
#1;
P = 1; Q = 0;
#1;
P = 1; Q = 1;
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TEST BENCH WAVEFORM:

Fig. 2.8. Output Waveform of half subtractor generated by Isim Simulator

RESULT:
The half subtractor is realized and simulated using Verilog. Simulated results are verified
with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 2 (d)
Full Subtractor
AIM:

To realize Full Subtractor circuits using Verilog data flow description.

THEORY:

A full subtractor is designed to accommodate the extra borrow bit from the
previous stage. Thus it has three single-bit inputs and produces two single-bit outputs.

Consider that we want to subtract three 1-bit numbers. The numbers are X, Y and Z
then a difference bit (D) and a borrow bit (B) will get generated.

DIAGRAM:

Fig. 2.9. Block Diagram of Full Subtractor

Fig. 2.10. Gate-level Diagram of Full Subtractor

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TRUTH TABLE:

Table 2.4. Truth Table of Full Subtractor

X Y Z D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

VERILOG CODE

module full_subtractor (D, B, X, Y, Z);

output D, B;
input X, Y, Z;
assign D = X ^ Y ^ Z;
assign B = ~X & (Y^Z) | Y & Z;
endmodule

TEST BENCH CODE

module full_subtractor_tb;
wire D, B;
reg X, Y, Z;
full_subtractor uut (D, B, X, Y, Z);
initial begin
X = 0; Y = 0; Z = 0;
#1 X = 0; Y = 0; Z = 1;
#1 X = 0; Y = 1; Z = 0;
#1 X = 0; Y = 1; Z = 1;
#1 X = 1; Y = 0; Z = 0;
#1 X = 1; Y = 0; Z = 1;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

#1 X = 1; Y = 1; Z = 0;
#1 X = 1; Y = 1; Z = 1;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 2.11. Output Waveform of full subtractor generated by Isim Simulator

RESULT:
The full subtractor is realized and simulated using Verilog. Simulated results are verified
with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 3
Arithmetic and Logic Unit [ALU]
AIM:
Verilog 4-bit ALU shown in figure and verify the functionality of ALU by selecting
appropriate test patterns. The functionality of the ALU is presented in Table 1.
a. Write test bench to verify the functionality of the ALU considering all possible
input patterns
b. The enable signal will set the output to required functions if enabled, if disabled all
the outputs are set to tri-state
c. The acknowledge signal is set high after every operation is completed

THEORY:
The ALU has 4-bit inputs ‘A’ and ‘B’ and produces one 4-bit output by performing
a specified arithmetic or logical functions on A and B inputs. The particular function to be
performed is specified by a 3-bit control input. ALU (arithmetic and logic unit) is a
combinational digital circuit that performs arithmetic and bitwise operations on integer
binary numbers.

DIAGRAM:

Fig. 3.1. Block Diagram of 4-bit ALU

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

OPERATION TABLE:

Table 3. Truth Table of ALU Functions

VERILOG CODE

module alu32 (aluout, ack, a, b, opcode, en);

input [3:0] a, b;
input [2:0] opcode;
input en;
output reg [3:0] aluout;
output reg ack;

always@ (en, opcode, a, b)

begin

if (en == 1'b0)
aluout = 4'dz;
else
begin
aluout = 4'b0;
case(opcode)
3'd0: begin aluout = a + b; ack = 1; end
3'd1: begin aluout = a - b; ack = 1; end
3'd2: begin aluout = a + 1; ack = 1; end
3'd3: begin aluout = a - 1; ack = 1; end
3'd4: begin aluout = !a; ack = 1; end

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

3'd5: begin aluout = ~a; ack = 1; end

3'd6: begin aluout = a | b; ack = 1; end
3'd7: begin aluout = a & b; ack = 1; end
endcase
end
end
endmodule

TEST BENCH CODE

module alu32_tb;
reg [3:0] a;
reg [3:0] b;
reg [2:0] opcode;
reg en;
wire [3:0] aluout;
wire ack;
alu32 uut (.a(a), .b(b), .opcode(opcode), .en(en), aluout(aluout),
.ack(ack));
initial
begin
a = 0; b = 0; en = 0; opcode = 0;

#100;
a = 4'd5; b = 4'd5; en = 1; opcode = 3'b000;

#100
opcode = 3'b001;

#100
opcode = 3'b010;

#100
opcode = 3'b011;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

#100
opcode = 3'b100;

#100
opcode = 3'b101;

#100
opcode = 3'b110;

#100
opcode = 3'b111;

end
endmodule

RESULT:
The functionality of a 4-bit ALU, as given, were verified considering all possible input
patterns and the given task was performed with Verilog code and Test bench.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 4 (a)
Binary to Gray
AIM:

To realize 4-bit binary to gray circuit using Verilog behavioural description.

THEORY:

Binary Number is the default way to store numbers, but in many applications,
binary numbers are difficult to use and a variety of binary numbers is needed. This is
where Gray codes are very useful.

Gray code has a property that two successive numbers differ in only one
bit because of this property gray code does the cycling through various states with
minimal effort and is used in K-maps, error correction, communication, etc.

DIAGRAM:

Fig. 4.1. Block Diagram of 4-bit Binary to Gray Converter

Fig. 4.2. Gate-level Diagram of 4-bit Binary to Gray Converter

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TRUTH TABLE:

Table 2.1. Truth Table of 4-bit Binary to Gray Converter

VERILOG CODE

module Binary_to_Gray(
input [3:0] b,
output reg[3:0] g
);
always@(b)
begin
g[0]=b[1]^b[0];

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

g[1]=b[2]^b[1];
g[2]=b[3]^b[2];
g[3]=b[3];
end
endmodule

TEST BENCH CODE

module Binary_to_Gray_tb;
reg [3:0]b;
wire [3:0]g;

Binary_to_Gray uut (b,g);

initial begin
b=4'b0000;
#10 b=4'b0001;
#10 b=4'b0010;
#10 b=4'b0011;
#10 b=4'b0100;
#10 b=4'b0101;
#10 b=4'b0110;
#10 b=4'b0111;
#10 b=4'b1000;
#10 b=4'b1001;
#10 b=4'b1010;
#10 b=4'b1011;
#10 b=4'b1100;
#10 b=4'b1101;
#10 b=4'b1110;
#10 b=4'b1111;
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TEST BENCH WAVEFORM:

Fig. 1.3. Output Waveform of 4-bit binary to gray converter generated by Isim Simulator

RESULT:
The binary to gray converter is realized and simulated using Verilog. Simulated results are
verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 4 (b)
Gray to Binary
AIM:

To realize 4-bit gray to binary circuit using Verilog behavioural description.

DIAGRAM:

Fig. 4.1. Block Diagram of 4-bit Gray to Binary Converter

TRUTH TABLE:

Table 2.1. Truth Table of 4-bit Gray to Binary Converter

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

module Binary_to_Gray(
input [3:0] b,
output reg[3:0] g
);
always@(b)
begin
b[0]=b[1]^g[0];
b[1]=b[2]^g[1];
b[2]=g[3]^g[2];
b[3]=g[3];
end
endmodule

TEST BENCH CODE

module Binary_to_Gray_tb;
wire [3:0]b;
reg [3:0]g;

Binary_to_Gray uut (g,b);

initial begin
g=4'b0000;
#10 g=4'b0001;
#10 g=4'b0010;
#10 g=4'b0011;
#10 g=4'b0100;
#10 g=4'b0101;
#10 g=4'b0110;
#10 g=4'b0111;
#10 g=4'b1000;
#10 g=4'b1001;
#10 g=4'b1010;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

#10 g=4'b1011;
#10 g=4'b1100;
#10 g=4'b1101;
#10 g=4'b1110;
#10 g=4'b1111;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 1.3. Output Waveform of Gray to Binary converter generated by Isim Simulator

RESULT:
The 4-bit gray to binary converter is realized and simulated using Verilog. Simulated
results are verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 4 (c)
Binary to Excess-3
AIM:

To realize 4-bit binary to excess-3 circuit using Verilog behavioural description.

THEORY:

Excess-3 binary code is an unweighted self-complementary BCD code.

Self-Complementary property means that the 1’s complement of an excess-3 number is
the excess-3 code of the 9’s complement of the corresponding decimal number. This
property is useful since a decimal number can be nines’ complemented (for subtraction)
as easily as a binary number can be ones’ complemented; just by inverting all bits.

DIAGRAM:

Fig. 4.1. Block Diagram of 4-bit Binary to Excess-3 Converter

TRUTH TABLE:

Table 2.1. Truth Table of 4-bit Binary to Excess-3 Converter

INPUT OUTPUT
B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1

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1 0 0 1 1 1 0 0
1 0 1 0 1 1 0 1
1 0 1 1 1 1 1 0
1 1 0 0 1 1 1 1
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

VERILOG CODE

module bin_ex_4bit(B, E);

output reg [3:0] E;
input [3:0] B;
always@(B)
begin
casex(B)
4'b0000:E = 4'b0000;
4'b0001:E = 4'b0001;
4'b0010:E = 4'b0010;
4'b0011:E = 4'b0011;
4'b0100:E = 4'b0100;
4'b0101:E = 4'b0101;
4'b0110:E = 4'b0110;
4'b0111:E = 4'b0111;
4'b1000:E = 4'b0000;
4'b1001:E = 4'b0001;
4'b1010:E = 4'b0010;
4'b1011:E = 4'b0011;
4'b1100:E = 4'b1100;
4'b1101:E = 4'bxxxx;
4'b1110:E = 4'bxxxx;
4'b1111:E = 4'bxxxx;
endcase

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

end
endmodule

TEST BENCH CODE

module ex_bin_4bit_tb;
reg [3:0] B;
wire [3:0] E;
bin_ex_4bit uut (.E(E), .B(B));
initial
begin

#100 B = 4'b0000;
#100 B = 4'b0001;
#100 B = 4'b0010;
#100 B = 4'b0011;
#100 B = 4'b0100;
#100 B = 4'b0101;
#100 B = 4'b0110;
#100 B = 4'b0111;
#100 B = 4'b1000;
#100 B = 4'b1001;
#100 B = 4'b1010;
#100 B = 4'b1011;
#100 B = 4'b1100;
#100 B = 4'b1101;
#100 B = 4'b1110;
#100 B = 4'b1111;
end
endmodule

RESULT:
The binary to excess-3 converter is realized and simulated using Verilog. Simulated results
are verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 4 (d)
Excess-3 to Binary
AIM:

To realize 4-bit excess-3 to binary circuit using Verilog behavioural description.

DIAGRAM:

Fig. 4.1. Block Diagram of 4-bit Binary to Excess-3 Converter

TRUTH TABLE:

Table 2.1. Truth Table of 4-bit Excess-3 to Binary Converter

INPUT OUTPUT
E3 E2 E1 E0 B3 B2 B1 B0

0 0 0 0 x x x x
0 0 0 1 x x x x
0 0 1 0 x x x x
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
1 1 0 1 1 0 1 0
1 1 1 0 1 0 1 1
1 1 1 1 1 1 0 0

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE

module ex_bin_4bit(E, B);

output reg [3:0] B;
input [3:0] E;
always@(E)
begin
casex(E)
4'b0000:B = 4'bxxxx;
4'b0001:B = 4'bxxxx;
4'b0010:B = 4'bxxxx;
4'b0011:B = 4'b0000;
4'b0100:B = 4'b0001;
4'b0101:B = 4'b0010;
4'b0110:B = 4'b0011;
4'b0111:B = 4'b0100;
4'b1000:B = 4'b0101;
4'b1001:B = 4'b0110;
4'b1010:B = 4'b0111;
4'b1011:B = 4'b1000;
4'b1100:B = 4'b1001;
4'b1101:B = 4'b1010;
4'b1110:B = 4'b1011;
4'b1111:B = 4'b1100;
endcase
end
endmodule

TEST BENCH CODE

module ex_bin_4bit_tb;
reg [3:0] E;
wire [3:0] B;
ex_bin_4bit uut (.E(E), .B(B));
initial

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

begin

#100 E = 4'b0000;
#100 E = 4'b0001;
#100 E = 4'b0010;
#100 E = 4'b0011;
#100 E = 4'b0100;
#100 E = 4'b0101;
#100 E = 4'b0110;
#100 E = 4'b0111;
#100 E = 4'b1000;
#100 E = 4'b1001;
#100 E = 4'b1010;
#100 E = 4'b1011;
#100 E = 4'b1100;
#100 E = 4'b1101;
#100 E = 4'b1110;
#100 E = 4'b1111;
end
endmodule

RESULT:
The excess-3 to binary converter is realized and simulated using Verilog. Simulated results
are verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 5 (a)
Multiplexer
AIM:
To realize 8:1 multiplexer circuit using Verilog behavioural description.

THEORY:
Multiplexer is a digital switch. It allows digital information from several sources to
be rooted on to a single output line. The basic multiplexer has several data input lines and
a single output line. The selection of a particular input line is controlled by a set of
selection lines. Normally there are 2N input lines and N selection lines whose bit
combinations determine which input is selected. Therefore, multiplexer is many into one
and it provides the digital equivalent of an analog selector switch.

DIAGRAM:

Fig. 5.1. Block Diagram of 8:1 Multiplexer

TRUTH TABLE:

Table 5.1. Truth Table of 8:1 Multiplexer

S(2) S(1) S(0) Y

0 0 0 I(0)
0 0 1 I(1)
0 1 0 I(2)
0 1 1 I(3)
1 0 0 I(4)
1 0 1 I(5)
1 1 0 I(6)
1 1 1 I(7)

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE

module mux8_1(Y, S, I);

output Y;
input [2:0] S;
input [7:0] I;
reg Y;
always@(S, I)
begin
case(S)
3'b000:Y = I[0];
3'b001:Y = I[1];
3'b010:Y = I[2];
3'b011:Y = I[3];
3'b100:Y = I[4];
3'b101:Y = I[5];
3'b110:Y = I[6];
default:Y = I[7];
endcase
end
endmodule

TEST BENCH CODE

module mux8_1_tb;
reg [2:0] S;
reg [7:0] I;
wire Y;
mux8_1 uut (.Y(Y), .S(S), .I(I));
initial
begin

I = 8'b01010101;
S = 3'b000;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

#100 S = 3'b001;
#100 S = 3'b010;
#100 S = 3'b011;
#100 S = 3'b100;
#100 S = 3'b101;
#100 S = 3'b110;
#100 S = 3'b111;

end
endmodule

TEST BENCH WAVEFORM:

Fig. 5.2. Output Waveform of 8:1 Multiplexer generated by Isim Simulator

RESULT:

The 8 to 1 multiplexer is realized using Verilog with case statement. Simulated

results are verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 5 (b)
Encoder
AIM:
To realize 8:3 encoder circuit using Verilog behavioural description.

THEORY:
An encoder is a digital circuit which performs the inverse of decoder. An encoder
has 2N input lines and N output lines. In encoder the output lines generate the binary code
corresponding to input value. The decimal to bcd encoder usually has 10 input lines and 4
output lines. The decoder decimal data as an input for decoder an encoded bcd output is
available at 4 output lines.

DIAGRAM:

Fig. 5.3. Block Diagram of 8:3 Encoder

TRUTH TABLE:
Table 5.2. Truth Table of 8:3 Encoder
INPUTS OUTPUTS
E D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Y[2] Y[1] Y[0]
1 x x x x x x x x 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 1 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 1 0
0 1 0 0 0 0 0 0 0 1 1 1

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE

module encoder8_3(Y, D, E);

output [2:0] Y;
input [7:0] D;
input E;
reg [2:0] Y;
always@(E, D)
begin
if (E == 1’b1)
Y = 3’d0;
else
begin
case (D)
8'b00000001:Y = 3'd0;
8'b00000010:Y = 3'd1;
8'b00000100:Y = 3'd2;
8'b00001000:Y = 3'd3;
8'b00010000:Y = 3'd4;
8'b00100000:Y = 3'd5;
8'b01000000:Y = 3'd6;
default:Y = 3'd7;
endcase
end
end
endmodule

TEST BENCH CODE

module encoder8_3_tb;
reg [7:0] D;
reg E;
wire [2:0] Y;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

encoder_pri8_3 uut (.Y(Y), .E(E), .D(D));

initial
begin

E = 1;
D = 8'b00000001;

#100;
E = 0;
D = 8'b00000001;

#100;
D = 8'b00000010;

#100;
D = 8'b00000100;

#100;
D = 8'b00001000;

#100;
D = 8'b00010000;

#100;
D = 8'b00100000;

#100;
D = 8'b01000000;

#100;
D = 8'b10000000;
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TEST BENCH WAVEFORM:

Fig. 5.4. Output Waveform of 8:3 Encoder

RESULT:

The 8 to 3 encoder is realized and simulated using Verilog. Simulated results are verified
with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 5 (c)
Priority Encoder
AIM:
To realize 8:3 priority encoder circuit using Verilog behavioural description.

THEORY:
In case of an ordinary encoder, one and only one decimal input can be activated at
any given time. But in the case of some practical digital systems, two or more decimal
inputs can unintentionally become active at the same time that might cause a confusion. In
digital electronics, a combinational logic circuit which produces outputs in response to
only one input among all those that may be activated at the same time is called a priority
encoder. For this, it uses a priority system, and hence it is named so.

DIAGRAM:

Fig. 5.5. Block Diagram of 8:3 Priority Encoder

TRUTH TABLE:

Table 5.3. Truth Table of 8:3 Priority Encoder

INPUTS OUTPUTS
E D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Y[2] Y[1] Y[0]
1 x x x x x x x x 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 x 0 0 1
0 0 0 0 0 0 1 x x 0 1 0
0 0 0 0 0 1 x x x 0 1 1
0 0 0 0 1 x x x x 1 0 0
0 0 0 1 x x x x x 1 0 1
0 0 1 x x x x x x 1 1 0
0 1 x x x x x x x 1 1 1

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE

module encoder_pri8_3 (Y, D, E);

output [2:0] Y;
input [7:0] D;
input E;
reg [2:0] Y;
always@(E, D)
begin
if (E == 1’b1)
Y = 3’d0;
else
begin
casex(D)
8'b00000001:Y = 3'd0;
8'b0000001X:Y = 3'd1;
8'b000001XX:Y = 3'd2;
8'b00001XXX:Y = 3'd3;
8'b0001XXXX:Y = 3'd4;
8'b001XXXXX:Y = 3'd5;
8'b01XXXXXX:Y = 3'd6;
8'b1XXXXXXX:Y = 3'd7;
endcase
end
end
endmodule

TEST BENCH CODE

module encoder_pri8_3_tb;
reg [7:0] D;
reg E;
wire [2:0] Y;
encoder_pri8_3 uut (.Y(Y), .D(D), .E(E));

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

initial
begin
E = 1;
D = 8'b00000001;
#100;
E = 0;
D = 8'b00000001;
#100;
D = 8'b0000001x;
#100;
D = 8'b000001xx;
#100;
D = 8'b00001xxx;
#100;
D = 8'b0001xxxx;
#100;
D = 8'b001xxxxx;
#100;
D = 8'b01xxxxxx;
#100;
D = 8'b1xxxxxxx;
end
endmodule

RESULT:
The 8 to 3 priority encoder is realized and simulated using Verilog. Simulated results are
verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 6 (a)
Demultiplexer
AIM:

To realize 1:8 demultiplexer circuit using Verilog behavioural description.

THEORY:

De-Multiplexer is a combinational circuit that performs the reverse operation of

Multiplexer. It has single input, ‘n’ selection lines and maximum of 2n outputs. The input
will be connected to one of these outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros
and ones. So, each combination can select only one output. De-Multiplexer is also called
as De-Mux.

DIAGRAM:

Fig. 6.1. Block Diagram of 1:8 Demultiplexer

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TRUTH TABLE:

Table 6.1. Truth Table of 1:8 Demultiplexer

VERILOG CODE

module demux_1_8(y,s,a);
output reg [7:0]y;
input [2:0]s;
input a;
always @(*)
begin
y=0;
case(s)
3'd0: y[0]=a;
3'd1: y[1]=a;
3'd2: y[2]=a;
3'd3: y[3]=a;
3'd4: y[4]=a;
3'd5: y[5]=a;
3'd6: y[6]=a;
3'd7: y[7]=a;
endcase
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TEST BENCH CODE

module test_demux;
reg [2:0]S;
reg A;
wire [7:0]Y;
demux_1_8 mydemux(.y(Y), .a(A), .s(S));
initial begin
A=1; S=3'd5;
#30;
A=0; S=3'd1;
#30;
A=1; S=3'd1;
#30;
S=3'd6;
#30;
S=3'd0;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 6.2. Output Waveform of 1:8 Demultiplexer generated by Isim Simulator

RESULT:
The 1:8 Demultiplexer is realized and simulated using Verilog. Simulated results
are verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 6 (b)
Decoder
AIM:

To realize 3:8 Decoder circuit using Verilog behavioural description.

THEORY:

A decoder is a combinational logic circuit that change the binary information into
2N output lines is known as Decoders. The binary information is passed in the form of N
input lines. The output lines define the 2N-bit code for the binary information. In simple
words, the Decoder performs the reverse operation of the Encoder. At a time, only one
input line is activated for simplicity. The produced 2N-bit output code is equivalent to the
binary information.

DIAGRAM:

Fig. 6.3. Block Diagram of 3:8 Decoder

TRUTH TABLE:
Table 6.2. Truth Table of 3:8 Decoder

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VERILOG CODE

module decoder3to8 (Data_in, Data_out);

input [2:0] Data_in;
output [7:0] Data_out;
reg [7:0] Data_out;
always @(Data_in)
case (Data_in)
3'b000 : Data_out = 8'b00000001;
3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;
3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;
default : Data_out = 8'b00000000;
endcase
endmodule

TEST BENCH CODE

module tb_decoder;
reg [2:0] Data_in;
wire [7:0] Data_out;
decoder3to8 uut (.Data_in(Data_in), .Data_out(Data_out));
initial
begin
Data_in = 3'b000; #100;
Data_in = 3'b001; #100;
Data_in = 3'b010; #100;
Data_in = 3'b011; #100;
Data_in = 3'b100; #100;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

Data_in = 3'b101; #100;

Data_in = 3'b110; #100;
Data_in = 3'b111; #100;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 6.4. Output Waveform of 3:8 Decoder generated by Isim Simulator

RESULT:
The 3:8 decoder is realized and simulated using Verilog. Simulated results are verified
with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 6 (c)
Comparator
AIM:

To realize 2-bit binary comparator circuit using Verilog behavioural description.

THEORY:

A two-bit comparator is a combinational circuit that compares two words

(numbers); each word has two bits. Figure shows the logic symbol of the comparator. In
Figure, the two words are X and Y. The output of the comparator indicates the result of the
comparison: X > Y, X = Y, or X < Y.

DIAGRAM:

Fig. 6.5. Block Diagram of 2-bit Comparator

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TRUTH TABLE:

Table 6.3. Truth Table of 2-bit Comparator

VERILOG CODE

module 2_Mag_Comp(
input [1:0]a,b,
output equal, greater, lower
);
reg greater, equal, lower;
initial greater = 0, equal = 0, lower = 0;
always @ (a or b)
begin
if (a < b)
begin
greater = 0; equal = 0; lower = 1;
end
else if (a == b)
begin
greater = 0; equal = 1; lower = 0;
end
else

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

begin
greater = 1; equal = 0; lower = 0;
end
end
endmodule

TEST BENCH CODE

module 2_Mag_Comp_tb;
reg [1:0] a, b;
wire equal, greater, lower;
2_Mag_Comp uut (.a(a), .b(b), .equal(equal), .greater(greater),
.lower(lower));
initial
begin
a = 0; b = 0;
#100; a = 2; b = 1;
#100; a = 1; b = 2;
#100; a = 3; b = 3;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 6.6. Output Waveform of 2-bit comparator generated by Isim Simulator

RESULT:
The 2-bit comparator is realized and simulated using Verilog. Simulated results are
verified with the truth table.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 7 (a)
AIM:

To realize SR flipflop circuit using Verilog behavioural description.

THEORY:
The SR flipflop is a 1-bit memory by stable device which stands for “Set-Reset”
flipflop having two inputs, i.e., SET and RESET. The SET input ‘S’ sets the device or
produces the output 1 and the RESET input ‘R’ resets the device or produces the output 0.
The reset input is used to get back the flip flop into its original state from the current state
within input ‘Q’. This output depends on the set and reset conditions, which is either at the
logic ‘0’ or ‘1’.

DIAGRAM:

Fig. 7.1. Block Diagram of SR Flipflop

TRUTH TABLE:

Table 7.1. Truth Table of SR Flipflip

Clk sr q qb
00 0 0
01 0 1
10 1 0
11 z z

VERILOG CODE
module srff (q, qb, sr, clk);
output q, qb;
input clk;
input [1:0] sr;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

reg q = 0, qb = 1;
always@ (posedge clk)
begin
case(sr)
2'b00 : q = q;
2'b01 : q = 0;
2'b10 : q = 1;
2'b11 : q = 1'bx;
endcase
qb = ~q;
end
endmodule

TEST BENCH CODE:

module srff_tb;
reg [1:0] sr;
reg clk;
wire q;
wire qb;
srff uut (.q(q), .qb(qb), .sr(sr), .clk(clk));
initial
begin
clk = 1'b0;
forever #50 clk = ~clk;
end
initial
begin
#100;
sr = 2'b00;
#100;
sr = 2'b01;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

#100;
sr = 2'b10;
#100;
sr = 2'b00;
#100;
sr = 2'b11;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 7.2. Output Waveform of SR Flipflop generated by Isim Simulator

RESULT:
The Verilog Code for SR flipflop was realized and the output is verified.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 7 (b)
AIM:

To realize JK flipflop circuit using Verilog behavioural description.

THEORY:

The JK flipflop is basically gated SR flipflop with the addition of a clock input
circuitry, that prevents the illegal or invalid output condition that can occur when both
input S and R are equal to logic level “1”. Due to this additional clock input, a JK flipflop
has four possible input combinations, “logic 1”, “logic 0”, “No Change” and “Toggle” as
shown in the truth table for JK flipflop.
JK flip flop is called Universal flipflop because the other flip flops like a D, SR, T
can be derived from it. The “racing or race around condition” takes place in a JK flip flop
when J = 1 and K = 1 and clock = 1

DIAGRAM:

Fig. 7.3. Block Diagram of JK Flipflop

TRUTH TABLE:

Table 7.2. Truth Table of JK Flipflop

clk jk q qb

00 0 1

01 0 1

10 1 0

11 𝑞̅ 𝑞𝑏
̅̅̅

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

VERILOG CODE
module jkff(q, qb, jk, clk);
output q, qb;
input clk;
input [1:0] jk;
reg q=0, qb=1;
always@(posedge clk)
begin
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
qb=~q;
end
endmodule

TEST BENCH CODE:

module jkff_tb;
reg [1:0] jk;
reg clk;
wire q;
wire qb;
jkff uut (.q(q), .qb(qb), .jk(jk), .clk(clk));
initial
begin
clk = 1'b0;
forever #50 clk = ~clk;
end
initial

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

begin
#100;
jk = 2'b00;
#100;
jk = 2'b01;
#100;
jk = 2'b10;
#100;
jk = 2'b00;
#100;
jk = 2'b11;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 7.4. Output Waveform of JK Flipflop generated by Isim Simulator

RESULT:
The Verilog Code for JK flipflop was realized and the output is verified.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 7 (c)
AIM:

To realize D flipflop circuit using Verilog behavioural description.

THEORY:

D flipflop stands for Delay flipflop or Data flipflop. In this flipflop, the single input
“D” is referred to as the “Data” input. When the data input is set to 1, the flipflop would be
set and when it is set to 0, the flipflop would change and become reset. When the clock
input is set to true, the D input is only copied to the output ‘Q’ as shown in the truth table.

DIAGRAM:

Fig. 7.5. Block Diagram of D Flipflop

TRUTH TABLE:

Table 7.3. Truth Table of D Flipflop

clk d q qb
0 0 1
1 1 0

VERILOG CODE
module dff(q, qb, d, clk);
output q, qb;
input d, clk;
reg q=0, qb=1;
always@ (posedge clk)
begin
q= d;

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

qb=~q;
end
endmodule

TEST BENCH CODE:

module dff_tb;
reg d;
reg clk;
wire q;
wire qb;
dff uut (.q(q), .qb(qb), .d(d), .clk(clk));
initial
begin
clk = 1'b0;
forever #50 clk = ~clk;
end
initial
begin
#100;
d = 0;
#100;
d = 1;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 7.6. Output Waveform of D Flipflop generated by Isim Simulator

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

RESULT:
The Verilog Code for D flipflop was realized and the output is verified.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

EXPERIMENT – 8

AIM:

Write a Verilog Code and Test Bench for 4-bit BCD synchronous counter.

THEORY:
In a synchronous counter, the clock input of all the individual flipflops within the
counter are all clocked together at the same time by the same clock signal. The result of
this synchronization is that all the individual output bits changing starts at exactly the same
time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.

A 4-bit BCD synchronous counter can be built by using synchronous binary

counters to produce a count sequence from 0 to 9. After reaching the count of ‘1001’, the
counter recycles back to ‘0000’. Synchronous counters count on the rising-edge which is
the low to high transition of the clock signal.

When a 4-bit BCD synchronous counter counts upwards from 0 (0000) to 9 (1001),
it is called a 4-bit BCD synchronous up counter and when the counter start with 9 (1001)
and count downward to 0 (0000) then it is called a 4-bit BCD synchronous down counter.

DIAGRAM:

Fig.8.1. Block Diagram of 4-bit BCD Counter

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

a. 4-bit BCD synchronous up counter

TRUTH TABLE:

Table 8.1 Truth Table of 4-bit BCD Up Counter

reset clk Count(3) Count(2) Count(1) Count(0)

1 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1

VERILOG CODE

module bcd_up_counter(count, clock, reset);

output [3:0] count;
input clock, reset;
reg [3:0] count;
always@ (posedge clock)
begin
if(reset == 1)
count = 4'b0000;
else
begin
if (count == 4'b1001)
count = 4'b0000;
else
count = count + 1'b1;
end
end
endmodule

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

TEST BENCH CODE:

module bcd_tb;
reg clock;
reg reset;
wire [3:0] count;
bcd_up_counter uut (.count(count), .clock(clock), .reset(reset));
initial
begin
clock = 1'b1;
forever #50 clock = ~clock;
end
initial
begin
reset = 1;
#100
reset = 0;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 8.2. Output Waveform of 4-bit BCD Up Counter generated by Isim Simulator

RESULT:
The 4-bit synchronous up counter is designed and implemented using Verilog code.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

b. 4-bit BCD synchronous down counter

TRUTH TABLE:

Table 8.2 Truth Table of 4-bit BCD Down Counter

reset clk Count(3) Count(2) Count(1) Count(0)

1 0 0 0 0
0 1 0 0 1
0 1 0 0 0
0 0 1 1 1
0 0 1 1 0
0 0 1 0 1
0 0 1 0 0
0 0 0 1 1
0 0 0 1 0
0 0 0 0 1
0 0 0 0 0

VERILOG CODE

module bcd_dn_counter(count, clock, reset);

output [3:0] count;
input clock, reset;
reg [3:0] count;
always@ (posedge clock)
begin
if(reset == 1)
count = 4'b0000;
else
begin
if (count == 4'b0000)
count = 4'b1001;
else
count = count - 1'b1;
end
end

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

endmodule

TEST BENCH CODE:

module bcd_tb;
reg clock;
reg reset;
wire [3:0] count;
bcd_dn_counter uut (.count(count), .clock(clock), .reset(reset));
initial
begin
clock = 1'b1;
forever #50 clock = ~clock;
end
initial
begin
reset = 1;
#100
reset = 0;
end
endmodule

TEST BENCH WAVEFORM:

Fig. 8.3. Output Waveform of 4-bit BCD Down Counter generated by Isim Simulator

RESULT:
The 4-bit synchronous down counter is designed and implemented using Verilog code.

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

DEMONSTRATION EXPERIMENT
Interface a Stepper motor to FPGA and write Verilog code to control the stepper motor
rotation.

AIM:

Write a Verilog code to design a digital circuit that controls the speed and direction of
the Stepper motor interfaced to FPGA.

DIAGRAM:

Fig. 9.1. Block Diagram of Stepper Motor interface to FPGA

VERILOG CODE

module step_motor(
input p_clk,
output reg[3:0] p_stp
);
reg [20:0] count = 0;
reg [16:0] dur = 0;
reg [3:0] stpval = 'b0001;
reg dir = 0;

parameter speed = 100000; //change this value for speed

parameter duration = 1000; /*change this value for changing
direction timing*/

always @(posedge p_clk)

begin
count = count + 1'b1;

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if (count == speed)
begin
count = 0;
p_stp = stpval;
if (dir == 0)
begin
stpval = stpval << 1;
if (stpval == 'b0000) stpval = 'b0001;
end
else
begin
stpval = stpval >> 1;
if (stpval == 'b0000) stpval = 'b1000;
end

dur = dur + 1'b1;

if(dur == duration)
begin
dur = 0;
dir = ~dir;
end
end
end
endmodule

OBSERVATION:
200 Steps for one full rotation i.e., 3600

3600
1 𝑠𝑡𝑒𝑝 = = 1. 80
200

𝑑𝑢𝑟𝑎𝑡𝑖𝑜𝑛 = 1000 (𝑔𝑖𝑣𝑒𝑛 𝑖𝑛 𝑐𝑜𝑑𝑒)

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DIGITAL SYSTEM DESIGN USING VERILOG BEC302

1000
= 5 𝑟𝑜𝑡𝑎𝑡𝑖𝑜𝑛𝑠
200

PIN ASSOCIATION:
NET "p_clk" LOC = P56;
NET "p_stp[0]" LOC = P29;
NET "p_stp[1]" LOC = P30;
NET "p_stp[2]" LOC = P32;
NET "p_stp[3]" LOC = P33;

RESULT:

Stepper Motor is interfaced to a FPGA and its speed and direction is verified.

Dept. of ETE, Sir. M Visvesvaraya Institute of Technology, Bengaluru. Page 74