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ITC Assignment 5

Good morning sir ji

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15 views

ITC Assignment 5

Good morning sir ji

Uploaded by

phoenixdark280
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Section A

GEETANJALI INSTITUTE OF TECHNICAL STUDIES, UDAIPUR


Information Theory & Coding (Code: 5CS3-01)
III Year V Semester
CO Covered: CO353-01.5

Assignment V

Roll No. (21EGICS010, 22EGICS001 to 22EGICS016)


1. Compare Linear Block code, Cyclic Code and Convolution Code.
1
2. A rate convolution has generating vector as g1 = (1, 0, 0); g2 = (1, 1, 1); g3 = (1, 0, 1).
3
a) Sketch the encode configuration.
b) Draw the code tree, state diagram and trellis diagram.
c) If input message sequence is 10110, determine the output sequence of the encoder.

Roll No. (22EGICS017 to 22EGICS031)


1. Explain Code Tree, Code Trellis, State Diagram with example.
2. A convolutional encoder has single shift register with two stage three modulo-2 adders and an
output multiplexer. The following generator sequence are combined by the multiplexer to
produce the encoder output: g1 = (1,0,1); g2 = (1,1,0); g3 = (1,1,1).
a) Draw the message of the encoder.
b) For the message sequence (10011), determine encoded sequence.
If above hardware is enhanced by increasing number of stages in Shift register and number of
mod-2 adders respectively, what is the effect on Generated output sequence and Periodicity of the
code tree.

Roll No. (22EGICS032 to 22EGICS048)


1. Briefly describe the steps of Viterbi algorithm.
1
2. A rate convolution has generating vector as g1 = (1, 0, 0); g2 = (1, 1, 1); g3 = (1, 0, 1).
3
a) Sketch the encode configuration.
b) Draw the code tree, state diagram and trellis diagram.
c) If input message sequence is 10110, determine the output sequence of the encoder.
Roll No. (22EGICS049 to 22EGICS063)
1. Let a convolutional encoder is:

Determine the convolutional codeword.

2. A convolutional encoder has single shift register with two stage three modulo-2 adders and an
output multiplexer. The following generator sequence are combined by the multiplexer to
produce the encoder output: g1 = (1,0,1); g2 = (1,1,0); g3 = (1,1,1).
a) Draw the message of the encoder.
b) For the message sequence (10011), determine encoded sequence.
If above hardware is enhanced by increasing number of stages in Shift register and number of
mod-2 adders respectively, what is the effect on Generated output sequence and Periodicity of the
code tree.
Section B
GEETANJALI INSTITUTE OF TECHNICAL STUDIES, UDAIPUR
Information Theory & Coding (Code: 5CS3-01)
III Year V Semester
CO Covered: CO353-01.5

Assignment V

Roll No. (22EGICS037, 22EGICS064 to 22EGICS078)


1. Compare Linear Block code, Cyclic Code and Convolution Code.
1
2. A rate convolution has generating vector as g1 = (1, 0, 0); g2 = (1, 1, 1); g3 = (1, 0, 1).
3
a) Sketch the encode configuration.
b) Draw the code tree, state diagram and trellis diagram.
c) If input message sequence is 10110, determine the output sequence of the encoder.

Roll No. (22EGICS079 to 22EGICS092)


1. Explain Code Tree, Code Trellis, State Diagram with example.
2. A convolutional encoder has single shift register with two stage three modulo-2 adders and an
output multiplexer. The following generator sequence are combined by the multiplexer to
produce the encoder output: g1 = (1,0,1); g2 = (1,1,0); g3 = (1,1,1).
a) Draw the message of the encoder.
b) For the message sequence (10011), determine encoded sequence.
If above hardware is enhanced by increasing number of stages in Shift register and number of
mod-2 adders respectively, what is the effect on Generated output sequence and Periodicity of the
code tree.

Roll No. (22EGICS093 to 22EGICS106)


1. Briefly describe the steps of Viterbi algorithm.
1
2. A rate convolution has generating vector as g1 = (1, 0, 0); g2 = (1, 1, 1); g3 = (1, 0, 1).
3
a) Sketch the encode configuration.
b) Draw the code tree, state diagram and trellis diagram.
c) If input message sequence is 10110, determine the output sequence of the encoder.
Roll No. (22EGICS107 to 22EGICS120)

1. Let a convolutional encoder is:

Determine the convolutional codeword.

2. A convolutional encoder has single shift register with two stage three modulo-2 adders and an
output multiplexer. The following generator sequence are combined by the multiplexer to
produce the encoder output: g1 = (1,0,1); g2 = (1,1,0); g3 = (1,1,1).
a) Draw the message of the encoder.
b) For the message sequence (10011), determine encoded sequence.
If above hardware is enhanced by increasing number of stages in Shift register and number of
mod-2 adders respectively, what is the effect on Generated output sequence and Periodicity of the
code tree.
Section C
GEETANJALI INSTITUTE OF TECHNICAL STUDIES, UDAIPUR
Information Theory & Coding (Code: 5CS3-01)
III Year V Semester
CO Covered: CO353-01.5

Assignment V

Roll No. (22EGICS122 to 22EGICS135)


1. Compare Linear Block code, Cyclic Code and Convolution Code.
1
2. A rate convolution has generating vector as g1 = (1, 0, 0); g2 = (1, 1, 1); g3 = (1, 0, 1).
3
d) Sketch the encode configuration.
e) Draw the code tree, state diagram and trellis diagram.
f) If input message sequence is 10110, determine the output sequence of the encoder.

Roll No. (22EGICS136 to 22EGICS149)


1. Explain Code Tree, Code Trellis, State Diagram with example.
2. A convolutional encoder has single shift register with two stage three modulo-2 adders and an
output multiplexer. The following generator sequence are combined by the multiplexer to
produce the encoder output: g1 = (1,0,1); g2 = (1,1,0); g3 = (1,1,1).
c) Draw the message of the encoder.
d) For the message sequence (10011), determine encoded sequence.
If above hardware is enhanced by increasing number of stages in Shift register and number of
mod-2 adders respectively, what is the effect on Generated output sequence and Periodicity of the
code tree.

Roll No. (22EGICS150 to 22EGICS162)


1. Briefly describe the steps of Viterbi algorithm.
1
2. A rate convolution has generating vector as g1 = (1, 0, 0); g2 = (1, 1, 1); g3 = (1, 0, 1).
3
d) Sketch the encode configuration.
e) Draw the code tree, state diagram and trellis diagram.
f) If input message sequence is 10110, determine the output sequence of the encoder.
Roll No. (22EGICS300 to 23EGICS211)

1. Let a convolutional encoder is:

Determine the convolutional codeword.

2. A convolutional encoder has single shift register with two stage three modulo-2 adders and an
output multiplexer. The following generator sequence are combined by the multiplexer to
produce the encoder output: g1 = (1,0,1); g2 = (1,1,0); g3 = (1,1,1).
c) Draw the message of the encoder.
d) For the message sequence (10011), determine encoded sequence.
If above hardware is enhanced by increasing number of stages in Shift register and number of
mod-2 adders respectively, what is the effect on Generated output sequence and Periodicity of the
code tree.

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