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    5_Memory Arch. Basics

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    Memory Design and testing lecture 5

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    5_Memory Arch. Basics

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    Memory Design and testing lecture 5

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    Memory Design and testing lecture 5

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    1 views24 pages

    5_Memory Arch. Basics

    Uploaded by

    pluscommander972
    Memory Design and testing lecture 5

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    EC 4136

    Memory Design & Testing

    Memory Basics
    Course Instructor: Dr. Pooran Singh
    Department of Electrical and Computer Engineering,
    Mahindra Ecole Centrale, Mahindra University
    Email: pooran.singh@mahindrauniversity.edu.in
    Introduction
    • Memory is a major component of a digital computer
    and is present in a large proportion of all digital
    systems.
    • Random-access memory (RAM) stores data
    temporarily, and read-only memory (ROM) stores data
    permanently.
    • ROM is one form of a variety of components called
    programmable logic devices (PLDs) that use stored
    information to define logic circuits.
    Write and Read Operations
    The steps that must be taken for a write are as follows:
    • Apply the binary address of the desired word to the address lines.
    • Apply the data bits that must be stored in memory to the data
    input lines.
    • Activate the Write input. The memory unit will then take the bits
    from the data input lines and store them in the word specified by
    the address lines.
    The steps that must be taken for a read are as follows:
    • Apply the binary address of the desired word to the address lines.
    • Activate the Read input.
    Memory Cycle Timing Waveforms
    Properties of Memory

    • Integrated-circuit RAM may be either static or dynamic.


    • Static RAM (SRAM) consists of internal latches that store the binary
    information.
    • The stored information remains valid as long as power is applied to the
    RAM.
    • Dynamic RAM (DRAM) stores the binary information in the form of
    electric charges on capacitors.
    • The capacitors are accessed inside the chip by n-channel MOS transistors.
    • The stored charge on the capacitors tends to discharge with time, and the
    capacitors must be periodically recharged by refreshing the DRAM.
    • This is done by cycling through the words every few milliseconds, reading
    and rewriting them to restore the decaying charge.
    • DRAM offers reduced power consumption and larger storage capacity in a
    single memory chip, but SRAM is easier to use and has shorter read and
    write cycles.
    • Also, no refresh is required for SRAM.
    16-Word by 1-Bit RAM Chip
    Diagram of a 16 × 1 RAM
    Using a 4 × 4 RAM Cell Array
    Block Diagram of an 8 × 2 RAM
    Using a 4 × 4 RAM Cell Array
    ARRAY OF SRAM IC
    Block Diagram of a
    256K X 8 RAM
    Block Diagram of a 64K X 16 RAM
    DRAM ICs
    Dynamic RAM cell, hydraulic analogy of cell operation, and cell model
    DRAM Bit Slice
    Block Diagram of a DRAM Including Refresh Logic
    Types of DRAM
    A 1 Gb DRAM uses 4-bit data and has equal-
    length row and column addresses. How many
    address pins does the DRAM have?

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