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    DOC-20231018-WA0030.

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    DOC-20231018-WA0030.

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    1 views7 pages

    DOC-20231018-WA0030.

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    shreyashp8969

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    MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

    GURU GOBIND SINGH POLYTECHNIC NASHIK

    MICRO PROJECT
    Academic Year: 2023-24

    TITLE OF PROJECT

    FULL ADDER CIRCUIT

    Program Name & Code: Computer Engineering (CO)


    Course Name & Code: Digital Techniques (22320)
    MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

    Certificate
    This is to certify that Mr. /Ms.

    Roll No. of Third Semester of Diploma in Computer Engineering of Institute,


    Guru Gobind Singh Polytechnic, Nashik (Institute Code: 0369) has completed the Micro
    Project satisfactorily in Subject – Digital Techniques (22320) for the Academic Year
    2023- 2024 as prescribed in the curriculum.

    Place: ……………………. Enrollment No: ……………………………………..

    Date: ……………………… Exam. Seat No: …………………………………….

    Subject Teacher Head of the Department Principal


    MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION

    GURU GOBIND SINGH POLYTECHNIC, NASHIK

    MICRO PROJECT
    Academic year: 2023-24

    TITLE OF PROJECT

    FULL ADDER CIRCUIT

    Program: Computer Engineering


    Program code: CO
    Course: Digital Techniques
    Course code: 22320
    Name of Guide: Mrs. S.S. Ripote
    Group Details:
    Sr. Name of group members Roll Enrollment No. Seat No.
    No No.
    1 Krushna Patil 96 2203690344

    2 Shreyash Patil 97 2203690345

    3 Mrunal Pansare 98 2203690346

    4 Sakshi Pote 99 2203690347

    5 Bhargavi Patil 100 2203690348


    ANNEXURE II

    Evaluation Sheet for the Micro Project


    Academic Year: 2023-24 Name of the Faculty: Mrs S.R. Ripote

    Course: Digital Techniques Course code: 22320 Semester: III


    Title of the project - FULL ADDER CIRCUIT

    COs addressed by Micro Project:

    a. Build simple combinational circuits.

    Major learning outcomes achieved by students by doing the project

    (a) Practical outcome:

    a. Design full adder

    (b) Unit outcomes in Cognitive domain:


    a. Use IC 7483 to design full adder

    (c) Outcomes in Affective domain:


    1) Follow safety practices.
    2) Practice good housekeeping.
    3) Demonstrate working as a leader/a team member.
    4) Maintain tools and equipment.
    5) Follow ethical practices.

    Comments/suggestions about team work /leadership/inter-personal communication (if any)


    Marks out of 6 Marks out of 4for
    for performance performance in
    Roll No Student Name in group activity oral/ presentation Total out of 10
    (D5 Col.8) (D5 Col.9)
    96 Krushna Patil

    97 Shreyash Patil

    98 Mrunal Pansare

    99 Sakshi Pote

    100 Bhargavi Patil

    Mrs. S.S.Ripote

    (Name & Signature of Faculty)


    Construction:-
    A Full Adder can be built using two Half Adders circuits and an OR gate. The first Half Adder has two 1-bit
    binary inputs, which are A and B. It produces two outputs; Sum and Carry.The Sum output of the first Half
    Adder will be the first input of the second Half Adder.

    Full Adder block diagram

    Working:-
    Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A and B and
    the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is
    designated as S which is SUM. The C-OUT is also known as the majority 1’s detector, whose output goes
    high when more than one input is high. A full adder logic is designed in such a manner that can take eight
    inputs together to create a byte-wide adder and cascade the carry bit from one adder to another. We use a full
    adder because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does
    not take a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit results.
    Actual Setup:-

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