KEI Systems

Virtual Asian IBIS Summit (Tokyo)

DDR memory system simulation method

November 12, 2021

KEI Systems
Shinichi Maeda

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 OVERVIEW
• (LP)DDR Memory has 5 generations
• Every generation is x2 speed and lower Vdd from previous
• Higher speed makes it difficult to design PCB system
• New generation DDR implements new features to make PCB
design easier
• New features require changes to simulation methods

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 (LP)DDR Speed/Vdd
• JEDEC
Vdd Clock Speed
DDR5
DDR DDR→LPDDR
2.5V 3.0GHz
DDR2→LPDDR2 LPDDR5
DDR3→LPDDR3
DDR4→LPDDR4 2.5GHz
2.0V LPDDR

DDR2 DDR4 2.0GHz

DDR3
1.5V
DDR3L LPDDR3 LPDDR4
DDR5 1.5GHz
DDR3U
1.0V LPDDR2 LPDDR4
DDR3 LPDDR5 1.0GHz

0.5V DDR2 LPDDR3

DDR 0.5GHz
LPDDR LPDDR2

Year
2000 2005 2010 2015 2020

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 (LP)DDR Features on Generation
• JEDEC
Item DDR LPDDR DDR2 LPDDR2 DDR3 LPDDR3 DDR4 LPDDR4 DDR5 LPDDR5
Rerease 2000/06 2008 2004 2010 2007 2012/5 2012/9 2014/8 2020/7 2019/7
Transfer 200〜
200〜400M 400〜800 400〜1066 800〜2066 800〜1600 1600〜32001600〜32003200〜64003200〜6400
Speed(gBPS) 400M
100〜
Clock(Hz) 100〜200M 200〜400M 200〜533M 400〜1033 400〜800 800〜1600 800〜1600 1600〜32001600〜3200
200M
Vdd/Vddq 2.5 1.8 1.8 1.2 1.5 1.2 1.2 1.1/0.6 1.1 1.05/0.5
Output Full/Reduc 34/48/60/8
Full/Half Full/Half 30/40 34/48 34/40 34/40 * *
Impedance e 0/120
34.3/40/60 34/40/48/640/48/60/8
50/75/150/ 20/30/40/6
Value ー ー ー /80/120/O 0/80/120/20/120/240/ * *
ODT OFF 0/120/OFF
FF 40/OFF OFF
Pull ー ー Vdd/2 ー Vdd/2 Vdd Vdd Vdd Vdd

Training ー ー ー ー ー ー ◯ ◯ ◯ ◯
Equalizer/E
ー ー ー ー ー ー ー ー ◯ ◯
mphasys
16Mb〜 128Mb〜 64Mb〜 512Mb〜 4Gb 〜 4Gb 〜
Strage 64Mb〜2Gb 1Gb〜32Gb 2Gb〜16Gb 8Gb〜64Gb
256Mb 4Gb 32Gb 8Gb 32Gb 32Gb

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 DDR vs. LPDDR
• DDR
• Application: HPC, PC, Built-in System
• High-end Performance: Speed, Memory Size
• Connect multiple memories
• BGA
• DIMM/SIMM Module
• LPDDR
• Application: Mobile device
• Low Power First, next size then speed, memory size
• Connect one or a few memories
• POP (Package-on-Package), Flip Chip, BGA

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 DDR Technologies
• DDR
• Lower Power
• Green Energy
• Data Center, Super Computer
• LPDDR
• Higher Speed, More Memory Size
• High Performance Mobile Device
• Smart Phone, Mobile Game, 5G
• DDR4/LPDDR4
• DDR5/LPDDR5

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 DDR〜DDR3 System Simulation
• Basic Simulation Flow

Schematic Design

PCB Stack-up
PCB Design Concept
Temporary Placement
Temporary Etch Length
Pre-Layout Simulation Layer Structure
PCB Design Design Rule

Layout Design

Design Verification
Post-Layout Simulation
Sign off

Manufacturing

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 DDR〜DDR3
• Features for PCB Design
• Multi-Driver Strength
• Multi-Value ODT (DDR2)
• Fly-by (DDR3)
• Considerations
• Typical/Worst
• Derating

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 Tolerance of IC Characteristics
• Drive: Slow - Fast
• Receiver: Slow - Fast

Fast
F/S F/F
• IO Model
• Fast/Typical/Slow
• Driver: Output Impedance
Ramp

Receiver
• Receiver: Threshold Voltage
• C Comp, Package L/C/R T/T

• Vcc Voltage
• Vtyp +/- 5~10% Fast
• IC Temperature
Slow
S/S S/F
Slow Driver Fast

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 Typ vs. Corner
• Fast Typ Slow

[Ramp]
• DDR4 2400 R_load = 50
| typ min max
• Driver: DQ dV/dt_r 4.1235E-01/6.4489E-11 3.8046E-01/8.4106E-11 4.4653E-01/5.2562E-11
• Receiver: DQ dV/dt_f 4.5987E-01/6.2372E-11 4.3947E-01/7.9203E-11 4.6741E-01/4.9982E-11
|************************************************************************
[Falling Waveform]
V_fixture = 1.2V
V_fixture_min = 1.14V
V_fixture_max = 1.26V
R_fixture = 50Ohm
C_fixture = 0F
| Time V(typ) V(min) V(max)
0.00000000E+00 1.19999848E+00 1.13999700E+00 1.25999947E+00
5.00000000E-12 1.19999849E+00 KEI Systems
1.13999700E+00 1.25999948E+00
1.00000000E-11 1.19999849E+00 1.13999700E+00 1.25999948E+00

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 Derating
• Timing Specification
• Reference: Threshold Voltage
• Timing differs based on Slew-Rate
• Standard is the value of 1v/ns
2v/ns 1v/ns

VthAC
VthDC
Vref
VthDC
VthAC

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 DDR3 System Simulation
• IBIS Model
• Timing Simulation
• Bus Simulation (Crosstalk)
• 8 Bit Parallel Signals
• PRBS
Typical
• Power Aware
Reasonable?
• Eye Pattern
Min Max
• Derating
• Worst Case/Typical Case
• Margin/Yield Rate Worst Case

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 DDR4/LPDDR4

• New Features
• DQ Vref Training/ZQ calibration
• Support Eye Mask
• No more Derating

Set
ODT/Driver
Controller Vref DDR Center of Convention
Ron:34/40
ODT: 34/40/48/60 Return Data
/120/240/OFF Same
Ron:34/40 Data
Write Different
Same? MPR
Convention of Values
Read
Return
Same
Data
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 DDR4/LPDDR4 System Simulation
• IBIS Model
Simulation Result
• Timing Simulation (Common Condition)
• Bus Simulation (Crosstalk)
• 8 Bit Parallel Signals Good
• PRBS NG
• Power Aware
• Eye Mask
Actual Board
• No More Derating (Tune-up Each Board)
• Best Case Analysis
• Any One Case is Good, Real Should be Better
• IBIS-AMI (Idea)
• Auto Model Selector
• Crosstalk Analysis, SSN Analysis
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 DDR5/LPDDR5
• New Features
• Analog Driver/Receiver
• Emphasis
• Equalizer
• Feature of PCI Express/High Speed Serial
• Separate Clock/DQ Write/DQ Read
• CMD/Address is Slower than DQ

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 DDR5 Simulation
• IBIS-AMI
• Emphasis, Equalization: IBIS Model Supports Driver/Receiver
• Crosstalk Analysis?
• SSN Effect?

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 Reference
• “Is Typ. Analysis Enough? What Is Corner Condition?”
S.Maeda, 2016 Asian IBIS Summit Tokyo

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