Applied Electronics/Practical Electronics Year 2024/2025

Lab 7

VHDL for Sequential Circuits

____________________

Lab Objectives

Upon completion of this lab, you should be able to

1. Use VHDL Sequential Statements to Implement D Flip Flops.

2. Use Different Approaches to Implement Synchronous Counters.

Equipment

1. Quartus Prime
2. DE0-CV Development Board (Figure 1)
3. USB Cable

Allocated Time: 2 hours

Figure 1: DE0-CV Development Board

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Applied Electronics/Practical Electronics Year 2024/2025

I. Background

I.1 Sequential Statements:

I.1.1 “Process” Statement

A process is a set of sequential instructions executed in a predefined order. A process has a name, which
is optional. A process has a sensitivity list. The execution of statements takes place in response to
changes of the signals in the sensitivity list. The sequence of statements is sequentially evaluated. The
syntax of the process statement is shown in figure 2.

[name:] process (sensitivity_list)

Declarations;
begin
sequence-of-statements;
end process;
Figure 2: The “Process” Statement

I.1.2. “if” Statement

In VHDL, “if” is a statement that is used to conditionally execute at least one sequential statement. The
execution depends on a certain condition. It is possible to nest statements, controlled by different
conditions using “elseif” branches (or “else if”). While the number of “elseif” is unlimited, there is only
one “else” branch. The “else” branch is the last instruction and comes at the end before the “elseif”
statement. What comes between the square brackets [ ] is optional. The syntax of the “if” statement is
shown in figure 3.

if (condition1) then
Sequence_of_statements;
[ elsif (condition2) then
Sequence_of_statements;
elsif (condition3) then
Sequence_of_statements;
…………………
………………… ]
else
[Sequence_of_statements];
endif;
Figure 3: The “if” Statement

I.1.3. “case” Statement

Depending on the value of an associated expression, the “case” statement selects for execution one of
several alternative sequences of statements. The syntax of the case statement is shown in figure 4.

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case expression is
when choice => sequential_statement;
when choice => sequential_statement;
……………
……………
when choice => sequential_statement;
end case;
Figure 4: The “Case” Statement

I.2 Implementing Sequential Circuits Using VHDL

I.2.1 Clocked D Flip Flops

A D flip flop, as illustrated in figure 5, has two synchronous inputs D and Clk (clock) and two
asynchronous inputs PRN (set) and CLRN (reset). The outputs of the flip flop are Q and Q ̅ (inverted
output), respectively. The operation of a D flip flop is very simple and is illustrated in Table 1. When
the asynchronous inputs are HIGH (PRN = 1 and CLRN = 1) and at the positive transition of the clock
signal, the input is assigned to the output (Q = D). The flip flop is reset when PRN = 1 and CLRN = 0.
The flip flop is set when PRN = 0 and CLRN = 1.

PRN
D Q
Clk
Q
CLRN

Figure 5: D clocked Flip Flop

D Clk Q
0 ↑ 0
1 ↑ 1

Table 1: Truth Table of a D Flip Flop

The VHDL code that implements a simple D flip flop is shown in figure 6. Notice that the two
asynchronous inputs PRN (Set) and CLRN (Clear) have been ignored in the VHDL description - as well
as the inverted output -.

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Figure 6: VHDL Implementation of D Flip Flop

The VHDL description of figure 6 could be easily expanded to include both asynchronous inputs and
the inverted output, respectively. The code could be then used as a building block (component) in
structural VHDL models to implement shift registers and counters.

I.2.2. Synchronous Counters

In both Lecture 6 and Lab 6, the methodology for designing synchronous counters using JK flip flops
has been introduced. In synchronous counters, the flip flops are simultaneously clocked using the same
clock signal. Figure 7 shows the state transition diagram of a MOD 5 synchronous counter as introduced
in both lecture 6 and lab 6.

Q0 Q1 Q2

000

111 001

110 010

101 011

100

Figure 7: State Transition Diagram of the 3-bit MOD 5 Synchronous Counter

The digital circuit that implements the MOD 5 counter is illustrated in figure 8.

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Q2 Q1

Q0 Q0 Q2 Q1
J Q J Q J Q
Q2
Clk Clk Clk
'1' K Q K Q '1' K Q
Q0+ Q2

Clock

Figure 8: 3-bit MOD 5 Synchronous Counter

Using sequential statements such process, case and if, different VHDL implementations could be
envisaged. Two of such implementations are illustrated in figure 9 and figure 10, respectively.

Figure 9: VHDL Description of a MOD 5 Synchronous Counter

using “process” and “case” Statements

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Figure 10: Behavioural Description of a MOD 5 Synchronous Counter

Using “process” and “if” Statements

Note that the first implementation is combining both “process” and “case” statements, while the second
one is combining “process” and “if” statements. All the changes in the outputs are taking place at the
rising edge of the clock signal (if (clock = ‘1’ and clock’event)).

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II. Task
1. Consider the VHDL description of figure 6 that implements a D Flip Flop. Expand the code to
implement a D flip flop with asynchronous inputs PRN (Set) and CLRN (Clear). Compile your
code and simulate the behaviour of your design. Don’t forget to log your results (screenshots of
VHDL description and simulation).

2. Expand the codes of figure 9 and figure 10 to implement a MOD-10 synchronous counter. Compile
and simulate the designs. Log your results (screenshots of both the VHDL codes and
simulations).

3. Create a symbol for the MOD 10 synchronous counter (any of the two designs will do). Combine
it with the Clock_Divider circuit, as shown in previous labs (download the clock divider files from
Blackboard). Assign pins and download your design into the DE0 CV board. Test it and show
your synchronous counter to your lab instructor.

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Deliverables: Submit a report including the objectives, the VHDL codes and simulations as logged
during the lab session (screenshots) and a conclusion and reflection - Please refer to the marking scheme
below. The front page of the report should include the module name, the module code, the lab
number/title and the student ID.

Submission Deadline: 14/01/25 @14:00 (online).

Submission point (where to upload the report): on the module page on Blackboard, select
“Learning Materials -> Teaching Block 1”, then open the “Labs” folder, then click on “Lab 7
– VHDL for Sequential Circuits - Upload Point”. Submission should be in PDF format.

Marking Sheet

Lab 7 – VHDL for Sequential Circuits (5 marks)

Category Novice Competent Proficient Weight

(0%) (50%) (100%)
Objectives and purpose of 5%
the lab

D flip flop 20%

- VHDL description of a D
flip flop with asynchronous
inputs.
- Simulation
Counters 40%
- VHDL descriptions of
counters
- Simulations.
Testing (to take place 30%
during a the lab session)
Conclusion and reflection 5%
Total 100%

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Appendix [1]

Pin Assignment of Switches

Pin Assignment of LEDs

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Pin Assignment of Push-buttons

[1] Terasic, DE0-CV User Manual (available from www.terasic.tw

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