CHAPTER 6: INTRODUCTION TO VHDL

Ø Introduction
Ø Domain of Description
Ø VHDL Example
Ø Behavioral Description
Ø Procedural Description
Ø Dataflow Description
Ø RTL Behavioral

INTRODUCTION

With the emergence of Integrated Circuit (IC) Technology and it’s development in
allowing more and more components on a single chip, digital systems have grown immensely in
complexity. As a result, detailed designing of the digital systems at the gate and the flip-flop level
has come out to be very tedious and time consuming. Hence, the importance of Hardware
Description Languages in the digital design process. A hardware description language allows a
digital system to be designed and debugged at a higher level before conversion to the gate and flip-
flop level. Use of synthesis computer-aided design tools to do this conversion is becoming more
widespread. An useful analogy would be that of writing software in a high level language like C
and then using a compiler to convert the programs to machine language. VHDL and Verilog are
the two most popular hardware description languages.

VHDL AND ITS DEVELOPMENTS

The acronym VHDL stands for VHSIC Hardware Description Language, and VHSIC in
turn stands for Very High Speed Integrated Circuit. However, as VHDL is a general-purpose
hardware description language, it can be used to describe and simulate the operation of a wide
variety of digital systems, ranging in complexity from a few gates to an interconnection of many
complex integrated circuits. VHDL was originally developed for the US military to allow a
uniform method for specifying digital systems. The VHDL language is now an IEEE standard and
is widely used in the industry.

· VHDL was initiated in the 1980s by the United States Department of Defence.
· The initial objective of the VHDL was modeling, thus, at that time only a simulator was
envisaged.
· Subsequently, tools for VHDL synthesis were developed.
DOMAINS OF DESCRIPTION

VHDL Description:

VHDL can be used to describe a digital system at several different levels- behavioural, data
flow, and structural.

Ø Behavioural Level: A digital circuit is specified in terms of its input and output behaviour. At
this level, the circuit does not include any implementation details, and can be regarded as a black
box.
Ø Data Flow Level: The circuit is specified in terms of the Boolean Logic equations, relating the
outputs to the inputs.
Ø Structural Level: The circuit is described by specifying what all does it comprise, e.g.
transistors, resistors, etc. and the various interconnections of the gates.

The four basic requirements of a Hardware Description Language are as follows:-

· Abstraction
· Modularity
· Concurrency
· Hierarchy
1) Abstraction: In VHDL, the components as well as systems can be described at various
levels of abstraction.
§ Gate and component delays.
§ Clock cycles.
§ Abstract behaviour without any notion of delays.

2) Modularity: A system generally consists of one or more components, which are referred
to as entities, having clear interfaces. The interface is what is known as entity declaration. In an
entity declaration, all the input and output ports of the component are clearly specified. The
internals of the component are referred to as the architecture declaration. In an architecture
declaration, we define the internal structure of an entity. The various outputs are declared and
assigned to the output ports. It is important to note that there can be multiple architectures even at
different levels of abstraction associated with the same entity.

3) Concurrency: More often than not the hardware that we synthesize is capable of
running several components simultaneously, i.e. it is concurrent. The idea of concurrency will be
made clearer below.

4) Hierarchy: The concept of hierarchy would be made explained by taking an example.

Consider a four-bit Binary Adder as a system. So, we have an entity 4Bit Adder (say). Now
suppose that our four-bit Binary Adder was made up of four one-bit binary adders. This can be
done by making separate entity declaration for the one-bit adder and use that in the architecture of
the 4Bit Adder. This is what is meant by hierarchy.

VHDL Example
The following is the VHDL representation of a two-input AND gate, whose inputs are a
and b, with c as the output.
entity AND is -- the name of entity is AND
port ( a, b: in bit; -- a and b are inputs of one bit each
c: out bit); -- c is a one-bit output
end AND; -- entity declaration ends

architecture behaviour of AND is -- name of architecture declaration is behaviour

begin
c <= a and b;
end behaviour;
The statement c<= a and b is a Concurrent Assignment Statement. One can have
concurrent assignment statements in VHDL, and therein does its power lies. The signal c is
assigned a value equal to a and b. This assignment is a concurrent assignment, i.e. the value of c is
updated by itself when any of the signals a or b changes. This is what makes VHDL different from
the programming languages like C or Pascal. Note that a,b and c here, are signals and not
variables (unlike in other programming languages), although variables are also defined in VHDL.
One more thing to note here is that in concurrent assignment statements the order in which
they are written does not matter.
For example,
architecture ....
signal d : bit;
d <= a and b || is equivalent ||c <= d or a
c <= d or a || to || d <= a and b
end ...
In traditional programming languages such assignments aren’t possible.

CONNRUENCY IN VHDL DESCRIPTION

The diagram given below shows how a number of active processes run simultaneously, or
concurrently, in VHDL. However the statements inside a process are executed sequentially.
We can say that concurrent statements are processes, which are
always active.
he above diagram shows the parallel running of n active processes. In VHDL, we say that the
processes are running simultaneously or concurrently, though, the statements inside each process
are executed sequentially.

NESTING OF STATEMENTS IN VHDL

There can be three types of Nesting in VHDL statements.

They are :
· Concurrent statements in a concurrent statement.
· Sequential statements in a concurrent statement.
· Sequential statements in a sequential statement.

This is illustrated in the figure given below.

Hierarchy in VHDL
In the figure given below, C0 to C7 are concurrent processes, while S1 to S12 are
sequential processes.
C1, C2 and C3 are concurrent processes which are embedded in another concurrent process
C0. In C1 there are two additional concurrent processes C4 and C5, while C2 has C6 and C7 as
concurrent processes.
In C3 , there are two sequential processes S11 and S12.
In C4, there are two sequential processes S1 and S2.
In C5, there are three sequential processes S3, S4 and S5.
In C6, there is a single sequential process S6.
In C7, there are four sequential processes S7, S8, S9 and S10.
BEHAVIORAL DESCRIPTION IN VHDL

MODELING STYLES

The following modeling styles are used in VHDL

· Semantic model of VHDL

· Structural Description

· Data Flow Description

· Algorithmic Description

· RTL Description

These modeling styles are used separately and there is no need to mix any two of them. The first
three styles have been discussed in the last class. The last two styles that form the behavioral
description will be discussed in this lecture and continued in the next.
CONCURRENT STATEMENTS IN VHDL

As discussed before, the following concurrent statements are used in VHDL.

Statement Function

Process Statement Behavior

Concurrent Procedure Call Behavior

Concurrent Signal Assignment Data Flow

Component Instantiation Structure

Generate Statement Structure

Block Statement Nesting

Concurrent Assertion Statement Error Check

We shall discuss some examples in VHDL now.

Example: D Flip Flop

The entity declaration of the flip flop is

entity DFF is
port (D, CLK : in bit ;
Q : out bit ; QN : out bit := '1') ;
end DFF ;

Please note that

 · The assignment of a value to a signal is called instantiation. For example QN has been
instantiated to the value '1'.

· The default value of instantiation of a signal is '0' so that we could also have written Q :
out bit := '0' ; QN : out bit := '1'

· CLK is just a name used to represent clock and we could use any other name as well.

· The modeling of the design is called simulation. Instantiation is allowed only in simulation
and not in synthesis. The constructs allowed in simulation are more than those allowed in
synthesis.

The following is the behavior architecture of DFF.

Architecture Beh of DFF is

begin
process (CLK)
begin
if (CLK = '1') then
Q <= D after 10 ns ;
QN <= not D after 10 ns ;
endif ;
end process ;
end Beh ;

Here are some points to be noted.

· Beh is an arbitrary name.

· The begins in the second and fourth lines match the ends in the last and the but last lines
respectively. The if statement in the fifth line ends with the endif.

· Each process is sensitive to some signals. The list of these signals is mentioned just after
process in parenthesis. The process is executed only when some item in the sensitivity list
changes. Here the process is sensitive to CLK. The CLK signal is also tested within the
process, and if CLK = '1', this means that a rising edge has just occurred on CLK. In this
case, Q is set equal to D, and QN is set to the complement of D. The 10 ns delay represents
the propagation time between the time the clock changes and the flip flop outputs change.
Sensitivity list is allowed only in simulation and not in synthesis.

· There may be several processes running within an architecture. The processes are
concurrent and interact with each other through signals.
CONCURRENT PROCESSES

Ø Concurrent Conditional Assignment : 4 to 1 Multiplexor

To model the MUX at the behavioral level, we can use a conditional assignment statement.

Data Flow Statement

y <= x0 when sel = 0

else x1 when sel = 1
else x2 when sel = 2
else x3 when sel = 3 ;

This concurrent event is executed whenever an event occurs on a signal used in one of the
expressions or conditions. if condition 1 is true then, sel is set to 0, else if condition 2 is true then ,
sel is set to 1 ,etc.

If a MUX model is used inside a process, a concurrent statement cannot be used. As an alternative,
the MX can be modeled using a case statement.

Ø As part of Process (Case Statement : 4-1 Mux)

case sel is
when 0 => y <= x0
when 1 => y <= x1
when 2 => y <= x2
when 3 => y <= x3
end case

The value of sel ( or in general, "expression" ) is found first. If it is equal to 0 ( or the first choice )
then the first statement ( or the first set of sequential statements ) is executed; if it is equal to 1 ( or
the second choice ) then the second statement ( or the second set of sequential statements ) is
executed, etc.

VARIABLES AND SIGNALS

Consider the following Architecture:

Architecture var of dummy is

signal trigger, sum : integer := 0 ;
begin
process
variable var1 : integer := 1 ;
variable var2, var3 : integer := 2 ;
 begin
wait on trigger ;
var3 := var1 + var2 ;
var1 := var3 ;
sum <= var1 ;
end process ;
end var ;

Ø The Concept of wait

This process will execute the sequential statements until a wait is encountered. Then it will wait
until the specified condition is satisfied ( here an event on trigger occurs ). It will then execute the
next set of sequential statements

until a wait statement is encountered. It will continue in this manner until the end of the process is
reached. Then it starts over again at the beginning of the process.

Wait statements can be of three different forms:

wait on sensitivity list;
wait for time expressions;
wait until boolean expression;

Note that

process ( trigger )
...
...

is equivalent to

process
...
...
wait on trigger ;
end process ;

Variables are to be defined within the process and are local to the process. It is not allowed to use
both wait and sensitivity list in the same process.wait is used in synthesis in a very limited manner.

A similar architecture declaration using signals instead of variables can be use to distinguish the
signals and variables.

Ø Another Architecture
Architecture sig of dummy is
signal trigger, sum : integer := 0 ;
signal sig1 : integer := 1 ;
signal sig2, sig3 : integer := 2 ;
begin
process
begin
wait on trigger ;
sig3 <= sig1 + sig2 ;
sig1 <= sig3 ;
sum <= sig1 ;
end process ;
end sig ;

Ø The concept of delta delay

The concept of delta delay is very important and basic to VHDL. In a process, several
sequential statements are executed ( sequentially ) at the same time and the assignments are
scheduled after an infinitesimal delay known as delta delay. But the actual simulation time
does not move forward.

The figure illustrates the concept of delta delay. At point A several expressions need to be
evaluated. There is an infinitesimal time delay of delta and the assignments occur simultaneously
at point B after the delta delay.

Ø Difference between variables and signals

The variables differ from signals in that they are 'containers', unlike signals that are 'nodes'. When
a variable assignment is executed, the variable is immediately updated without delay, not even a
delta delay. In contrast, when a signal assignment is executed, the signal is scheduled to change
after a delta delay. So in the first case ( in architecture var ), sum will get the value 3 ( equal to
var1 + var3 ) . In the second case ( in architecture sig ), the values of sig3, sig1 and sum are
updated only after a delta delay after an event on trigger. Hence sig1 gets the previous value of
sig3. But the simulation time does not move ahead by delta. So the value of sum is 1.

Hence the architecture var is equivalent to the following statements:

...
wait on trigger ;
sig3 <= sig1 + sig2 ;
wait on sig3 ;
sig1 <= sig3 ;
wait on sig1 ;
sum <= sig1 ;
...

In the following example, the new value of sig3 is assigned to sig1 since the assignment is
scheduled at time t +1+ delta and takes place at simulation time t +1, till when sig3 has got the new
value.

sig3 <= sig1 after 1 ns ;

wait for 1 ns ;
sig1 <= sig3 ;

The definitions and instantiation of signals is outside the process description while variable
definitions is inside.Note that anything between the processes have to go through signals.

Ø Constants

Constants can also be declared. Constants declared at the start of an architecture can be used
anywhere within that architecture, but constants declared within a process are local to the process.

PROCEDURAL DESCRIPTION
Procedures facilitate decomposition of VHDL code into modules. The following statements are
used in procedural description in VHDL. This will be discussed in the next class.

· process statements

· concurrent procedure calls

STATEMENTS IN PROCESSES & PROCEDURES

The following statements are used in processes and procedures in VHDL. These will be dealt in
the next class.

· assignments

· control statements

· procedure calls

· wait statements
DATAFLOW DESCRIPTION
In a dataflow description we describe the drivers for all the signals in a system using concurrent
assignment statements.
Example:
We start with an example, describing a 1-bit cascadable comparator.
First, we have to make an entity declaration

entity comp1 is
port(a,b,gt,eq,lt:in bit; a_gt_b, a_eq_b, a_lt_b:out bit);
end comp1;

This entity declaration declares an entity ‘comp1’ which has five input ports and three output
ports:

Comp1

A dataflow description of the comparator will use concurrent assignments to describe the drivers
for each of the signals or nodes in the circuit. The dataflow architecture for the 1-bit cascadable
comparator is:

architecture dataflow of comp1 is

signal s:bit;
begin
s<=(a and b)or(not a and not b);
a_gt_b<=(gt and s) or (a and not b);
a_lt_b<=(lt and s) or (not a and b);
end dataflow:

Architecture has to be declared in terms of an entity, that is, architecture always refers to a
particular entity. All the input and output ports declared in the entity are visible within the
architecture. The input ports can be used on the right hand side of the assignments and the output
ports can be used on the left-hand side of concurrent assignments.
In the above example all signals except ‘s’ are input-output ports. ‘s’ is an internal signal of the
entity.
CONCURRENT ASSIGNMENTS IN VHDL

The VHDL signal assignments as in the previous example are called concurrent assignments when
they are not contained in a process or a block. The VHDL simulator monitors the right-hand-side
of each concurrent statement, and every time a signal changes, the expression on the right hand
side is immediately re-evaluated. The new value is assigned to the signal on the left-hand-side after
an appropriate delay. When we are talking in terms of modeling the system, we may not be
concerned about the propagation delays in such a case, simulator assumes an infinitesimal
delay(D). Also, unlike a sequential statement the order of assignments is not important.

Each assignment that we write describes a driver for the signal on the left-hand-side of the
assignment.

a
s<=(a and b) or (not a and not b) s
b

gt
a_gt_b<=(gt and s) or (a and not b) a_gt_b s
a
b

lt
a_lt_b<=(lt and s)or (not a and b) a_lt_b s
a
b

a_eq_b eq
a_eq_b<=eq and s s
The driver need not be implemented explicitly, we can simply state the boolean equation which
describes the driver. All the drivers are acting concurrently.

CONDITIONAL EVALUATION USING GUARD

VHDL also has a mechanism for conditional evaluation of a concurrent assignment by using the
‘guard’. Physically, the guard represents a signal, which is used to control the functioning of a sub-
system, like the enable signal. In terms of modeling the ‘guard’ can also be used to block certain
‘unimportant’ statements, to enable faster simulation. For example, if we have large system in
which all the sub-systems are not required at the same time, we can ignore the sub-system and
enable a faster simulation.

s<=(a and b) or (not a and not b)

a
s
b

a_gt_b<=guarded (gt and s) or (a and not b)

gt
a_gt_b s
a
b
guard
a_lt_b<=guarded (lt and s)or (not a and b)

lt
a_lt_b s
a
b
a_eq_b<=guarded eq and s
guard

a_eq_b eq
s
guard
Role of guards

Guards play the following role in VHDL:

1. They enable conditional evaluation of the signal assignments and allow us to control the
whether the concurrent statement is evaluated or not.
2. Input changes may occur but the changes are to be registered only at certain points, for
example clocking of registers by using the guarded signal of kind register.
3. For enabling buses(guarded signals of kind bus)

RTL BEHAVIOUR

The RTL behavior description involves specifying the various operations to be performed in a
process. The behavioral description is procedural in which the textual order is also the order of
execution. Behavioral description uses sequential statements and control constructs to alter the
normal sequential flow. For example

process
in_ready: in bit;
while in_ready=’0’ loop
wait until clock’rising;
end loop;
x:=in_port1;
y:=in_port2;
wait until clock’rising;
while x/=y loop
if x>y then
wait until clock’rising;x:=x-y;
else
wait until clock’rising;y:=y-x;
end if;
end loop;
end process;

Note:
1. clock’ represents an attribute of clock and clock’rising is the associated event
attribute of the clock signal.
2. clock‘rising represents (clock’event and clock=’1’)
3. clock is an input signal and not a keyword

In_ready
(asynchronous)

In this example we have a process within which we have specified sequential statements to be
Clock
executed. The signal in_ready is asynchronous, to synchronize the signal we have to
introduce a wait statement.

In_ready (asyncronous)

Clock (synchronous wait for the

asynchronous signal)

Consider the statements

x:=in_port1;
wait until clock’rising;

The simulator does not require the wait statement the value is assigned to x immediately,
however, physically (in synthesis) the value needs to be stored in a clocked register. Since,
latching occurs only at the rising edge, we have to wait till the rising edge of the clock. An
asynchronous design needs a wait statement within a while loop for the data to actually latch
into the register.

This model assumes that all the associated delays are restricted to within the clock period. However, at
synthesis stages we will need to consider the timing issues. This kind of a description is the “true to the clock
cycle” description of behavior. Prediction can be done upto a clock cycle only.

Process with one statement only

If we have a process with one statement only we can model it by using a sensitivity list only.
process
begin
-- assignments and conditional constructs
wait until clock’rising;
end process;

such a process can be written in an equivalent manner as:

process(clock)
begin
if clock=’1’ then
-- assignments and conditional constructs
end process;

In such a process all the statements in the body are executed in a single clock cycle only. We can
control the flow of execution within the process (i.e. doing different computations in each
iteration) by using if-then-else.

FINITE STATE MACHINE

We can describe a finite state machine in VHDL by a behavioral description of the state-machine
using the case statement.

process
begin
case state_reg is
when state_0 => -- statements for state_0;
when state_1 => -- statements for state_1;
….
end case;
wait until clock’rising;
end process;

Note :
1. VHDL supports enumerated types so we can use statements like when state_0,
where state_0 is a signal of an enumerated type.
2. Statements for state_i will typically contain statements which perform the action
associated for the ith state and also change the state of the machine as required
3. We have to wait for the rising clock for the state transition to occur.

Finite state machine (dataflow)

A finite state machine can also be specified by a dataflow description. For the above example an
equivalent dataflow description would be:
block(clock’rising)
begin
block(state_reg=state_0 and guard)
begin
-- statements for state_0
end block;
block(state_reg=state_1 and guard)
begin
-- statements for state_1
end block;
...
end block;

In this case we have to use the guard for each set of concurrent blocks. The guard determines when
the block is executed, it is used for synchronization, in the above example. In case of nested blocks
the guard refers to the nearest outer guard set. For example, in the above code:

block(clock’rising) This guard refers to the outermost

begin guard signal
block(state_reg=state_0 and guard)
begin
-- statements for state_0
end block; Any guard statement
block(state_reg=state_1 and guard) within these blocks will
begin refer to the statement
-- statements for state_1 (state_reg=state_
end block; 0 and guard)
...
end block;

TEST BENCH

The test bench is used to test any design during the testing stages. It is a very useful concept during
the simulation stages. The design under test will have a set of input and a set of output.

Design
Input Under Output
Test
We can declare an entity testbench with no inputs and no outputs. The entity will consist of a test
pattern generator, a clock geenrator and a result check. These three components will be concurrent
processes with the design under test. To test various designs for the same system we can use the
same test bench simply replacing the design under test. We can test the same design with different
designs for the individual components. The test bench is particularly while working with large
designs.

PREVIOUS YEARS QUESTIONS

1. Consider a variable pulse generator or VPG. It accepts a 1-digit BCD input and
generates that many number of pulses e.g. if input is \6" then it would generate 6 pulses.
Only exception is that for input \0" it would generate 10 pulses. Write the behavioral
VHDL description of the VPG circuit as two processes.
· First process generates a periodic output “P" which is ON for 400 msec and OFF
for 600 msec.
· The second process takes three inputs; “P", “D0-3" (4-bit) and “dav" and produces
one output “Y". \D0-3" is a BCD input and “dav" is the data valid signal for the BCD
input. “Y" passes on the number of “P" pulses as specified by the “D0-3" input.
(Major –2003)

2. Assume all identifiers a, b, c, d and clk are declared to be bit type signals.
1. Consider the following process. Draw the waveform for c and d.
2. Write the VHDL structural description for two 2-input NAND gates with output of
first connected to one of the inputs of second with a, b and clk as the primary
inputs, c as the output of the first NAND gate and d as the final output.
3. Assuming the same inputs at a,b and clk, draw the waveforms for c and d.
process (clk)
begin
c <= a nand b;
d <= clk nand c;
end process;
(Quiz7 –2003)

3. A multiplier-accumulator consists of a 16X16 multiplier (32-bit output), a 36-bit adder

and a 36-bit register. The adder and the register are capable of adding upto 16 products
without overflow. The register is rising edge-triggered.
a) Write a VHDL structural description of the multiplier accumulator as composed of
these three components.
 b) Write a behavioral description of a multiplier-accumulator in VHDL where the
multiplication and accumulation is pipelined i.e for each clock cycle two inputs are
taken and multiplied by the multiplier and simultaneously the previous product is
accumulated. Assume * and + are available as basic operators for writing your
description.
(Remajor –2003)

4. A multiplier-accumulator consists of a 16X16 multiplier (32-bit output), a 36-bit adder

and a 36-bit register. The adder and the register are capable of adding upto 16 products
without overflow. The register is rising edge-triggered.
a) Write a structural description of the multiplier accumulator as composed of these
three components.
b) Write a behavioral description of a multiplier-accumulator in VHDL where the
multiplication and accumulation is pipelined i.e for each clock cycle two inputs are
taken and multiplied by the multiplier and simultaneously the previous product is
accumulated. Assume * and + are available as basic operators for writing your
description.
(Major –2002)