TPS51362

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22-V Input, 10-A Integrated FET Converter

With Ultra-Low Quiescent ( ULQ™)
Check for Samples: TPS51362

1FEATURES APPLICATIONS
•
2 Input Voltage Range: 3 V to 22 V • Notebook Computers (VCCIO)
• Output Voltage Range: 0.6 V to 2 V • Memory Rails (DDR VDDQ)
• 10-A Integrated FET Converter
• Fewest External Components DESCRIPTION
The TPS51362 is a high-voltage input, synchronous
• ULQ™-100 Mode of Operation to Enable Long
converter with integrated FET, based on DCAP-2™
Battery Life During System Standby control topology, which enables fast transient
• Soft-Start Time Programmable by External response and supports both POSCAP and all MLCC
Capacitor output capacitors. TI proprietary FET technology
• Switching Frequency: 800 kHz combined with TI leading-edge package technology
provides the highest density solution for single-output
• D-CAP2™ Architecture to Enable POSCAP and power rail such as VCCIO and VDDQ for DDR
All MLCC Output Capacitor Usage notebook memory, or any point-of-load (POL) in wide
• Integrated and Temperature Compensated application.
Low-Side On-Resistance Sensing for Accurate The key feature of the TPS51362 is its ULQ™ Mode
OCL Protection to enable low-bias current (100 µA in low power
• Powergood Output mode, enabled by LP#). This feature is extremely
OCL, OVP, UVP and UVLO Protections beneficial for long battery life in system standby
• Thermal Shutdown (non-latch) mode.
• Output Discharge Function The feature set includes switching frequency of 800
kHz. Programmable soft-start time with an external
• Integrated Boost MOSFET Switch
capacitor. auto skip, pre-bias startup, integrated
• 28-Pin, 3.5-mm × 4.5-mm, RVE, QFN Package bootstrap switch, power good, enable and a full suite
with 0.4-mm Pitch and 1-mm Height of fault protection schemes, including OCL, UVP,
OVP, 5-V UVLO and thermal shutdown.
It is packaged in 3.5 mm × 4.5 mm, 0.4-mm pitch, 28-
pin QFN (RVE), and specified from -10°C to 85°C.

SIMPLIFIED APPLICATION

VSNS
VIN
GSNS
7.4 V
23 22 21 20 19 18 17 16 15 to
20 V
GSNS VSNS SLEW TRIP GND V5 VIN VIN VIN
24 REFIN2 PGND 14

25 REFIN PGND 13

26 VREF TPS51362 PGND 12

27 NU PGND 11

28 EN PGND 10
PGOOD LP# MODE NC BST SW SW SW SW
1 2 3 4 5 6 7 8 9

EN VOUT
PGOOD 1.05 V

LP# UDG-13052

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 ULQ, DCAP-2 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION (1) (2)

MINIMUM
ORDERABLE DEVICE
TA PACKAGE PINS TRANSPORT MEDIA ORDER
NUMBER
QUANTITY
Plastic Quad Flat Pack TPS51362RVET Small tape-and-reel 250
–10°C to 85°C 28
(QFN) TPS51362RVER Large tape-and-reel 3000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

ABSOLUTE MAXIMUM RATINGS (1)

over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
VIN –0.3 30
36
BST transient <10 ns 38
w/r/t SW 6
Input voltage range (2) SW 30 V
EN, TRIP, NU, MODE, V5, LP# -0.3 6
SLEW, VSNS, REFIN, REFIN2 –0.3 3.6
GSNS –0.35 0.35
PGND -0.3 0.3
PGOOD –0.3 6
Output voltage range (2) VREF –0.3 3.6 V
NC –5 36
Human body model (HBM) QSS 009-105 (JESD22-A114A) 2000 V
Electrostatic discharge
Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) 500
Junction temperature range, TJ –10 150 °C
Storage temperature range, Tstg –55 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

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THERMAL INFORMATION
TPS51362
THERMAL METRIC (1) QFN (RVE) UNITS
(28 PINS)
θJA Junction-to-ambient thermal resistance 40.2
θJCtop Junction-to-case (top) thermal resistance 22.8
θJB Junction-to-board thermal resistance 20.1
°C/W
ψJT Junction-to-top characterization parameter 1.6
ψJB Junction-to-board characterization parameter 19.4
θJCbot Junction-to-case (bottom) thermal resistance 2.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN 3 22
Supply voltage range
V5 4.6 5.5
BST –0.1 33.5
SW –3 27
EN, TRIP, NU, MODE, LP# –0.1 5.5
Input voltage range V
SLEW, VSNS, REFIN, REFIN2 –0.1 3.5
GSNS –0.1 0.3
PGND –0.1 0.1
PGOOD –0.1 5.5
Output voltage range
VREF, SLEW –0.1 3.5
Operating free-air temperature, TA –10 85 °C

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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V, VV5 = 5 V, MODE = GND, VEN = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
TA=25°C, No load, VEN = 5 V, LP # = 0 V 100 μA
IV5 V5 supply current
TA=25°C, No load, VEN = 5 V 560
IV5SDN V5 shutdown current TA=25°C, No load, VEN = 0 V 1 μA
VREF OUTPUT
IVREF = 30 µA, w.r.t. GSNS 2 V
VVREF Reference voltage
0 µA ≤ IVREF ≤ 300 µA, -10°C ≤ TA ≤ 85°C -1% 1%
IVREF(OCL) Current limit (VVREF–VGSNS) = 1.7 V 0.4 1 mA
VOLTAGE AMPLIFIER
IVSNS VSNS input current VVSNS = 1 V -1 1 μA
IVSNS(DIS) VSNS discharge current VEN = 0 V, VVSNS = 0.5 V 12 mA
SMPS FREQUENCY
tOFF(min) Minimum off-time 320 ns
tDEAD1 Deadtime1 (1) SW rising to falling 10 ns
(1)
tDEAD2 Deadtime2 SW falling to rising 10 ns
INTERNAL BOOT STRAP SW
VFBST Forward foltage VV5 - BST, TA = 25°C, IF = 10 mA 0.1 0.2 V
IBST BST leakage current TA = 25°C, VBST = 14 V, VSW = 7 V 0.01 1.5 μA
MOSFET ON-RESISTANCE
RDS(on)H High-side on-resistance TA = 25°C, VV5 = 5 V 17.5 mΩ
RDS(on)L Low-side on-resistance TA = 25°C, VV5 = 5 V 8.75 mΩ
LOGIC THRESHOLD
VMODE(TH) MODE threshold voltage MODE = Float 2.5 V
VLL EN low-level voltage 0.35 V
VLH EN high-level voltage 0.9 V
VL(HYST) EN hysteresis voltage 0.25 V
VL(LK) EN input leakage current -1 0 1 μA
VLL LP# low-level voltage 0.35 V
VLH LP# high-level voltage 0.85 V
VL(HYST) LP# hysteresis voltage 0.4 V
VL(LK) LP# input leakage current -1 0 1 μA
SOFT-START
ISS Soft-Start current Soft-start current source 10 μA
PGOOD COMPARATOR
VPGTH PGOOD threshold PGOOD in from lower (startup) 92%
IPG PGOOD sink current VPGOOD = 0.5V 6 mA
tPG(CMPSS) PGOOD start-up delay PGOOD comparator startup delay 1.5 ms
IPG(LK) PGOOD leakage current -1 0 1 μA

(1) Ensured by design.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V, VV5 = 5 V, MODE = GND, VEN = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
OVERCURRENT LIMIT LEVEL
VTRIP = 0 V, valley current set point, TA=25°C 7 8 9 A
IOCL Current limit threshold
VTRIP = 5 V, valley current set point, TA=25°C 10.5 12 13.5
VZC (2) Zero cross detection offset 0 mV
PROTECTIONS
VPOR V5 POR threshold voltage (2) Reset OVP fault 1.7 V
V5 POR threshold voltage mV
VPORHYS Reset OVP fault hysteresis 85
hysteresis (2)
Wake-up 4.3 4.4 4.6 V
VUVLO V5 UVLO threshold voltage
Shutdown 3.8 4 4.2
VOVP OVP threshold voltage OVP detect voltage 118% 120% 123%
tOVPDLY OVP propagation delay With 100 mV overdrive 430 ns
VOOB OOB threshold voltage 105.5% 109.5%
VUVP UVP threshold voltage UVP detect voltage 63% 66% 69%
tUVPDLY UVP delay 1 ms
THERMAL SHUTDOWN
Shutdown temperature 140 °C
TSDN Thermal shutdown threshold (2)
Hysteresis 10

(2) Ensured by design.

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DEVICE INFORMATION

RVE PACKAGE
28 PINS
(TOP VIEW)

GSNS

SLEW
VSNS

TRIP

GND

VIN

VIN

VIN
V5
21
22
23

20

19

18

17

16

15
24

14
REFIN2 PGND

13
25
REFIN PGND

12
26
VREF Thermal Pad PGND

11
27
NU PGND

28

10
EN PGND

8
5

9
PGOOD

LP#

NC
MODE

SW

SW

SW

SW
BST

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PIN FUNCTIONS
NAME NO. I/O/P (1) DESCRIPTION
Power supply for internal high side MOSFET. Connect a 0.1-µF bootstrap capacitor between this pin and
BST 5 I
SW pin.
EN 28 I Enable signal, 1.05-V logic compatible.
GND 19 — General device ground.
GSNS 23 O GND sense input. Connect GSNS to general/system ground or GND sensing point at the output return.
LP# 2 I Low power signal (active low) to indicate the converter entering ULQ™ mode. 1.05-V logic compatible.
MODE 3 I Frequency (800 kHz) programmable input (see Table 2).
NC 4 — Not connected.
NU 27 — Not used for external applications.
10
11
PGND 12 — Power ground. Connect to the system ground.
13
14
PGOOD 1 O PGOOD output. Connect a pull-up resistor with a value of 100 kΩ to this pin.
Power
29 — Connect to system ground by multiple vias.
PAD
REFIN 25 I Target output voltage input pin. 0.6 V to 2 V, 1.05 V/1.2 V built-in (GND and Open) (see Table 1).
REFIN2 24 I Tie to GND or float. This input is used to determine the fixed voltage setpoint (see Table 1).
SLEW 21 O Connect a capacitor between this pin and GND for soft start and integrator functions.
6
7
SW O Switching node output. Connect external inductor.
8
9
TRIP 20 I OCL programmable input (see Table 3).
V5 18 I 5-V power supply for analog circuits and gate driver.
15 I
VIN 16 I Power supply input pin. Apply 3-V to 22-V of supply voltage.
17 I
VREF 26 O 2-V reference output. Connect a 0.1-µF ceramic capacitor between this pin and the GNDS pin.
VSNS 22 I Output voltage sense input.

(1) I = Input, O = Output, P = Power, G = Ground

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FUNCTIONAL BLOCK DIAGRAM

REFIN REFIN2

PGOOD
VREFIN – 34% +
UV VREFIN + 20% +
VREF Reference
Reference
Detection
Delay
GSNS
+ +
OV
VREFIN + 20%
EN Soft-Start VREFIN - 8/34%

Control Mode
SLEW On-Time MODE
Control Logic
· On/Off Time Selection
VSNS · Minimum On /Off
+ PWM · SKIP/FCCM BST
VREFIN + · OCL/OVP/UVP
· Disharge VIN

Discharge

Phase SW
Compensation

ULQ
LP#
Control XCON
tON V5
One -
Shot
OCL OC
TRIP +
TRIP Reference
Detection
Voltage
NOC
+ 5-V UVLO
PGND
+
+ V5OK
ZC
4.4 V/4.0 V

GND

TPS51362

UDG-13060

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TYPICAL CHARACTERISTICS
EFFICIENCY EFFICIENCY
vs vs
OUTPUT CURRENT OUTPUT CURRENT
100 100
VIN = 7.4V VIN = 7.4V
VIN = 11.1V VIN = 11.1V
90 VIN = 20V 90 VIN = 20V
Efficiency (%)

Efficiency (%)
80 80

70 70

fSW = 800kHz fSW = 800kHz

60 LOUT = 0.33µH 60 LOUT = 0.33µH
TA = 25°C TA = 25°C
VOUT = 1.05V VOUT = 1.2V
50 50
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) G001
Output Current (A) G002

Figure 1. Figure 2.

EFFICIENCY FREQUENCY
vs vs
OUTPUT CURRENT OUTPUT CURRENT
100 1000
fSW = 800kHz VIN = 7.4V
950 LOUT = 0.33µH VIN = 11.1V
90 TA = 25°C VIN = 20V
900 VOUT = 1.05V
Frequency (kHz)
Efficiency (%)

80 850

800
70 750
fSW = 800kHz 700
60 VIN = 7.4V LOUT = 0.33µH
VIN = 11.1V TA = 25°C 650
VIN = 20V VOUT = 1.35V
50 600
0.001 0.01 0.1 1 10 1 2 3 4 5 6 7 8 9 10
Output Current (A) G003
Output Current (A) G004

Figure 3. Figure 4.

FREQUENCY OUTPUT VOLTAGE

vs vs
OUTPUT CURRENT OUTPUT CURRENT
1000 1.07
fSW = 800kHz VIN = 7.4V
950 LOUT = 0.33µH VIN = 11.1V
TA = 25°C VIN = 20V
900 VOUT = 1.35V 1.06
Output Voltage (V)
Frequency (kHz)

850

800 1.05

750

700 1.04 fSW = 800kHz

LOUT = 0.33µH VIN = 7.4V
650 TA = 25°C VIN = 11.1V
VOUT = 1.05V VIN = 20V
600 1.03
1 2 3 4 5 6 7 8 9 10 0.001 0.01 0.1 1 10
Output Current (A) G005
Output Current (A) G006

Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT VOLTAGE GAIN and PHASE
vs vs
OUTPUT CURRENT FREQUENCY
1.22 1.38

1.37
1.21
Output Voltage (V)

Output Voltage (V)

1.36

1.20 1.35

1.34
1.19 fSW = 800kHz fSW = 800kHz
LOUT = 0.33µH VIN = 7.4V LOUT = 0.33µH VIN = 7.4V
1.33
TA = 25°C VIN = 11.1V TA = 25°C VIN = 11.1V
VOUT = 1.2V VIN = 20V VOUT = 1.35V VIN = 20V
1.18 1.32
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) G007
Output Current (A) G008

Figure 7. Figure 8.

GAIN and PHASE GAIN and PHASE

vs vs
FREQUENCY FREQUENCY
80 450 80 450
Power Stage Design = 0.33µH + 6 × 22µF fSW = 800kHz Power Stage Design = 0.33µH + 6 × 22µF fSW = 800kHz
400 400
60 IOUT = 10A 60 IOUT = 10A
TA = 25°C 350 TA = 25°C 350
40 VIN = 12V 300 40 VIN = 12V 300
VOUT = 1.2V VOUT = 1.35V
250 250
Gain (dB)

Gain (dB)
Phase (°)

Phase (°)
20 200 20 200

0 150 0 150
100 100
−20 50 −20 50
0 0
−40 Gain −40 Gain
Phase −50 Phase −50
−60 −100 −60 −100
100 1k 10k 100k 1M 100 1k 10k 100k 1M
Frequency (Hz) G010
Frequency (Hz) G011

Figure 9. Figure 10.

OUTPUT VOLTAGE RIPPLE OUTPUT VOLTAGE RIPPLE

vs vs
OUTPUT CURRENT (IOUT = 0.1A) OUTPUT CURRENT (IOUT = 1A)

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT VOLTAGE RIPPLE
vs vs
OUTPUT CURRENT (IOUT = 10A) LOAD TRANSIENT RESPONSE

Figure 13. Figure 14.

vs vs
START-UP SHUTDOWN

Figure 15. Figure 16.

AMBIENT TEMPERATURE
vs vs
LP TOGGLE OUTPUT CURRENT
90

80
Ambient Temperature (°C)

70

60

50

40
fSW = 800 kHz
30 200 LFM VIN = 20 V
Natural Convection VOUT =1.5 V
20
0 1 2 3 4 5 6 7 8 9 10
Output Current (A) G012

Figure 17. Figure 18.

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APPLICATION INFORMATION

Functional Overview
The TPS51362 is a 10-A, integrated FET synchronous step-down converter with differential voltage feedback
support.
It uses adaptive on-time D-CAP2 for compensation-less stable loop operation in POSCAP, POSCAP/MLCCs and
all MLCCs output capacitor configurations.
TPS51362 automatically operates in discontinuous mode to optimize light-load efficiency. An 800-kHz switching
frequency enables optimization of the power train for cost, size and efficiency performance of the design. The
key feature of the TPS51362 is its ULQ™ mode to enable low-bias current (100 µA in low power mode, enabled
by LP#). This feature is extremely beneficial for long battery life in system standby mode.

VREF, REFIN, REFIN2 and Output Voltage

This device provides a 2.0-V, accurate voltage reference from the VREF pin. This output has a 300-uA sourcing
current capability to drive voltage setpoint reference through a voltage divider circuit as shown in Figure 19. To
ensure higher overall system voltage accuracy, the sum of the total resistance from VREF to GND should be
designed to be more than 67kohm. A MLCC capacitor with a value of 0.1uF or larger should be attached close to
the VREF pin. The voltage setpoint range supported by this device is between 0.6 V and 2.0 V.
This device also supports resistor-less fixed voltage operation by the use of both REFIN and REFIN2 pins.
Table 1 lists all the possible fixed voltage configurations by the REFIN and REFIN2 pin. The TPS51362 detects
the state of both REFIN and REFIN2 during the initial startup and decides the output voltage setpoint for the
operation.

Table 1. REFIN and REFIN2 Pin Settings

VOLTAGE (V)
VOUT OUTPUT
REFIN PIN REFIN2 PIN VOLTAGE (V)
(VREFIN) (VREFIN2)
GND GND 1.05
Float GND 1.2
GND Float 1.5
Float Float 1.35
Either GND or
Resistor dividers Adjustable from 0.6 to 2.0
Float

VREF 2 V
TPS51362
Either
REFIN2
R1
REFIN

R2 VREF
0.1 mF

UDG-13052

Figure 19. Setting the Output Voltage

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PWM Operation
TPS51362 employs DCAP2 mode operation. It uses an internal phase compensation network (RC1, RC2, CC1, CC2
and gain) to work with very low ESR output capacitors such as multi-layer ceramic capacitor (MLCC). The role of
such network is to sense and scale the current ripple component of the output inductor current information and
then use it in conjunction with the voltage feedback signal to achieve loop stability of the converter.
The transconductance (gM) amplifier and SLEW capacitor (C1) forms an integrator. The output ripple voltage
generated is inversed and averaged by this integrator. The AC information is superimposed onto otherwise DC
information and forms a reference voltage at the input of the PWM comparator. As long as the integrator time
constant is much larger than the inverse of the loop crossover frequency, the AC component is negligible.
gM f
£ 0
(2p ´ C1) 10
where
• gM is 60 µS
• f0 is 1/3 or 1/4 of the switching frequency (fSW) (1)
The voltage difference (VSLEW – VVSNS) is then compared to the G×(CSP-CSN) (see Figure 21) voltage at the
PWM comparator inputs. The PWM comparator creates a SET signal to turn on the high-side MOSFET during
each cycle when the current level falls below the loop demand (see Figure 20).

PWM

Inductor Current

REFIN
Output Voltage

SLEW

CSP - CSN

CSP - CSN

SLEW - VOUT

(1)
tON UDG-13015
Time

(1)
Figure 20. On-Time Waveforms
(1) ON time is initiated by (VOUT-SLEW) and (CSP-CSN) crossover

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The device operates at one distinct switching frequencies, 800 kHz. The switching frequency is configured by
MODE pin for this converter operation (see Table 2). For stable operation of the buck converter, it is generally
recommended to have a unity gain crossover (f0) of 1/4 or 1/3 or the switching frequency. (see Table 2).

Table 2. Mode and Recommended Frequency Settings

FREQUENCY (kHz)
MODE CROSSOVER (f0)
SWITCHING (fSW)
MIN MAX
FLOAT 200 267 800

Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as the
following equation is satisfied.
1 1
fLC = £ ´ f0
2p ´ LOUT ´ COUT 10
(2)
Operating in D-CAP2 mode, the overall loop response is dominated by the internal phase compensation network.
The compensation network is designed to have two identical zeros at 8 kHz (800-kHz operation) in the frequency
domain, which serves the purpose of splitting the LC double pole into one low frequency pole (same as the L-C
double pole) and one high-frequency pole (greater than the unity gain crossover frequency).

VIN

VSNS CC1 SW
R C1
22
CC2 RC2

C1 SLEW CSP LX
Control
21 CSN G VOUT
– Logic
– and
+ PWM Driver
REFIN + Comparator ESR
R LOAD
25
C OUT

PGND

VREF
R1
26
+ 2.0 V
R2
TPS51362

UDG-13054

Figure 21. Simplified Architecture Illustrating DCAP2 Mode

Light-Load Operation
The mandatory light load operation for TPS51362 is referred to as auto skip. In auto-skip mode, the control logic
automatically reduces its switching frequency to improve light load efficiency. To achieve this intelligence, a zero
crossing detection comparator is used to prevent negative inductor current by turning off the low side FET when
the SW crossing zero is detected. The equation below shows the boundary load condition of this skip mode and
continuous conduction operation.
(V - VOUT ) VOUT 1
ILOAD(LL ) = IN ´ ´
2 ´ LX VIN fSW (3)

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Power Sequences: Soft-Start and Power Good

Prior to asserting EN high, the power stage conversion voltage and V5IN voltage should be up and running.
When EN is asserted high, TPS51362 provides soft start operation to suppress in-rush current during startup.
The soft start action is achieved by an internal SLEW current of 10 µA (typ) sourcing into a small external MLCC
capacitor connected from SLEW pin to GND.
Use Equation 4 to determine the soft-start timing.
V
tSS = CSLEW ´ OUT
ISLEW

where
• CSLEW is the soft-start capacitance
• VOUT is the output voltage
• ISLEW is the internal, 10-µA current source (4)
The TPS51362 includes a PGOOD open drain output. During the startup, once the output voltage is slewing up
within –8% of the final setpoint target, the PGOOD becomes asserted after 1.5 ms of delay from the end of the
soft-start period. During the operation, if the output voltage rises beyond 120% (typ) of the setpoint, the PGOOD
pin becomes immediately de-asserted without hysteresis. Re-asserting the PGOOD pin requires either resetting
either the V5IN pin or the EN pin. If the output voltage falls below 68% (typ) of the setpoint, the PGOOD pin
becomes immediately de-asserted without hysteresis. Re-asserting the PGOOD pin requires resetting either the
V5IN pin or the EN pin.

Fault Protection

Overcurrent Limit
TPS51362 integrates both high side and low side FETs to support a maximum DC current of 10-A operation. The
current sensing method employed for over current limit is to monitor the SW node during the “ON” state of the
low side FET for each switching cycle. TRIP pin is used to program one of the two current limits for TPS51362
operation (see Table 3). When the overcurrent limit is detected, the converter does not allow the next “ON” cycle
for the high side FET until the overcurrent limit is no longer reached. This ensures the safe operation of the
converter. And when the overcurrent limit condition persists, the current to the load exceeds the current to the
output capacitors, the output voltage tends to fall. When the output voltage falls below the undervoltage
protection threshold, the converter latch shut down.

Table 3. TRIP Pin Settings

TYPICAL OCL
TRIP
LIMIT IOCL (A)
GND 8
5V 12

Negative Overcurrent Limit

TPS51362 is also protected by the negative over current limit. Both positive and negative current limit is
programmed by the TRIP pin. Negative current limit level is the same as that of positive current limit level (see
Table 3). During the normal converter operation, negative current is not allowed due to the mandatory light load
operation for this device (Auto Skip). It is during the OOB or OVP operation, negative overcurrent might be
engaged.

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Out-of-Bounds Operation (OOB)

When the output voltage rises to 8% above the target value, the out-of-bound operation starts. During the OOB
operation, the controller operates in forced PWM-only mode by turning on low side FET. Turning on the low side
FET beyond the zero inductor current can quickly discharge the output capacitor thus causing VOUT to fall quickly
towards setpoint. During the operation, the cycle by cycle negative current limit is also activated to ensure the
safe operation of the internal FETs.

Overvoltage Profection (OVP) and Undervoltage Protection (UVP)

When the output voltage rises to a level 20% (typ) higher than the setpoint voltage, an overvoltage condition is
present. When a 0-V event is detected, the converter turns off the high side FET and turns on the low side FET.
The operation continues until the cycle by cycle negative current limit is reached and low side FET is turned off
and high side FET is turned on, for a minimum on-time. After the minimum on-time expires, the high side FET is
driven off and low side FET is driven on again until negative current limit is reached or VOUT is discharged to 0 V.
When the VOUT is discharged to 0 V, both high-side and low-side FETs are latched off. An OVP fault requires the
V5IN voltage to fall below POR threshold or EN reset to clear.

Undervoltage Protection (UVP)

The undervoltage protection (UVP) is set when the VOUT voltage falls below 68% (typ) of the setpoint voltage for
1msec or longer. In this fault condition, the converter turns off both high-side and low-side FETs. The UVP
function is enabled after 1.4 ms of soft start completion. An UVP fault requires 5-V UVLO or EN reset.

V5IN Undervoltage Lockout (UVLO) Protection

TPS51362 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower
than UVLO threshold voltage, Vout is shut off. This is a non-latch protection.

Power-On-Reset (POR)
To prevent single rail supply voltage brown-out due to output OV condition, when the output voltage is shut down
due to OVP fault, Power-on-Reset (POR) on V5IN is implemented. To reset OVP fault, V5IN voltage must fall
below POR threshold voltage of 1.7 V (typ) or EN reset to clear.

Thermal Shutdown
TPS51362 includes an internal temperature monitor. If the die temperature exceeds the threshold (published in
the EC table of this datasheet), the converter will be shutdown. This is a non-latch protection and the operation is
restarted with soft-start sequence when the device temperature is reduced by the hysteresis.

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DESIGN PROCEDURE

Introduction
The simplified design procedure is done for a VCCIO rail for Intel platform application using TPS51362.

Step One: Determine the system specifications.

The VCCIO rail requirements provide the following key parameters:
• VOUT = 1.05 V
• ICC(max) = 6 A
• IDYN(max) = 4 A

Step Two: Determine the power supply design specifications.

The input voltage range and operating frequency are of primary interest. For this example:
• 7.4 V ≤ VIN ≤ 19.5 V
• fSW = 800 kHz

Step Three: Set the output voltage.

TPS51362 supports resistor-less fixed voltage operation by the use of both REFIN and REFIN2 pins (see
Table 1). Grounding both REFIN and REFIN2 pins provides a 1.05-V fixed output setpoint.

Step Four: Determine inductance value and choose inductor.

Smaller values of inductor have better transient performance and smaller physical size but higher ripple and
lower efficiency. Higher values have the opposite characteristics. It is common practice to limit the ripple current
to 25% to 50% of the maximum current. For this example,use 30% as a starting point. IL(P-P)= 6 A × 0.30 = 1.8 A.
For a switching frequency of 800 kHz, maximum 19.5-V input and 1.05-V output.
æ VOUT ö æ 1.05V ö
(VIN - VOUT )´ ç ÷ (19.5 V - 1.05 V )´ ç ÷
L=
V ´ dT
= è SW ´ VIN ø
f
= è 800kHz ´ 19.5 V ø = 0.68 mH
IP-P IP-P 1.8 A (5)
For this application, a 0.68-µH, 6.8 mm × 7.3 mm × 3.0 mm inductor with typical DCR of 4.8 mΩ and heating
current of 16 A is chosen. The Cyntec part number of the inductor is PIMB063T.

Step Five: Calculate SLEW capacitance.

The SLEW pin is used to program the soft-start time. During soft-start operation, the current source used to
program the SLEW rate is 10 µA (typ). In this design example, the soft-start timing should be target to be in the
range of 500 µs to 2 ms. The proper slew rate design minimizes large inductor current perturbation during the
startup, thus reducing the possibility of acoustic noise in the system.
dt
CSLEW = ISLEW ´ = 10nF
DVOUT (6)
• ISLEW = 10 µA,
• dt = tSS = 1 ms
• ΔVOUT = 1.05 V

Step Six: Select the proper OCL.

There are two options for the over current limit (see Table 3). For this application example, because ICC(max) =
6 A, the proper OCL level should be set at least 30% over the ICC(max) level, which makes the 8-A OCL
appropriate for this design. Grounding the TRIP pin achieves this effect.

Step Seven: Determine the output capacitance.

The amount of the output capacitance needed for this design is both a function of loop stability and of transient
requirement.

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Stability Considerations
The switching frequency of the design example is 800 kHz (which is set by the MODE pin, see Table 3). For D-
CAP2 mode operation, it is generally recommended to have a unity gain crossover (f0) of less than 1/4 or 1/3 of
the switching frequency, which is approximately between 200 kHz and 266 kHz. In this design example, use 1/4.
f
f0 = SW = 200kHz
4 (7)
Given the range of the recommended unity gain crossover frequency, the power stage design is flexible, as long
as the L-C double pole frequency is less than 10% of f0.
When the above criteria is met, the internal compensation network provides sufficient phase boost at the unity
gain crossover frequency such that the converter is stable with sufficient phase margin (greater than 60 deg.).
When the ESR frequency of the output bulk capacitor is in the vicinity of the unity gain crossover frequency of
the loop, additional phase boost can be achieved. This applies to higher ESR output bulk capacitor, POSCAP
and SPCAP.
When the ESR frequency of the output capacitor is beyond the unity gain crossover frequency of the control
loop, no additional phase boost is achieved. This applies to low or ultra low ESR output capacitor, such as
MLCCs.
For this application example,consider only all MLCCs for output capacitors. Based on Equation 3 and Equation 7,
the minimum capacitance for stable operation is calculated to be 110 µF.

Transient considerations
• IDYN(max) = 4 A
• di/dt = 2.5 A/µs
• VOUT deviation = ±3% for the given transient
Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load/release.
2 æV ´t ö
( )
L ´ DILOAD(max) ´ ç OUT SW + tMIN(off ) ÷
ç VIN(min) ÷
COUT(min_ under) = è ø
æ æ VIN(min) - VOUT ö ö
2 ´ DVLOAD(insert) ´ ç ç ÷ ´ tSW - tMIN(off ) ÷ ´ VOUT
çç VIN(min) ÷ ÷
èè ø ø (8)
2

COUT(min_ over) =
(
LOUT ´ DILOAD(max) )
2 ´ DVLOAD(release) ´ VOUT
(9)
Based on these calculation, to meet the transient requirement, the minimum amount of capacitance in this design
is 164 µF.
Considering both stability and transient, the minimum capacitance is 164 µF. The design example uses 8, 22-µF
capacitors with minor consideration of the MLCC derating for both DC and AC effect.

Step Eight: Select decoupling and peripheral components.

For the TPS51362, peripheral capacitors use the following minimum values of ceramic capacitance. X5R or
better temperature coefficient is recommended. Tighter tolerance and higher voltage rating are always
appropriate.
• V5IN decoupling ≥ 2.2 µF, ≥ 10 V
• VREF decoupling 0.1 µF to 1 µF, ≥ 4 V
• Bootstrap capacitor ≥ 0.1 µF, ≥ 10 V
• Pull-up resistors on PGOOD, 100 kΩ

Step Nine: Layout guidelines.

Figure 22 applies to the layer where device is situated. Additional reinforcement of VIN, PGND, and VOUT
through vias are always recommended.
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GSNS

SLEW
VSNS

TRIP
GND

VIN
VIN
VIN
V5
2 2 2 2 1 1 1 1 1
3 2 1 0 9 8 7 6 5
REFIN2

1
4
PGND
4
2

1
3
REFIN PGND
5
2

VREF

1
2
PGND
6
2

1
1
NU PGND
7
2

PGND

1
0
EN
8
2

1 2 3 4 5 6 7 8 9
PGOOD

MODE

SW
SW
SW
BST
SW
LP#

NC

Figure 22. TPS51362 Design Layout

Input capacitors, output capacitors, and the output inductor are the power components and should be placed on
one side of the PCB. Small signal components can be placed on the same side of the PCB with proper ground
isolation or the opposite side with at least one inner ground plane in between, depending on the
system/motherboard design requirement.
All sensitive analog traces and components such as VSNS, GSNS, SLEW, VREF, REFIN and REFIN2 should be
placed away from the high voltage switching node, such as SW and BST to avoid switching noise coupling. Use
internal layer(s) as ground plane(s) and shield feedback traces from power traces.
VSNS can be connected directly to the output voltage sense point at the load device or the bulk capacitor at the
converter side. Connect GSNS to ground return at the general ground plane/layer. VSNS and GSNS can be
used for the purpose of remote sensing across the load device, however, ensure to minimize the routing trace
length to prevent excess noise injection into the sense lines.
In order to effectively remove heat from the package, prepare the thermal land and solder to the package thermal
pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate the heat.
Numerous vias (at least 6) with a 0.3-mm diameter connected from the thermal land to the internal/solder side
ground plane(s) should be used to help dissipation.

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REFERENCE DESIGNS
This section describes one typical application circuit using the TPS51362.

Design 1
This design is a VCCIO application with an output voltage of 1.05 V, maximum processor current (ICC(max)) of 6 A,
an OCL of 8 A and a switching frequency of 800 kHz.

V5
2.2 mF 5V

VSNS
10 nF VIN
GSNS 0.1 mF 7.4 V
23 22 21 20 19 18 17 16 15 2 x 10 mF to
20 V
GSNS VSNS SLEW TRIP GND V5 VIN VIN VIN
24 REFIN2 PGND 14

25 REFIN PGND 13

26 VREF TPS51362 PGND 12

0.1 mF
27 NU PGND 11

28 EN PGND 10
PGOOD LP# MODE NC BST SW SW SW SW 8 x 22 mF
1 2 3 4 5 6 7 8 9

EN 0.68 mH
0.1 mF VOUT
PGOOD 1.05 V
LP#
UDG-13058

Figure 23. Design 1: Application Schematic

Table 4. Design 1: List of Materials

REFERENCE
QTY SPECIFICATION MANUFACTURER PART NUMBER
DESIGNATOR
CIN 2 10 µF, 25 V Taiyo Yuden TMK325BJ106MM
COUT 8 22 µF, 6.3 V Murata GRM21BB30J226ME38
LOUT 1 0.68 µH, 4.8 mΩ Cyntec PIMB063T-R68MS-63

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REVISION HISTORY
NOTE: Page numbers of current version may differ from previous versions.

Changes from Original (February 2013) to Revision A Page

• Added MIN and MAX values to IOCLspec in the Elec Characteristics table .......................................................................... 5
• Changed the Functional Block Diagram VREFIN signal line identifier on the UV-detect device from "VREFIN – 32%" to
"VREFIN – 34%". Changed signal line identifier on the high-side comparator from "VREFIN+ 8/20%" to "VREFIN+ 20%".
Changed the high-side device symbol from hysteresis to a comparator. Changed signal line identifier on the low-
side device from "VREFIN– 8/32%" to "VREFIN– 8/34%. ........................................................................................................... 8
• Added Land pads for a 0.1-µF capacitor between VIN and PGND of the TPS51362 Design Layout figure. .................... 19
• Added a 0.1-µF capacitor symbol between VIN and PGND of the Design 1: Application Schematic. ............................... 20
• Changed LOUT inductor part number from PIMB063T to PIMB063T-R68MS-63 in Design 1: List of Materials table. ....... 20

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 PACKAGE OPTION ADDENDUM

www.ti.com 11-Aug-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

FX026 ACTIVE VQFN RVE 28 3000 Pb-Free (RoHS CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51362
Exempt)
TPS51362RVER ACTIVE VQFN RVE 28 3000 Pb-Free (RoHS CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51362
Exempt)
TPS51362RVET ACTIVE VQFN RVE 28 250 Pb-Free (RoHS CU NIPDAU Level-2-260C-1 YEAR -10 to 85 TPS51362
Exempt)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 11-Aug-2013

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51362RVER VQFN RVE 28 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
TPS51362RVET VQFN RVE 28 250 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-May-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51362RVER VQFN RVE 28 3000 367.0 367.0 35.0
TPS51362RVET VQFN RVE 28 250 210.0 185.0 35.0

Pack Materials-Page 2
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