DS

ISL6522
®
O M ME N
R EC 6535
T E RSIL CT - ISL
,IN U
NSSheet
Data RO D March 10, 2006 FN9030.8
D ESIG NCED P
N EW HA
F O R P- I N EN
DR O

Buck and Synchronous Rectifier Features

Pulse-Width Modulator (PWM) Controller • Drives two N-Channel MOSFETs
The ISL6522 provides complete control and protection for a
• Operates from +5V or +12V input
DC-DC converter optimized for high-performance micro-
processor applications. It is designed to drive two N-Channel • Simple single-loop control design
MOSFETs in a synchronous rectified buck topology. The - Voltage-mode PWM control
ISL6522 integrates all of the control, output adjustment, • Fast transient response
monitoring and protection functions into a single package.
- High-bandwidth error amplifier
The output voltage of the converter can be precisely - Full 0–100% duty ratio
regulated to as low as 0.8V, with a maximum tolerance of
• Excellent output voltage regulation
±1% over temperature and line voltage variations.
- 0.8V internal reference
The ISL6522 provides simple, single feedback loop, voltage- - ±1% over line voltage and temperature
mode control with fast transient response. It includes a
• Overcurrent fault monitor
200kHz free-running triangle-wave oscillator that is
- Does not require extra current sensing element
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and - Uses MOSFETs rDS(ON)
6V/µs slew rate which enables high converter bandwidth for • Converter can source and sink current
fast transient performance. The resulting PWM duty ratio • Small converter size
ranges from 0–100%. - Constant frequency operation
The ISL6522 protects against overcurrent conditions by - 200kHz free-running oscillator programmable from
inhibiting PWM operation. The ISL6522 monitors the current 50kHz to over 1MHz
by using the rDS(ON) of the upper MOSFET which eliminates • 14-lead SOIC and TSSOP package and 16-lead 5x5mm
the need for a current sensing resistor. QFN Package
• QFN Package
Pinouts SOIC, TSSOP
TOP VIEW - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
No Leads-Product Outline.
RT 1 14 VCC
- Near Chip-Scale Package Footprint; Improves PCB
OCSET 2 13 PVCC Efficiency and Thinner in Profile
SS 3 12 LGATE
• Pb-free plus anneal available (RoHS compliant)
COMP 4 11 PGND
FB 5 10 BOOT Applications
EN 6 9 UGATE
• Power supply for Pentium®, Pentium Pro, PowerPC® and
GND 7 8 PHASE
AlphaPC™ microprocessors
QFN • High-power 5V to 3.xV DC-DC regulators
TOP VIEW
• Low-voltage distributed power supplies
OCSET

VCC
NC

RT

16 15 14 13

SS 1 12 PVCC

COMP 2 11 LGATE
GND
FB 3 10 PGND

EN 4 9 BOOT

5 6 7 8
PHASE

UGATE
NC

GND

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, 2002, 2004-2006. All Rights Reserved
PowerPC® is a trademark of IBM. AlphaPC™ is a trademark of Digital Equipment Corporation. Pentium® is a registered trademark of Intel Corporation.
 ISL6522

Ordering Information Ordering Information (Continued)

PART PART TEMP. PKG. PART PART TEMP. PKG.
NUMBER MARKING RANGE (°C) PACKAGE DWG. # NUMBER MARKING RANGE (°C) PACKAGE DWG. #
ISL6522CB ISL6522CB 0 to 70 14 Ld SOIC M14.15 ISL6522CR ISL6522CR 0 to 70 16 Ld 5x5 QFN L16.5x5B
ISL6522CBZ 6522CBZ 0 to 70 14 Ld SOIC M14.15 ISL6522CRZ ISL6522CRZ 0 to 70 16 Ld 5x5 QFN L16.5x5B
(Note) (Pb-free) (Note) (Pb-free)
ISL6522CBZA 6522CBZ 0 to 70 14 Ld SOIC M14.15 ISL6522IR ISL6522IR -40 to 85 16 Ld 5x5 QFN L16.5x5B
(Note) (Pb-free) ISL6522IRZ ISL6522IRZ -40 to 85 16 Ld 5x5 QFN L16.5x5B
ISL6522IB ISL6522IB -40 to 85 14 Ld SOIC M14.15 (Note) (Pb-free)
ISL6522IBZ 6522IBZ -40 to 85 14 Ld SOIC M14.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free
(Note) (Pb-free) material sets; molding compounds/die attach materials and 100% matte
ISL6522CV ISL6522CV 0 to 70 14 Ld TSSOP M14.173 tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
ISL6522CVZ ISL6522CVZ 0 to 70 14 Ld TSSOP M14.173 products are MSL classified at Pb-free peak reflow temperatures that
(Note) (Pb-free) meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL6522IV ISL6522IV -40 to 85 14 Ld TSSOP M14.173 Add “-T” for tape and reel.
ISL6522IVZ ISL6522IVZ -40 to 85 14 Ld TSSOP M14.173
(Note) (Pb-free)

Typical Application
12V
+5V OR +12V
VCC

OCSET
SS MONITOR AND
EN
PROTECTION
BOOT

RT
OSC UGATE
PHASE
ISL6522 +VO
REF PVCC +12V

- LGATE
+ +
FB
- PGND

COMP GND

2 FN9030.8
March 10, 2006
 ISL6522

Block Diagram
VCC

POWER-ON
EN
RESET (POR)

10µA
+ SOFT-
OCSET SS
- OVER START
CURRENT BOOT

200µA 4V UGATE

PHASE
PWM
0.8VREF COMPARATOR
REFERENCE GATE
+ INHIBIT
+ CONTROL
- LOGIC
- PWM PVCC
ERROR
FB AMP LGATE

COMP PGND

RT OSCILLATOR GND

3 FN9030.8
March 10, 2006
 ISL6522

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W)
Boot Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . . . . +15.0V SOIC Package (Note 1) . . . . . . . . . . . . 67 n/a
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to VCC +0.3V TSSOP Package (Note 1) . . . . . . . . . . 95 n/a
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 QFN Package (Notes 2, 3). . . . . . . . . . 36 5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Recommended Operating Conditions Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range, ISL6522C . . . . . . . . . . . . 0°C to 70°C (SOIC - Lead Tips Only)
Ambient Temperature Range, ISL6522I. . . . . . . . . . . .-40°C to 85°C
Junction Temperature Range, ISL6522C. . . . . . . . . . . 0°C to 125°C
Junction Temperature Range, ISL6522I . . . . . . . . . .-40°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. θJA is measured with the component mounted on a highs effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. SeeTech
Brief TB379.
3. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply ICC EN = VCC; UGATE and LGATE Open - 5 - mA

Shutdown Supply EN = 0V - 50 100 µA

POWER-ON RESET

Rising VCC Threshold VOCSET = 4.5VDC - - 10.4 V

Falling VCC Threshold VOCSET = 4.5VDC 8.1 - - V

Enable-Input Threshold Voltage ISL6522C, VOCSET = 4.5VDC 0.8 - 2.0 V

ISL6522I, VOCSET = 4.5VDC 0.8 - 2.1 V

Rising VOCSET Threshold - 1.27 - V

OSCILLATOR

Free Running Frequency ISL6522C, RT = OPEN, VCC = 12 175 200 230 kHz

ISL6522I, RT = OPEN, VCC = 12 160 200 230

Total Variation 6kΩ < RT to GND < 200kΩ -20 - +20 %

Ramp Amplitude ∆VOSC RT = OPEN - 1.9 - VP-P

REFERENCE

Reference Voltage Tolerance VREF Commercial -1 - 1 %

Industrial -2 - +1 %

Reference Voltage - 0.800 - V

ERROR AMPLIFIER

DC Gain - 88 - dB

Gain-Bandwidth Product GBW - 15 - MHz

Slew Rate SR COMP = 10pF - 6 - V/µs

GATE DRIVERS

Upper Gate Source IUGATE VBOOT - VPHASE = 12V, VUGATE = 6V 350 500 - mA

4 FN9030.8
March 10, 2006
 ISL6522

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Upper Gate Sink RUGATE ISL6522C, ILGATE = 0.3A - 5.5 10 Ω

ISL6522I, ILGATE = 0.3A - 5.5 7.2 Ω

Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V 300 450 - mA

Lower Gate Sink RLGATE ISL6522C, ILGATE = 0.3A - 3.5 6.5 Ω

ISL6522I, ILGATE = 0.3A - 3.5 4.5 Ω

PROTECTION

OCSET Current Source IOCSET VOCSET = 4.5VDC 170 200 230 µA

Soft-Start Current ISS - 10 - µA

Typical Performance Curves

80

70
RT PULLUP
1000 TO +12V 60
RESISTANCE (kΩ)

CGATE = 3300pF
50

100 IVCC (mA) 40

RT PULLDOWN CGATE = 1000pF
30
TO VSS

10 20

10 CGATE = 10pF

0
10 100 1000 100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz)

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

Functional Pin Descriptions RT

SOIC This pin provides oscillator switching frequency adjustment.
RT 1 14 VCC
and By placing a resistor (RT) from this pin to GND, the nominal
OCSET 2 13 PVCC
TSSOP 200kHz switching frequency is increased according to the
SS 3 12 LGATE
following equation:
COMP 4 11 PGND
6
5 • 10
FB 5 10 BOOT Fs ≈ 200kHz + ------------------ (RT to GND)
RT
EN 6 9 UGATE
GND 7 8 PHASE Conversely, connecting a pull-up resistor (RT) from this pin
to VCC reduces the switching frequency according to the
OCSET

following equation:
VCC
NC

RT

QFN 7
4 • 10
16 15 14 13 Fs ≈ 200kHz – ------------------ (RT to 12V)
RT
SS 1 12 PVCC

COMP 2 11 LGATE
GND
FB 3 10 PGND

EN 4 9 BOOT

5 6 7 8
PHASE

UGATE
NC

GND

5 FN9030.8
March 10, 2006
 ISL6522

OCSET LGATE
Connect a resistor (ROCSET) from this pin to the drain of the Connect LGATE to the lower MOSFET gate. This pin provides
upper MOSFET. ROCSET, an internal 200µA current source the gate drive for the lower MOSFET. This pin is also
(IOCS), and the upper MOSFET on-resistance (rDS(ON)) set monitored by the adaptive shoot through protection circuitry to
the converter overcurrent (OC) trip point according to the determine when the lower MOSFET has turned off.
following equation:
PVCC
I OCS • R OCSET
I PEAK = -------------------------------------------
- Provide a bias supply for the lower gate drive to this pin.
r DS ( ON )
VCC
An overcurrent trip cycles the soft-start function.
Provide a 12V bias supply for the chip to this pin.
SS
Connect a capacitor from this pin to ground. This capacitor, Functional Description
along with an internal 10µA current source, sets the soft-start Initialization
interval of the converter.
The ISL6522 automatically initializes upon receipt of power.
COMP and FB Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
COMP and FB are the available external pins of the error
the input supply voltages and the enable (EN) pin. The POR
amplifier. The FB pin is the inverting input of the error
monitors the bias voltage at the VCC pin and the input
amplifier and the COMP pin is the error amplifier output.
voltage (VIN) on the OCSET pin. The level on OCSET is
These pins are used to compensate the voltage-control
feedback loop of the converter. equal to VIN Less a fixed voltage drop (see overcurrent
protection). With the EN pin held to VCC, the POR function
EN initiates soft-start operation after both input supply voltages
This pin is the open-collector enable pin. Pull this pin below exceed their POR thresholds. For operation with a single
1V to disable the converter. In shutdown, the soft-start pin is +12V power source, VIN and VCC are equivalent and the
discharged and the UGATE and LGATE pins are held low. +12V power source must exceed the rising VCC threshold
before POR initiates operation.
GND
The POR function inhibits operation with the chip disabled
Signal ground for the IC. All voltage levels are measured
(EN pin low). With both input supplies above their POR
with respect to this pin.
thresholds, transitioning the EN pin high initiates a soft-start
PHASE interval.
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
Soft-Start
for overcurrent protection. This pin also provides the return The POR function initiates the soft-start sequence. An internal
path for the upper gate drive. 10µA current source charges an external capacitor (CSS) on
the SS pin to 4V. Soft-start clamps the error amplifier output
UGATE (COMP pin) to the SS pin voltage. Figure 3 shows the soft-
Connect UGATE to the upper MOSFET gate. This pin start interval. At t1 in Figure 3, the SS and COMP voltages
provides the gate drive for the upper MOSFET. This pin is also reach the valley of the oscillator’s triangle wave. The
monitored by the adaptive shoot through protection circuitry to oscillator’s triangular waveform is compared to the ramping
determine when the upper MOSFET has turned off. error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
BOOT interval of increasing pulse width continues to t2, at which
This pin provides bias voltage to the upper MOSFET driver. point the output is in regulation and the clamp on the COMP
A bootstrap circuit may be used to create a BOOT voltage pin is released. This method provides a rapid and controlled
suitable to drive a standard N-Channel MOSFET. output voltage rise.
PGND
This is the power ground connection. Tie the lower MOSFET
source to this pin.

6 FN9030.8
March 10, 2006
 ISL6522

VOLTAGE is reference to VIN. When the voltage across the upper

MOSFET (also referenced to VIN) exceeds the voltage
VSOFT START across ROCSET, the overcurrent function initiates a soft-start
sequence. The soft-start function discharges CSS with a
10µA current sink and inhibits PWM operation. The soft-start
VOUT function recharges CSS, and PWM operation resumes with
the error amplifier clamped to the SS voltage. Should an
overload occur while recharging CSS, the soft-start function
VCOMP inhibits PWM operation while fully charging CSS to 4V to
VOSC(MIN) complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
CLAMP ON VCOMP RELEASED AT
to over 15A during the CSS charging interval and causes an
STEADY STATE
overcurrent trip. The converter dissipates very little power
TIME
with this method. The measured input power for the
t0 t1 t2
conditions of Figure 4 is 2.5W.
C SS
t 1 = ----------- ⋅ V OSC ( MIN ) The overcurrent function will trip at a peak inductor current
I SS
(IPEAK) determined by:
C SS V OUT SteadyState
t SoftStart = t 2 – t 1 = ----------- ⋅ ------------------------------------------------ ⋅ ∆V OSC I OCSET • R OCSET
I SS V IN I PEAK = --------------------------------------------------
-
r DS ( ON )
Where: CSS = Soft Start Capacitor
ISS = Soft Start Current = 10µA where IOCSET is the internal OCSET current source (200µA
VOSC(MIN) = Bottom of Oscillator = 1.35V is typical). The OC trip point varies mainly due to the
VIN = Input Voltage MOSFETs rDS(ON) variations. To avoid overcurrent tripping
∆VOSC = Peak to Peak Oscillator Voltage = 1.9V in the normal operating load range, find the ROCSET resistor
VOUTSteadyState = Steady State Output Voltage from the equation above with:

FIGURE 3. SOFT-START INTERVAL The maximum rDS(ON) at the highest junction temperature.

1. The minimum IOCSET from the specification table.

2. Determine I PEAK for I PEAK > I OUT ( MAX ) + ( ∆I ) ⁄ 2 ,
where ∆I is the output inductor ripple current.
SOFT-START

4V
For an equation for the ripple current see the section under
2V
component guidelines titled Output Inductor Selection.
0V
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
OUTPUT INDUCTOR

15A
presence of switching noise on the input voltage.
10A
Current Sinking
5A
The ISL6522 incorporates a MOSFET shoot-through
0A protection method which allows a converter to sink current
as well as source current. Care should be exercised when
TIME (20ms/DIV)
designing a converter with the ISL6522 when it is known that
the converter may sink current.
FIGURE 4. OVERCURRENT OPERATION
When the converter is sinking current, it is behaving as a boost
Overcurrent Protection converter that is regulating its input voltage. This means that
The overcurrent function protects the converter from a the converter is boosting current into the VIN rail, the voltage
shorted output by using the upper MOSFETs on-resistance, that is being down-converted. If there is nowhere for this current
rDS(ON) to monitor the current. This method enhances the to go, such as to other distributed loads on the VIN rail, through
converter’s efficiency and reduces cost by eliminating a a voltage limiting protection device, or other methods, the
current sensing resistor. capacitance on the VIN bus will absorb the current. This
situation will cause the voltage level of the VIN rail to increase. If
The overcurrent function cycles the soft-start function in a the voltage level of the rail is boosted to a level that exceeds the
hiccup mode to provide fault protection. A resistor (ROCSET) maximum voltage rating of the MOSFETs or the input
programs the overcurrent trip level. An internal 200µA capacitors, damage may occur to these parts. If the bias
(typical) current sink develops a voltage across ROCSET that voltage for the ISL6522 comes from the VIN rail, then the

7 FN9030.8
March 10, 2006
 ISL6522

maximum voltage rating of the ISL6522 may be exceeded and

+VIN
the IC will experience a catastrophic failure and the converter BOOT
D1
will no longer be operational. Ensuring that there is a path for CBOOT Q1 LO
the current to follow other than the capacitance on the rail will VOUT
ISL6522
PHASE
prevent these failure modes.

LOAD
SS
+12V CO
Application Guidelines Q2

VCC
Layout Considerations CVCC
CSS
As in any high frequency switching converter, layout is very
important. Switching current from one power device to GND
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
traces. These interconnecting impedances should be
LAYOUT GUIDELINES
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as Feedback Compensation
possible using ground plane construction or single point
Figure 7 highlights the voltage-mode control loop for a
grounding.
synchronous rectified buck converter. The output voltage
Figure 5 shows the critical power components of the (VOUT) is regulated to the reference voltage level. The error
converter. To minimize the voltage overshoot the amplifier (error amp) output (VE/A) is compared with the
interconnecting wires indicated by heavy lines should be part oscillator (OSC) triangular wave to provide a pulse-width
of ground or power plane in a printed circuit board. The modulated (PWM) wave with an amplitude of VIN at the
components shown in Figure 6 should be located as close PHASE node. The PWM wave is smoothed by the output filter
together as possible. Please note that the capacitors CIN (LO and CO).
and CO each represent numerous physical capacitors.
The modulator transfer function is the small-signal transfer
Locate the ISL6522 within three inches of the MOSFETs, Q1
function of VOUT/VE/A. This function is dominated by a DC
and Q2. The circuit traces for the MOSFETs’ gate and
gain and the output filter (LO and CO), with a double pole
source connections from the ISL6522 must be sized to
break frequency at FLC and a zero at FESR. The DC gain of
handle up to 1A peak current.
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC.
VIN
ISL6522
UGATE Q1 LO
VOUT
PHASE

CIN
LOAD

Q2 D2 CO
LGATE

PGND

RETURN

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, CSS
close to the SS pin because the internal current source is
only 10µA. Provide local VCC decoupling between VCC and
GND pins. Locate the capacitor, CBOOT as close as practical
to the BOOT and PHASE pins.

8 FN9030.8
March 10, 2006
 ISL6522

VIN 4. Place 1ST Pole at the ESR Zero

OSC DRIVER 5. Place 2ND Pole at Half the Switching Frequency
PWM
COMPARATOR LO 6. Check Gain against Error Amplifier’s Open-Loop Gain
VOUT
7. Estimate Phase Margin - Repeat if Necessary
- DRIVER PHASE
∆VOSC +
CO Figure 8 shows an asymptotic plot of the DC-DC converter’s
ESR gain vs. frequency. The actual modulator gain has a high gain
(PARASITIC)
peak due to the high Q factor of the output filter and is not
ZFB
shown in Figure 8. Using the above guidelines should give a
VE/A
ZIN
compensation gain similar to the curve plotted. The open loop
-
+ error amplifier gain bounds the compensation gain. Check the
REFERENCE
ERROR compensation gain at FP2 with the capabilities of the error
AMP
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 8 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
DETAILED COMPENSATION COMPONENTS
the modulator transfer function to the compensation transfer
ZFB function and plotting the gain.
VOUT
C2
ZIN

C1 R2 C3 R3 100
FZ1 FZ2 FP1 FP2
80
R1
COMP OPEN LOOP
60 ERROR AMP GAIN
FB
- GAIN (dB) 40
+ 20LOG
20 (R2/R1)
ISL6522 20LOG
REF (VIN/∆VOSC)
0
COMPENSATION
-20 MODULATOR GAIN
GAIN
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER CLOSED LOOP
-40
COMPENSATION DESIGN FLC
GAIN
FESR
-60
Modulator Break Frequency Equations 10 100 1K 10K 100K 1M 10M
FREQUENCY (Hz)
1 1
F LC = --------------------------------------- F ESR = --------------------------------------------- FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
2π • L O • C O 2π • ( ESR • C O )

The compensation network consists of the error amplifier The compensation gain uses external impedance networks
(internal to the ISL6522) and the impedance networks ZIN ZFB and ZIN to provide a stable, high bandwidth (BW) overall
and ZFB. The goal of the compensation network is to provide loop. A stable control loop has a gain crossing with
a closed loop transfer function with the highest 0dB crossing -20dB/decade slope and a phase margin greater than 45
frequency (f0dB) and adequate phase margin. Phase margin degrees. Include worst case component variations when
is the difference between the closed loop phase at f0dB and determining phase margin.
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
Component Selection Guidelines
R3, C1, C2, and C3) in Figure 8. Use these guidelines for Output Capacitor Selection
locating the poles and zeros of the compensation network: An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
Compensation Break Frequency Equations function of the switching frequency and the ripple current.
1 1 The load transient requirements are a function of the slew
F Z1 = ---------------------------------- F P1 = -------------------------------------------------------
2π • R 2 • C1 C1 • C2
2π • R2 •  ---------------------- rate (di/dt) and the magnitude of the transient load current.
 C1 + C2
These requirements are generally met with a mix of
1 1
F Z2 = ------------------------------------------------------ F P2 = ---------------------------------- capacitors and careful layout.
2π • ( R1 + R3 ) • C3 2π • R3 • C3
Modern microprocessors produce transient load rates above
1. Pick Gain (R2/R1) for desired converter bandwidth 1A/ns. High frequency capacitors initially supply the transient
2. Place 1ST Zero Below Filter’s Double Pole and slow the current load rate seen by the bulk capacitors.
(~75% FLC) The bulk filter capacitor values are generally determined by
3. Place 2ND Zero at Filter’s Double Pole

9 FN9030.8
March 10, 2006
 ISL6522

the ESR (effective series resistance) and voltage rating equations give the approximate response time interval for
requirements rather than actual capacitance requirements. application and removal of a transient load:

High frequency decoupling capacitors should be placed as L O × I TRAN L O × I TRAN

t RISE = -------------------------------
- t FALL = ------------------------------
-
close to the power pins of the load as physically possible. Be V IN – V OUT V OUT
careful not to add inductance in the circuit board wiring that
where: ITRAN is the transient load current step, tRISE is the
could cancel the usefulness of these low inductance
response time to the application of load, and tFALL is the
components. Consult with the manufacturer of the load on
response time to the removal of load. With a +5V input
specific decoupling requirements. For example, Intel
source, the worst case response time can be either at the
recommends that the high frequency decoupling for the
application or removal of load and dependent upon the
Pentium-Pro be composed of at least forty (40) 1.0µF
output voltage setting. Be sure to check both of these
ceramic capacitors in the 1206 surface-mount package.
equations at the minimum and maximum output levels for
Use only specialized low-ESR capacitors intended for the worst case response time.
switching-regulator applications for the bulk capacitors. The
Input Capacitor Selection
bulk capacitor’s ESR will determine the output ripple voltage
Use a mix of input bypass capacitors to control the voltage
and the initial voltage drop after a high slew-rate transient. An
overshoot across the MOSFETs. Use small ceramic
aluminum electrolytic capacitor’s ESR value is related to the
capacitors for high frequency decoupling and bulk capacitors
case size with lower ESR available in larger case sizes.
to supply the current needed each time Q1 turns on. Place the
However, the equivalent series inductance (ESL) of these
small ceramic capacitors physically close to the MOSFETs
capacitors increases with case size and can reduce the
and between the drain of Q1 and the source of Q2.
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with The important parameters for the bulk input capacitor are the
your capacitor supplier and measure the capacitor’s voltage rating and the RMS current rating. For reliable
impedance with frequency to select a suitable component. In operation, select the bulk capacitor with voltage and current
most cases, multiple electrolytic capacitors of small case size ratings above the maximum input voltage and largest RMS
perform better than a single large case capacitor. current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
Output Inductor Selection
input voltage and a voltage rating of 1.5 times is a
The output inductor is selected to meet the output voltage conservative guideline. The RMS current rating requirement
ripple requirements and minimize the converter’s response for the input capacitor of a buck regulator is approximately
time to the load transient. The inductor value determines the 1/2 the DC load current.
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are For a through-hole design, several electrolytic capacitors
approximated by the following equations: (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
V IN - V OUT V OUT solid tantalum capacitors can be used, but caution must be
∆I = -------------------------------- • ---------------- ∆VOUT= ∆I x ESR
Fs x L V IN exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
Increasing the value of inductance reduces the ripple current
the 593D series from Sprague are both surge current tested.
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient. MOSFET Selection/Considerations
One of the parameters limiting the converter’s response to a The ISL6522 requires two N-Channel power MOSFETs.
load transient is the time required to change the inductor These should be selected based upon rDS(ON), gate supply
current. Given a sufficiently fast control loop design, the requirements, and thermal management requirements.
ISL6522 will provide either 0% or 100% duty cycle in response In high-current applications, the MOSFET power dissipation,
to a load transient. The response time is the time required to package selection and heatsink are the dominant design
slew the inductor current from an initial current value to the factors. The power dissipation includes two loss
transient current level. During this interval the difference components; conduction loss and switching loss. The
between the inductor current and the transient current level conduction losses are the largest component of power
must be supplied by the output capacitor. Minimizing the dissipation for both the upper and the lower MOSFETs.
response time can minimize the output capacitance required. These losses are distributed between the two MOSFETs
The response time to a transient is different for the according to duty factor. The switching losses seen when
application of load and the removal of load. The following sourcing current will be different from the switching losses seen
when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower

10 FN9030.8
March 10, 2006
 ISL6522

switch realizes most of the switching losses when the converter DBOOT
+12V
is sinking current (see the equations below).
+ - +5V OR +12V
VD
Losses while Sourcing Current VCC
2 1
P UPPER = Io × r DS ( ON ) × D + --- ⋅ Io × V IN × t SW × F S BOOT
2 ISL6522 CBOOT
PLOWER = Io2 x rDS(ON) x (1 - D) Q1
UGATE NOTE:
VG-S ≈ VCC - VD
Losses while Sinking Current PHASE

PUPPER = Io2 x rDS(ON) x D

+5V
2 1 PVCC OR +12V
P LOWER = Io × r DS ( ON ) × ( 1 – D ) + --- ⋅ Io × V IN × t SW × F S
2
D2
Where: D is the duty cycle = VOUT / VIN , LGATE
Q2
- NOTE:
tSW is the switching interval, and +
PGND VG-S ≈ PVCC
FS is the switching frequency.
GND
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse- FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
recovery of the upper and lower MOSFET’s body diode. The
Figure 10 shows the upper gate drive supplied by a direct
gate-charge losses are dissipated by the ISL6522 and do not
connection to VCC . This option should only be used in
heat the MOSFETs. However, large gate-charge increases
converter systems where the main input voltage is +5VDC or
the switching interval, tSW which increases the upper
less. The peak upper gate-to-source voltage is approximately
MOSFET switching losses. Ensure that both MOSFETs are
VCC less the input supply. For +5V main power and +12VDC
within their maximum junction temperature at high ambient
for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level
temperature by calculating the temperature rise according to
MOSFET is a good choice for Q1 and a logic-level MOSFET
package thermal-resistance specifications. A separate
can be used for Q2 if its absolute gate-to-source voltage rating
heatsink may be necessary depending upon MOSFET
exceeds the maximum voltage applied to PVCC .
power, package type, ambient temperature and air flow.
+12V
Standard-gate MOSFETs are normally recommended for
+5V OR LESS
use with the ISL6522. However, logic-level gate MOSFETs
VCC
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to- BOOT
ISL6522
source voltage rating determine whether logic-level
Q1
MOSFETs are appropriate. UGATE
NOTE:
Figure 9 shows the upper gate drive (BOOT pin) supplied by
PHASE VG-S ≈ VCC - 5V

a bootstrap circuit from VCC . The boot capacitor, CBOOT +5V

OR +12V
develops a floating supply voltage referenced to the PHASE PVCC
pin. This supply is refreshed each cycle to a voltage of VCC Q2 D2
LGATE
less the boot diode drop (VD) when the lower MOSFET, Q2 -
+ NOTE:
turns on. A logic-level MOSFET can only be used for Q1 if PGND VG-S ≈ PVCC
the MOSFETs absolute gate-to-source voltage rating
exceeds the maximum voltage applied to VCC . For Q2, a GND

logic-level MOSFET can be used if its absolute gate-to-

FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION
source voltage rating exceeds the maximum voltage applied
to PVCC.
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency will drop one or two
percent as a result. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.

11 FN9030.8
March 10, 2006
 ISL6522

ISL6522 DC-DC Converter Application implemented using the ISL6522 controller without any
Circuit modifications. Detailed information on the circuit, including a
complete bill of materials and circuit board description, can
Figure 11 shows a DC-DC converter circuit for a
be found in Application Note AN9722. See Intersil’s home
microprocessor application, originally designed to employ
page on the web: http://www.intersil.com.
the HIP6006 controller. Given the similarities between the
HIP6006 and ISL6522 controllers, the circuit can be
12VCC

VIN
C17-18
C1-3 2x 1µF
3x 680µF 1206
RTN

C12
1µF C19
R7 1206
10K VCC 1000pF CR1
14 R6 4148
6 2 OCSET
ENABLE MONITOR AND
SS 3 PROTECTION 3.01K
10 BOOT PHASE
RT 1 TP2
Q1
9 UGATE C20
R1 OSC 0.1µF L1
C13 U1
0.1µF SPARE 8 PHASE
ISL6522
REF VOUT
13 PVCC

-- 12 LGATE Q2 CR2 C6-9

++ + MBR 4x 1000µF
FB 5 + 11 PGND
-- 340
RTN
4 7
R2 COMP GND JP1
1K C14

33pF
C15 R5
COMP
TP1
0.01µF 15K
C16

SPARE R4
R3
1K SPARE

Component Selection Notes:

C1-C3 - Three each 680µF 25W VDC, Sanyo MV-GX or equivalent.
C6-C9 - Four each 1000µF 6.3W VDC, Sanyo MV-GX or equivalent.
L1 - Core: micrometals T50-52B; winding: ten turns of 17AWG.
CR1 - 1N4148 or equivalent.
CR2 - 3A, 40V Schottky, Motorola MBR340 or equivalent.
Q1, Q2 - Fairchild MOSFET; RFP25N05
FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT

12 FN9030.8
March 10, 2006
 ISL6522

Small Outline Plastic Packages (SOIC)

N M14.15 (JEDEC MS-012-AB ISSUE C)
INDEX
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
AREA H 0.25(0.010) M B M PACKAGE
E
INCHES MILLIMETERS
-B-
SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
1 2 3
L
A1 0.0040 0.0098 0.10 0.25 -
SEATING PLANE B 0.013 0.020 0.33 0.51 9
-A- C 0.0075 0.0098 0.19 0.25 -
D A h x 45o
D 0.3367 0.3444 8.55 8.75 3
-C- E 0.1497 0.1574 3.80 4.00 4
α e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C A M B S
L 0.016 0.050 0.40 1.27 6
N 14 14 7
NOTES:
α 0o 8o 0o 8o -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

13 FN9030.8
March 10, 2006
 ISL6522

Thin Shrink Small Outline Plastic Packages (TSSOP)

N M14.173
INDEX 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
E 0.25(0.010) M B M
AREA PACKAGE
E1
GAUGE INCHES MILLIMETERS
-B- PLANE
SYMBOL MIN MAX MIN MAX NOTES

1 2 3 A - 0.047 - 1.20 -

L
A1 0.002 0.006 0.05 0.15 -
0.05(0.002) SEATING PLANE 0.25
A2 0.031 0.051 0.80 1.05 -
0.010
-A-
A
b 0.0075 0.0118 0.19 0.30 9
D
c 0.0035 0.0079 0.09 0.20 -
-C- D 0.195 0.199 4.95 5.05 3
α
A2 E1 0.169 0.177 4.30 4.50 4
e A1
c e 0.026 BSC 0.65 BSC -
b 0.10(0.004)
E 0.246 0.256 6.25 6.50 -
0.10(0.004) M C A M B S
L 0.0177 0.0295 0.45 0.75 6
N 14 14 7
NOTES:
α 0o 8o 0o 8o -
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E. Rev. 1 6/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

14 FN9030.8
March 10, 2006
 ISL6522

Quad Flat No-Lead Plastic Package (QFN) L16.5x5B

Micro Lead Frame Plastic Package (MLFP) 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL MIN NOMINAL MAX NOTES
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.28 0.33 0.40 5, 8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7, 8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.95 3.10 3.25 7, 8
e 0.80 BSC -
k 0.25 - - -
L 0.35 0.60 0.75 8
L1 - - 0.15 10
N 16 2
Nd 4 3
Ne 4 3
P - - 0.60 9
θ - - 12 9
Rev. 1 10/02

NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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15 FN9030.8
March 10, 2006