CDCM61002

www.ti.com SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011

Two Output, Integrated VCO, Low-Jitter Clock Generator

Check for Samples: CDCM61002

1FEATURES • Divider Programming Using Control Pins:

2• One Crystal/LVCMOS Reference Input – Two Pins for Prescaler/Feedback Divider
Including 24.8832 MHz, 25 MHz, and – Three Pins for Output Divider
26.5625 MHz – Two Pins for Output Select
• Input Frequency Range: 21.875 MHz to • Chip Enable Control Pin Available
28.47 MHz • 3.3-V Core and I/O Power Supply
• On-Chip VCO Operates in Frequency Range of • Industrial Temperature Range: –40°C to +85°C
1.75 GHz to 2.05 GHz
• 5-mm × 5-mm, 32-pin, QFN (RHB) Package
• 2x Output Available:
• ESD Protection Exceeds 2 kV (HBM)
– Pin-Selectable Between LVPECL, LVDS, or
2-LVCMOS; Operates at 3.3 V
APPLICATIONS
• LVCMOS Bypass Output Available
• Low Jitter Clock Driver for High-End Datacom
• Output Frequency Selectable by /1, /2, /3, /4, /6,
Applications Including SONET, Ethernet, Fibre
/8 from a Single Output Divider
Channel, Serial ATA, and HDTV
• Supports Common LVPECL/LVDS Output
• Cost-Effective High-Frequency Crystal
Frequencies:
Oscillator Replacement
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
155.52 MHz, 156.25 MHz, 159.375 MHz,
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz, DESCRIPTION
311.04 MHz, 312.5 MHz, 622.08 MHz, The CDCM61002 is a highly versatile, low-jitter
625 MHz frequency synthesizer that can generate two low-jitter
• Supports Common LVCMOS Output clock outputs, selectable between low-voltage
Frequencies: positive emitter coupled logic (LVPECL), low-voltage
differential signaling (LVDS), or low-voltage
– 62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,
complementary metal oxide semiconductor
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,
(LVCMOS) outputs, from a low-frequency crystal or
155.52 MHz, 156.25 MHz, 159.375 MHz,
LVCMOS input for a variety of wireline and data
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz
communication applications. The CDCM61002
• Output Frequency Range: 43.75 MHz to features an onboard PLL that can be easily
683.264 MHz (See Table 3) configured solely through control pins. The overall
• Internal PLL Loop Bandwidth: 400 kHz output random jitter performance is less than 1ps,
• High-Performance PLL Core: RMS (from 10 kHz to 20 MHz), making this device a
– Phase Noise typically at –146 dBc/Hz at perfect choice for use in demanding applications such
5-MHz Offset for 625-MHz LVPECL Output as SONET, Ethernet, Fibre Channel, and SAN. The
CDCM61002 is available in a small, 32-pin, 5-mm ×
– Random Jitter typically at 0.509 ps, RMS 5-mm QFN package.
(10 kHz to 20 MHz) for 625-MHz LVPECL
Output
• Output Duty Cycle Corrected to 50% (± 5%)
• Low Output Skew of 20 ps on LVPECL Outputs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION, CONTINUED
The CDCM61002 is a high-performance, low phase noise, fully-integrated voltage-controlled oscillator (VCO)
clock synthesizer with two universal output buffers that can be configured to be LVPECL, LVDS, or LVCMOS
compatible. Each universal output can also be converted to two LVCMOS outputs. Additionally, an LVCMOS
bypass output clock is available in an output configuration which can help with crystal loading in order to achieve
an exact desired input frequency. It has one fully-integrated, low-noise, LC-based VCO that operates in the 1.75
GHz to 2.05 GHz range.
The phase-locked loop (PLL) synchronizes the VCO with respect to the input, which can either be a
low-frequency crystal. The outputs share an output divider sourced from the VCO core. All device settings are
managed through a control pin structure, which has two pins that control the prescaler and feedback divider,
three pins that control the output divider, two pins that control the output type, and one pin that controls the
output enable. Any time the PLL settings (including the input frequency, prescaler divider, or feedback divider)
are altered, a reset must be issued through the Reset control pin (active low for device reset). The reset initiates
a PLL recalibration process to ensure PLL lock. When the device is in reset, the outputs and dividered are turned
off.
The output frequency (fOUT) is proportional to the frequency of the input clock (fIN). The feedback divider, output
divider, and VCO frequency set fOUT with respect to fIN. For a configuration setting for common wireline and
datacom applications, refer toTable 2. For other applications, use Equation 1 to calculate the exact crystal
oscillator frequency required for the desired output.
fIN =( Output Divider f
Feedback Divider OUT ( (1)
The output divider can be chosen from 1, 2, 3, 4, 6, or 8 through the use of control pins. Feedback divider and
prescaler divider combinations can be chosen from 25 and 3, 24 and 3, 20 and 4, or 15 and 5, respectively, also
through the use of control pins. Figure 1 shows a high-level block diagram of the CDCM61002.
The device operates in a 3.3-V supply environment and is characterized for operation from –40°C to +85°C.

RSTN PR[1...0] OD[2...0]

2 3

CDCM61002

PFD
Crystal/ Charge Pump
LVCMOS Loop Filter LVPECL/
Output
Driver LVCMOS/
VCO LVDS
Output Divider
Prescaler

Feedback LVPECL/
Divider Output
LVCMOS/
Driver
LVDS

3.3 V
LVCMOS

2
CE OS[1...0]

Figure 1. CDCM61002 Block Diagram

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 CDCM61002

www.ti.com SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011

AVAILABLE OPTIONS (1)

TA PACKAGED DEVICES FEATURES (2)
CDCM61002RHBT 32-pin QFN (RHB) package, small tape and reel
–40°C to +85°C
CDCM61002RHBR 32-pin QFN (RHB) package, tape and reel

(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
(2) These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material
contentcan be accessed at www.ti.com/leadfree. GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package
materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1%of total product weight. N/A: Not yet
available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean
RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered,
suitable for use in specified lead-free soldering processes.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range (unless otherwise noted).
PARAMETER VALUE UNIT
VCC_OUT,
VCC_PLL1,
VCC_PLL2, Supply voltage range (2) –0.5 to 4.6 V
VCC_VCO,
VCC_IN
VIN Input voltage range (3) –0.5 to (VCC_IN + 0.5) V
VOUT Output voltage range (3) –0.5 to (VCC_OUT + 0.5) V
IIN Input current 20 mA
IOUT Output current 50 mA
TSTG Storage temperature range –65 to +150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
condition is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All supply voltages must be supplied simultaneously.
(3) Input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted).
PARAMETER MIN NOM MAX UNIT
VCC_OUT Output supply voltage 3.0 3.30 3.60 V
VCC_PLL1 PLL supply voltage 3.0 3.30 3.60 V
VCC_PLL2 PLL supply voltage 3.0 3.30 3.60 V
VCC_VCO On-chip VCO supply voltage 3.0 3.30 3.60 V
VCC_IN Input supply voltage 3.0 3.30 3.60 V
TA Ambient temperature –40 +85 °C

DISSIPATION RATINGS (1) (2)

VALUE
TEST 4 × 4 VIAS
PARAMETER CONDITIONS ON PAD UNIT
θJA Thermal resistance, junction-to-ambient 0 LFM 35 °C/W
θJP (3) Thermal resistance, junction-to-pad 4 °C/W

(1) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
(2) Connected to GND with nine thermal vias (0.3-mm diameter).
(3) θJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN
package.

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ELECTRICAL CHARACTERISTICS
At VCC = 3 V to 3.6 V and TA = –40°C to +85°C, unless otherwise noted.
CDCM61002
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Control Pin LVCMOS Input Characteristics
VIH Input high voltage 0.6VCC V
VIL Input low voltage 0.4VCC V
IIH Input high current VCC = 3.6 V, VIL = 0 V 200 μA
IIL Input low current VCC = 3 V, VIH = 3.6 V –200 μA
LVCMOS Output Characteristics (1) (See Figure 9 and Figure 10)
fOSC_OUT Bypass output frequency 21.875 28.47 MHz
fOUT Output frequency 43.75 250 MHz
VOH Output high voltage VCC = min to max, IOH = –100 μA VCC –0.5 V
VOL Output low voltage VCC = min to max, IOL = 100 μA 0.3 V
tRJIT RMS phase jitter 250 MHz (10 kHz to 20 MHz) 0.85 ps, RMS
tSLEW-RATE Output rise/fall slew rate 20% to 80% 2.4 V/ns
ODC Output duty cycle 45% 55%
tSKEW Skew between outputs 50 ps
ICC, fIN = 25 MHz, fOUT = 250 MHz,
Device current, LVCMOS 120 140 mA
LVCMOS CL = 5 pF
LVPECL Output Characteristics (2) (See Figure 11 and Figure 12)
fOUT Output frequency 43.75 683.264 MHz
VOH Output high voltage VCC –1.18 VCC –0.73 V
VOL Output low voltage VCC –2 VCC –1.55 V
|VOD| Differential output voltage 0.6 1.23 V
tRJIT RMS phase jitter 625 MHz (10 kHz to 20 MHz) 0.77 ps, RMS
tR/tF Output rise/fall time 20% to 80% 175 ps
ODC Output duty cycle 45% 55%
tSKEW Skew between outputs 20 ps
ICC,
Device current, LVPECL fIN = 25 MHz, fOUT = 625 MHz 126 144 mA
LVPECL
LVDS Output Characteristics (3) (See Figure 13 and Figure 14)
fOUT Output frequency 43.75 683.264 MHz
|VOD| Differential output voltage 0.247 0.454 V
ΔVOD VDD magnitude change 50 mV
VOS Common-mode voltage 1.125 1.375 V
ΔVOS VOS magnitude change 50 mV
tRJIT RMS phase jitter 625 MHz (10 kHz to 20 MHz) 0.73 ps, RMS
tR/tF Output rise/fall time 20% to 80% 255 ps
ODC Output duty cycle 45% 55%
tSKEW Skew between outputs 30 ps
ICC, LVDS Device current, LVDS fIN = 25 MHz, fOUT = 625 MHz 110 125 mA

(1) Figure 9 and Figure 10 show dc and ac test setups, respectively. Jitter measurements made using 25-MHz quartz crystal in.
(2) Figure 11 and Figure 12 show dc and ac test setups, respectively. Jitter measurements made using 25-MHz quartz crystal in.
(3) Figure 13 and Figure 14 show dc and ac test setups, respectively. Jitter measurements made using 25-MHz quartz crystal in.

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TYPICAL OUTPUT PHASE NOISE CHARACTERISTICS

Over operating free-air temperature range (unless otherwise noted).
CDCM61002
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
250-MHz LVCMOS Output (1) (see Figure 10)
phn100 Phase noise at 100-Hz offset –95 dBc/Hz
phn1k Phase noise at 1-kHz offset –110 dBc/Hz
phn10k Phase noise at 10-kHz offset –117 dBc/Hz
phn100k Phase noise at 100-kHz offset –120 dBc/Hz
phn1M Phase noise at 1-MHz offset –135 dBc/Hz
phn10M Phase noise at 10-MHz offset –148 dBc/Hz
phn20M Phase noise at 20-MHz offset –148 dBc/Hz
tRJIT RMS phase jitter from 10 kHz to 20 MHz 544 fs, RMS
tPJIT Total period jitter 27.4 ps, PP
Start-up time, power supply ramp time of 1 ms,
tSTARTUP 2.25 ms
final frequency accuracy of ±10 ppm
625-MHz LVPECL Output (2) (see Figure 12)
phn100 Phase noise at 100-Hz offset –81 dBc/Hz
phn1k Phase noise at 1-kHz offset –101 dBc/Hz
phn10k Phase noise at 10-kHz offset –109 dBc/Hz
phn100k Phase noise at 100-kHz offset –112 dBc/Hz
phn1M Phase noise at 1-MHz offset –129 dBc/Hz
phn10M Phase noise at 10-MHz offset –146 dBc/Hz
phn20M Phase noise at 20-MHz offset –146 dBc/Hz
tRJIT RMS phase jitter from 10 kHz to 20 MHz 509 fs, RMS
tPJIT Total period jitter 26.9 ps, PP
Start-up time, power supply ramp time of 1 ms,
tSTARTUP 2.25 ms
final frequency accuracy of ±10 ppm
625-MHz LVDS Output (3) (see Figure 14)
phn100 Phase noise at 100-Hz offset –88 dBc/Hz
phn1k Phase noise at 1-kHz offset –102 dBc/Hz
phn10k Phase noise at 10-kHz offset –109 dBc/Hz
phn100k Phase noise at 100-kHz offset –112 dBc/Hz
phn1M Phase noise at 1-MHz offset –129 dBc/Hz
phn10M Phase noise at 10-MHz offset –146 dBc/Hz
phn20M Phase noise at 20-MHz offset –146 dBc/Hz
tRJIT RMS phase jitter from 10 kHz to 20 MHz 510 fs, RMS
tPJIT Total period jitter 27 ps, PP
Start-up time, power supply ramp time of 1 ms,
tSTARTUP 2.25 ms
final frequency accuracy of ±10 ppm

(1) Figure 10 shows test setup and uses 25-MHz quartz crystal in, VCC = 3.3 V, and TA = +25°C.
(2) Figure 12 shows test setup and uses 25-MHz quartz crystal in, VCC = 3.3 V, and TA = +25°C.
(3) Figure 14 shows test setup and uses 25-MHz quartz crystal, VCC = 3.3 V, and TA = +25°C.

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TYPICAL OUTPUT JITTER CHARACTERISTICS (1)

OUTPUT LVCMOS OUTPUT LVPECL OUTPUT LVDS OUTPUT
FREQUENCY
(MHz) INPUT (MHz) tRJIT tPJIT (psPP) tRJIT tPJIT (psPP) tRJIT tPJIT (psPP)
62.5 25 592 32.9 611 20.7 667 28.4
75 25 518 27.5 533 19.4 572 25.7
77.76 24.8832 506 29.2 526 20.9 567 26.9
100 25 507 24.5 510 20.7 533 26.5
106.25 26.5625 535 23.5 524 20.2 553 26.5
125 25 557 39.6 556 21.4 570 27.1
150 25 518 38.4 493 18.9 515 26.2
155.52 24.8832 498 36.9 486 19.8 502 26.7
156.25 25 510 37.7 503 20.7 518 26.5
159.375 26.5625 535 37.4 510 19.9 534 26.3
187.5 25 506 32.8 506 20.3 509 25.5
200 25 491 23.3 492 30 499 34.9
212.5 26.5625 520 47.8 509 30.8 530 37.3
250 25 544 27.4 541 21.4 550 27.5
311.04 24.8832 481 20.5 496 24.7
312.5 25 501 20.8 508 25.8
622.08 24.8832 492 27.2 500 27.2
625 25 515 26.9 509 27

(1) Figure 10, Figure 12, and Figure 14 show LVCMOS, LVPECL, and LVDS test setups (respectively) using appropriate quartz crystal in,
VCC = 3.3 V, and TA = +25°C.

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CRYSTAL CHARACTERISTICS
PARAMETER MINIMUM TYPICAL MAXIMUM UNIT
Mode of oscillation Fundamental MHz
Frequency 21.875 28.47 MHz
Equivalent series resistance (ESR) 50 Ω
On-chip load capacitance 8 10 pF
Drive level 0.1 1 mW
Maximum shunt capacitance 7 pF

DEVICE INFORMATION
RHB PACKAGE
QFN-32
(TOP VIEW)

PR1

PR0
NC

NC

NC

NC

NC

NC
32 31 30 29 28 27 26 25

VCC_OUT 1 24 NC

OUTN1 2 23 OSC_OUT

OUTP1 3 22 GND1
CDCM61002
VCC_OUT 4 21 XIN

OUTN0 5 Thermal Pad 20 VCC_IN

(must be soldered to ground)
OUTP0 6 19 REG_CAP1

CE 7 18 VCC_PLL1

NC 8 17 REG_CAP2

9 10 11 12 13 14 15 16
OS1

OD1
VCC_VCO

OD2

VCC_PLL2
OS0

OD0
RSTN

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CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

PIN FUNCTIONS
PIN
NAME PAD NO. TYPE DIRECTION (1) DESCRIPTION
VCC_OUT 1, 4 Power 3.3-V supply for the output buffer
VCC_PLL1 18 Power 3.3-V supply for the PLL circuitry
VCC_PLL2 16 Power 3.3-V supply for the PLL circuitry
VCC_VCO 9 Power 3.3-V supply for the internal VCO
VCC_IN 20 Power 3.3-V supply for the input buffers
GND1 22 Ground Additional ground for device. (GND1 shorted on-chip to GND)
Ground is on thermal pad. See Thermal
GND Pad Ground
Management .
XIN 21 Input Parallel resonant crystal/LVCMOS input
OUTP0,
6, 5 Output Differential output pair or two single-ended outputs
OUTN0
OUTP1,
3, 2 Output Differential output pair or two single-ended outputs
OUTN1
OSC_OUT 23 Output Bypass LVCMOS output
Capacitor for internal regulator (connect to a 10-μF Y5V capacitor to
REG_CAP1 19 Output
GND)
Capacitor for internal regulator (connect to a 10-μF Y5V capacitor to
REG_CAP2 17 Output
GND)
PR1, PR0 26, 25 Input Pull-up Prescaler and Feedback divider control pins (see Table 4)
OD2, OD1,
15, 14, 13 Input Pull-up Output divider control pins (see Table 5)
OD0
OS1, OS0 10, 11 Input Pull-up Output type select control pin (see Table 6)
CE 7 Input Pull-up Chip enable control pin (see Table 7)
RSTN 12 Input Pull-up Device reset (active low) (see Table 8)
8, 24, 27, 28,
NC 29, 30, 31, No connection
32

(1) Pull-up refes to internal input resistors; see Pin Characteristics for typical values.

Table 1. PIN CHARACTERISTICS

SYMBOL PARAMETER MIN TYP MAX UNIT
CIN Input capacitance 8 10 pF
RPULLUP Input pull-up resistor 150 kΩ

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PACKAGE

Figure 2. RHB Package

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CDCM61002

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FUNCTIONAL BLOCK DIAGRAM

VCC_IN VCC_PLL1 VCC_PLL2 VCC_VCO VCC_VDD VCC_OUT

XO Loop Filter
XIN Phase
LVCMOS Frequency Charge
Detector Pump
21.875 MHz 224 mA
to 28.47 MHz
400 kHz

¸15
¸5

VCO
FB_MUX

¸20
¸4 1.75 GHz
to 2.05 GHz
¸24 RSTN
¸3

¸25 Prescaler
Divider
Feedback
Divider LVCMOS

¸1

PR1 DIV_MUX
¸2 OUTP[1...0]
PR0 LVPECL

¸3
2
¸4 LVDS
OUTN[1...0]
¸6

REG_CAP1
¸8 LVCMOS

Output
Divider
REG_CAP2

LVCMOS OSC_OUT

CDCM61002

CE GND1 OD2 OD1 OD0 OS1 OS0

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DEVICE CONFIGURATION

Table 2. Common Configuration

VCO OUTPUT
PRESCALER FEEDBACK FREQUENCY OUTPUT FREQUENCY
INPUT (MHz) DIVIDER DIVIDER (MHz) DIVIDER (MHz) APPLICATION
25 4 20 2000 8 62.5 GigE
24.75 3 24 1782 8 74.25 HDTV
25 3 24 1800 8 75 SATA
24.8832 3 25 1866.24 8 77.76 SONET
25 3 24 1800 6 100 PCI Express
26.5625 3 24 1912.5 6 106.25 Fibre Channel
25 4 20 2000 4 125 GigE
25 3 24 1800 4 150 SATA
24.8832 3 25 1866.24 4 155.52 SONET
25 3 25 1875 4 156.25 10 GigE
26.5625 3 24 1912.5 4 159.375 10-G Fibre Channel
25 5 15 1875 2 187.5 12 GigE
25 3 24 1800 3 200 PCI Express
26.5625 3 24 1912.5 3 212.5 4-G Fibre Channel
25 4 20 2000 2 250 GigE
24.8832 3 25 1866.24 2 311.04 SONET
25 3 25 1875 2 312.5 XGMII
24.8832 3 25 1866.24 1 622.08 SONET
25 3 25 1875 1 625 10 GigE

Table 3. Generic Configuration

OUTPUT
INPUT FREQUENCY PRESCALER FEEDBACK VCO FREQUENCY FREQUENCY
RANGE (MHz) DIVIDER DIVIDER RANGE (MHz) OUTPUT DIVIDER RANGE (MHz)
21.875 to 25.62 4 20 1750 to 2050 8 54.6875 to 64.05
21.875 to 25.62 4 20 1750 to 2050 6 72.92 to 85.4
21.875 to 25.62 4 20 1750 to 2050 4 109.375 to 128.1
21.875 to 25.62 4 20 1750 to 2050 3 145.84 to 170.8
21.875 to 25.62 4 20 1750 to 2050 2 218.75 to 256.2
21.875 to 25.62 4 20 1750 to 2050 1 437.5 to 512.4
23.33 to 27.33 3 25 1750 to 2050 8 72.906 to 85.408
23.33 to 27.33 3 25 1750 to 2050 6 97.21 to 113.875
23.33 to 27.33 3 25 1750 to 2050 4 145.812 to 170.816
23.33 to 27.33 3 25 1750 to 2050 3 194.42 to 227.75
23.33 to 27.33 3 25 1750 to 2050 2 291.624 to 341.632
23.33 to 27.33 3 25 1750 to 2050 1 583.248 to 683.264
23.33 to 27.33 5 15 1750 to 2050 8 43.75 to 51.25
23.33 to 27.33 5 15 1750 to 2050 6 58.33 to 68.33
23.33 to 27.33 5 15 1750 to 2050 4 87.5 to 102.5
23.33 to 27.33 5 15 1750 to 2050 3 116.66 to 136.66
23.33 to 27.33 5 15 1750 to 2050 2 175 to 205
23.33 to 27.33 5 15 1750 to 2050 1 350 to 410
24.305 to 28.47 3 24 1750 to 2050 8 72.915 to 85.41
24.305 to 28.47 3 24 1750 to 2050 6 97.22 to 113.88
24.305 to 28.47 3 24 1750 to 2050 4 145.83 to 170.82

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Table 3. Generic Configuration (continued)

OUTPUT
INPUT FREQUENCY PRESCALER FEEDBACK VCO FREQUENCY FREQUENCY
RANGE (MHz) DIVIDER DIVIDER RANGE (MHz) OUTPUT DIVIDER RANGE (MHz)
24.305 to 28.47 3 24 1750 to 2050 3 194.44 to 227.76
24.305 to 28.47 3 24 1750 to 2050 2 291.66 to 341.64
24.305 to 28.47 3 24 1750 to 2050 1 583.32 to 683.28

Table 4. Programmable Prescaler and Feedback Divider Settings

CONTROL INPUTS PFD FREQUENCY
PRESCALER FEEDBACK
PR1 PR0 DIVIDER DIVIDER MINIMUM MAXIMUM
0 0 3 24 24.305 28.47
0 1 5 15 23.33 27.33
1 0 3 25 23.33 27.33
1 1 4 20 21.875 25.62

Table 5. Programmable Output Divider

CONTROL INPUTS
OD2 OD1 OD0 OUTPUT DIVIDER
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 Reserved
1 0 1 6
1 1 0 Reserved
1 1 1 8

Table 6. Programmable Output Type

CONTROL INPUTS
OS1 OS0 OUTPUT TYPE
0 0 LVCMOS, OSC_OUT Off
0 1 LVDS, OSC_OUT Off
1 0 LVPECL, OSC_OUT Off
1 1 LVPECL, OSC_OUT On

Table 7. Output Enable

CONTROL INPUT
OPERATING
CE CONDITION OUTPUT
0 Power Down Hi-Z
1 Normal Active

Table 8. Reset
CONTROL INPUT
OPERATING
RSTN CONDITION OUTPUT
0 Device Reset Hi-Z
0→1 PLL Recalibration Hi-Z
1 Normal Active

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TYPICAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted).
TYPICAL CURRENT CONSUMPTION FOR LVPECL OUTPUT
vs OUTPUT FREQUENCY
145
Output-divide-by-8
Output-divide-by-6
Output-divide-by-4
140 Output-divide-by-3
Output-divide-by-2
Output-divide-by-1
Supply CUrrent (mA)

135

130

125

120
0 200 400 600 800
Output Frequency (MHz)

Figure 3.

TYPICAL CURRENT CONSUMPTION FOR LVDS OUTPUT

vs OUTPUT FREQUENCY
130
Output-divide-by-8
Output-divide-by-6
Output-divide-by-4
125 Output-divide-by-3
Output-divide-by-2
Output-divide-by-1
Supply CUrrent (mA)

120

115

110

105
0 200 400 600 800
Output Frequency (MHz)

Figure 4.

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TYPICAL CHARACTERISTICS (continued)

Over operating free-air temperature range (unless otherwise noted).
TYPICAL CURRENT CONSUMPTION FOR LVCMOS OUTPUT
WITH 5-pF LOAD vs OUTPUT FREQUENCY
130

125

120
Supply Current (mA)

115

110

105

Output-divide-by-8
100
Output-divide-by-6
Output-divide-by-4
95
Output-divide-by-3
Output-divide-by-2
90
0 50 100 150 200 250 300
Output Frequency (MHz)

Figure 5.

TYPICAL LVPECL DIFFERENTIAL OUTPUT VOLTAGE

vs OUTPUT FREQUENCY
0.77

0.76
Differential Output Voltage, VOD (V)

0.75

0.74

0.73

0.72

0.71

0.70
0 100 200 300 400 500 600 700
Output Frequency (MHz)

Figure 6.

14 Copyright © 2009–2011, Texas Instruments Incorporated

 CDCM61002

www.ti.com SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011

TYPICAL CHARACTERISTICS (continued)

Over operating free-air temperature range (unless otherwise noted).
TYPICAL LVDS DIFFERENTIAL OUTPUT VOLTAGE
vs OUTPUT FREQUENCY
0.42

0.40
Differential Output Voltage, VDO (V)

0.38

0.36

0.34

0.32

0.30
0 100 200 300 400 500 600 700
Output Frequency (MHz)

Figure 7.

TYPICAL LVCMOS OUTPUT VOLTAGE WITH 5-pF LOAD

vs OUTPUT FREQUENCY
3.30

3.25
Output Voltage, VOUT (V)

3.20

3.15

3.10

3.05

3.00
50 100 150 200 250
Output Frequency (MHz)

Figure 8.

Copyright © 2009–2011, Texas Instruments Incorporated 15

CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

TEST CONFIGURATIONS

This section describes the function of each block for the CDCM61002. Figure 9 through Figure 15 illustrate how
the device should be set up for a variety of output configurations.

LVCMOS

5 pF

Figure 9. LVCMOS Output Loading During Device Test

Phase Noise
LVCMOS Analyzer

Figure 10. LVCMOS AC Configuration During Device Test

LVPECL Oscilloscope

50 W 50 W

VCC - 2V

Figure 11. LVPECL DC Configuration During Device Test

Phase Noise
Analyzer
LVPECL

150 W 150 W 50 W

Figure 12. LVPECL AC Configuration During Device Test

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 CDCM61002

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LVDS 100 W Oscilloscope

Figure 13. LVDS DC Configuration During Device Test

Phase Noise
Analyzer
LVDS

50 W

Figure 14. LVDS AC Configuration During Device Test

Yx VOH
VOD
Yx VOL

80%
20% VOUTpp
0V

tr tf

Figure 15. Output Voltage and Rise/Fall Times

Copyright © 2009–2011, Texas Instruments Incorporated 17

CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

FUNCTIONAL DESCRIPTION

Phase-Locked Loop (PLL)

The CDCM61002 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a crystal input
interface, which can also accept an LVCMOS signal, a phase frequency detector (PFD), a charge pump, an
on-chip loop filter, and prescaler and feedback dividers. Completing the CDCM61002 device are the output
divider and universal output buffer.
The PLL is powered by on-chip, low-dropout (LDO) linear voltage regulators. The regulated supply network is
partitioned such that the sensitive analog supplies are powered from separate LDOs rather than the digital
supplies which use a separate LDO regulator. These LDOs provide isolation for the PLL from any noise in the
external power-supply rail. The REG_CAP1 and REG_CAP2 pins should each be connected to ground by 10-μF
capacitors to ensure stability.

Configuring the PLL

The CDCM61002 permits PLL configurations to accommodate the various input and output frequencies listed in
Table 2 and Table 3. These configurations are accomplished by setting the prescaler divider, feedback divider
and output divider. The various dividers are managed by setting the device control pins as shown in Table 4 and
Table 5.

Crystal Input Interface

Fundamental mode is the recommended oscillation mode of operation for the input crystal and parallel
resonance is the recommended type of circuit for the crystal.
A crystal load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of
capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the
correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters.
The CDCM61002 implements an input crystal oscillator circuitry, known as the Colpitts oscillator, and requires
one pad of the crystal to interface with the XIN pin; the other pad of the crystal is tied to ground. In this crystal
interface, it is important to account for all sources of capacitance when calculating the correct value for the
discrete capacitor component, CL, for a design.
The CDCM61002 has been characterized with 10-pF parallel resonant crystals. The input crystal oscillator stage
in the CDCM61002 is designed to oscillate at the correct frequency for all parallel resonant crystals with low-pull
capability and rated with a load capacitance that is equal to the sum of the onchip load capacitance at the XIN
pin (10-pF), crystal stray capacitance, and board parasitic capacitance between the crystal and XIN pin.
The normalized frequency error of the crystal, as a result of load capacitance mismatch, can be calculated as
Equation 2:
Df = CS CS
-
f 2(CL,R + CO) 2(CL,A + CO) (2)
Where:
CS is the motional capacitance of the crystal,
C0 is the shunt capacitance of the crystal,
CL,R is the rated load capacitance for the crystal,
CL,A is the actual load capacitance in the implemented PCB for the crystal,
Δf is the frequency error of the crystal,
and f is the rated frequency of the crystal.
The first three parameters can be obtained from the crystal vendor.
In order to minimize the frequency error of the crystal to meet application requirements, the difference between
the rated load capacitance and the actual load capacitance should be minimized and a crystal with low-pull
capability (low CS) should be used.

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For example, if an application requires less than ±50 ppm frequency error and a crystal with less than ±50 ppm
frequency tolerance is picked, the characteristics are as follows: C0 = 7 pF, CS = 10 fF, and CL,R = 12 pF. In
order to meet the required frequency error, calculate CL,A using Equation 2 to be 17 pF. Subtracting CL,R from
CL,A, results in 5 pF; care must be taken during printed circuit board (PCB) layout with the crystal and the
CDCM61002 to ensure that the sum of the crystal stray capacitance and board parisitic capacitance is less than
the calculated 5 pF.
Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is critical to
locate the crystal components very close to the XIN pin to minimize routing distances. Long traces in the
oscillator circuit are a very common source of problems. Do not route other signals across the oscillator circuit.
Also, make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk and
noise coupling. Avoid the use of vias; if the routing becomes very complex, it is much better to use 0-Ω resistors
as bridges to go over other signals. Vias in the oscillator circuit should only be used for connections to the
ground plane. Do not share ground connections; instead, make a separate connection to ground for each
component that requires grounding. If possible, place multiple vias in parallel for each connection to the ground
plane. Especially in the Colpitts oscillator configuration, the oscillator is very sensitive to capacitance in parallel
with the crystal. Therefore, the layout must be designed to minimize stray capacitance across the crystal to less
than 5 pF total under all circumstances to ensure proper crystal oscillation. Be sure to take into account both
PCB and crystal stray capacitance.
Table 9 lists several recommended crystals and the respective manufacturer of each.

Table 9. Recommended Crystal Manufacturers

MANUFACTURER PART NUMBER
Vectron VXC1-1133
Fox 218-3
Saronix FP2650002

Phase Frequency Detector (PFD)

The PFD takes inputs from the input interface and the feedback divider and produces an output that depends on
the phase and frequency differences between the two inputs. The allowable range of frequencies at the PFD
inputs is 21.875 MHz to 28.47 MHz.

Charge Pump (CP)

The charge pump is controlled by the PFD, which dictates either to pump up or down in order to charge or
discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then
converted to a voltage that drives the control voltage node of the internal VCO through the on-chip loop filter. The
charge pump current is preset to 224 μA and cannot be changed.

On-Chip PLL Loop Filter

Figure 16 shows the on-chip active loop filter topology implemented in the device. This design corresponds to a
PLL bandwidth of 400 kHz for a PFD in the range of 21.875 MHz to 28.47 MHz, and a charge pump current of
224 μA.
473.5 pF 20 kW

Charge Pump
Output 15 kW
VCO Control

Figure 16. On-Chip PLL Loop Filter Topology

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CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

Prescaler Divider and Feedback Divider

The VCO output is routed to the prescaler divider and then to the feedback divider. The prescaler divider and
feedback divider are set in tandem with each other, according to the control pin settings given in Table 4. The
allowable combinations of the two dividers ensure that the VCO frequency and the PFD frequency are within the
specified limits.

On-Chip VCO
The CDCM61002 includes an on-chip, LC oscillator-based VCO with low phase noise covering a frequency
range of 1.75 GHz to 2.05 GHz. The VCO must be calibrated to ensure proper operation over the valid device
operating conditions. This calibration requires that the PLL be set up properly to lock the PLL loop and that the
reference clock input be present. During the first device initialization after power-up, which occurs after the
Power-On-Reset is released (2.64 V or lower, over valid device operating conditions) or a device reset with the
RSTN pin, a VCO calibration sequence is initiated after 16,384 × Reference Input Clock Cycles. The VCO
calibration then takes about 20 µs over the allowable range of the reference clock input.
The VCO calibration can also be reinitiated with a pulse on the RSTN pin at any time after POR is released on
power-up; the RSTN pulse must be at least 100 ns wide
For proper device operation, the reference input must be stable at the start of VCO calibration. Since inputs from
crystals or crystal oscillators can typically take up to 1-2ms to be stable, it is recommended to establish circuitry
on the RSTN pin that ensures device initialization including VCO calibration after a delay of greater than 5ms
compared to the power up ramp, as shown in Figure 17. A possible implementation of the delay circuitry on the
RSTN pin would be a 47nF capacitor to GND, and this in tandem with the 150kΩ on-chip pull-up resistor ensures
the appropriate delay. The CE pin has an internal 150kΩ pull-up resistor and can be left unconnected or pulled to
high for proper device operation.

tCE>0
3.3 V Vtrigger(POR)
tRST = 5 ms
RSTN
VIL, RST

CE VIH

Figure 17. Suggested Timing Recommendations

LVCMOS INPUT INTERFACE

Alternately, the CDCM61002 can be operated with an external ac-coupled 2.5-V LVCMOS or dc-coupled 3.3-V
LVCMOS reference input applied to the XIN pin. For proper operation, the LVCMOS reference should be
available and fairly stable by the time the power supply voltages or the RSTN pin voltage on the CDCM61002
reaches 2.27 V. See the application report SCAA111, available for download at ti.com, for more details about the
LVCMOS input interface to the CDCM61002.

Output Divider
The output from the prescaler divider is also routed to the output divider. The output divider can be set with
control pins according to Table 5.

Output Buffer
Each output buffer can be set to LVPECL or LVDS or 2x LVCMOS, according to Table 6. OSC_OUT is an
LVCMOS output that can be used to monitor proper loading of the input crystal in order to achieve the necessary
crystal frequency with the least error. The OSC_OUT turns on as soon as power is available and remains on
during deviec calibration. The output buffers are disabled during VCO calibration and are enabled only after
calibration is complete.
The output buffers on the CDCM61002 can also be disabled, along with other sections of the device, using the
CE pin according to Table 7.

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 CDCM61002

www.ti.com SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011

APPLICATION INFORMATION

Start-up Time Estimation

The CDCM61002 startup time can be estimated based on the parameters defined in Table 10 and graphically
shown in Figure 18.

Table 10. Start-up Time Dependencies

FORMULA/METHOD OF
PARAMETER DEFINITION DESCRIPTION DETERMINATION

The reciprocal of the applied reference 1

tREF Reference clock period tREF =
frequency in seconds. fREF
Power-supply rise time to low limit of Power Time required for power
tpul Power-up time (low limit)
On Reset (POR) trip point supply to ramp to 2.27 V
Power supply rise time to high limit of POR Time required for power
tpuh Power-up time (high limit)
trip point supply to ramp to 2.64 V
After POR releases, the Colpits oscillator is
enabled. This start-up time is required for the
500 μs best-case and 800 μs
trsu Reference start-up time oscillator to generate the requisite signal
worst-case
levels for the delay block to be clocked by
the reference input.
Internal delay time generated from the
tdelay Delay time reference clock. This delay provides time for tdelay= 16384 × tref
the reference oscillator to stabilize.
VCO Calibration Time generated from the
reference clock. This process selects the
tVCO_CAL VCO calibration time tVCO_CAL= 550 × tref
operating point for the VCO based on the
PLL settings.
Based on the 400-kHz loop
Time required for PLL to lock within ±10 ppm
tPLL_LOCK PLL lock time bandwidth, the PLL settles in
of fREF
5τ or 12.5 μs.

Reference
Power up Startup Delay VCO Calibration PLL Lock
Power Supply (V)

2.64 V

2.27 V

tpul
trsu tVCO_CAL
Time (s)
tpuh tPLL_LOCK
tdelay

Figure 18. Start-up Time Dependencies

Copyright © 2009–2011, Texas Instruments Incorporated 21

CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

The CDCM61002 start-up time limits, tMAX and tMIN, can be calculated as follows:
tMAX = tpuh + trsu + tdelay + tVCO_CAL + tPLL_LOCK
tMIN = tpul + trsu + tdelay + tVCO_CAL + tPLL_LOCK

Power Considerations
As a result of the different possible configurations of the CDCM61002, Table 11 is intended to provide enough
information on the estimated current consumption of the device. Unless otherwise noted, VCC = 3.3 V and TA =
+25°C.

Table 11. Estimated Block Power Consumption

EXTERNAL
RESISTOR
POWER
CURRENT CONSUMPTION IN-DEVICE POWER DISSIPATION DISSIPATION
BLOCK CONDITION (mA) (mW) (mW)
Entire device, Output off, no termination
65 214.5
core current resistors
LVPECL output, active mode 28 42.4 50
LVCMOS output pair, static 4.5 14.85
Output buffer LVCMOS output pair,
transient, 'CL' load, 'f' MHz V × fOUT × (CL + 20 × 10–12) × 103 V2 × fOUT × (CL + 20 × 10–12) × 103
output frequency
LVDS output, active mode 20 66
Divide enabled, divide = 1 5 16.5
Divide enabled, divide = 2 10 33
Divide circuitry
Divide enabled, divide = 3, 4 15 49.5
Divide enabled, divide = 6, 8 20 66

From Table 11, the current consumption can be calculated for any configuration. For example, the current for the
entire device with one LVPECL output in active mode can be calculated by adding up the following blocks: core
current, LVPECL output buffer current, and the divide circuitry current. The overall in-device power consumption
can also be calculated by summing the in-device power dissipated in each of these blocks.
As an example scenario, let us consider the use case of a crystal input frequency of 25 MHz and device output
frequency of 312.5 MHz in LVPECL mode. For this case, the typical overall power dissipation can be calculated
as:
3.3 V × (65 + 2 × 28 + 10) mA = 432.3 mW
Because the LVPECL output has external resistors and the power dissipated by these resistors is 50 mW, the
typical overall in-device power dissipation is:
432.3 mW – 2 × 50 mW = 332.3 mW
When the LVPECL output is active, the average voltage is approximately 1.9 V on each output as calculated
from the LVPECL VOH and VOL specifications. Therefore, the power dissipated in each emitter resistor is
approximately (1.9 V)2/150Ω = 25 mW.
When the LVCMOS output is active and drives a load capacitance, CL, the overall LVCMOS output current
consumption is the sum of a static pre-driver current and a dynamic switching current (which is a function of the
output frequency and the load capacitance).
Let us consider another use case of a crystal input frequency of 26.5625 MHz and device output frequency of
212.5 MHz in LVCMOS mode and driving a 5-pF load capacitance. For this case, the typical overall power
dissipation can be calculated as:
3.3 V × (65 + 15 + 2 × 21.4) mA = 405.24 mW

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Thermal Management
Power consumption of the CDCM61002 can be high enough to require attention to thermal management. For
reliability and performance reasons, the die temperature should be limited to a maximum of +125°C. That is, as
an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed +125°C.
The device package has an exposed pad that provides the primary heat removal path as well as an electrical
grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal land
pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the
package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
Check the mechanical data at the end of the data sheet for land and via pattern examples.

Power-Supply Filtering
PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically
increase the jitter of the PLL. This characteristic is especially true for analog-based PLLs. Thus, it is essential to
reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. A
PLL would have attenuated jitter as a result of power-supply noise at frequencies beyond the PLL bandwidth
because of attenuation by the loop response.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use these bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1-μF) bypass capacitors as there are supply
pins in the package.
The CDCM61002 power-supply requirements can be grouped into two sets: the analog supply line and the
output/input supply line. The analog supply line consists of the following power-supply pins on the CDCM61002:
VCC_PLL1, VCC_PLL2, and VCC_VCO. These pins can be shorted together. The output/input supply line
consists of the VCC_OUT and the VCC_IN power-supply pins on the CDCM61002. These pins can be shorted
together. Inserting a ferrite bead between the analog supply line and the output/input supply line isolates the
high-frequency switching noises generated by the device input and outputs, preventing them from leaking into
the sensitive analog supply line. Choosing an appropriate ferrite bead with very low dc resistance is important
because it is imperative to provide adequate isolation between the sensitive analog supply line and the other
board supply lines, and to maintain a voltage at the analog power-supply pins of the CDCM61002 that is greater
than the minimum voltage required for proper operation.

Copyright © 2009–2011, Texas Instruments Incorporated 23

CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

Figure 19 shows a general recommendation for decoupling the power supply.

Board/
Analog
Output/Input Ferrite Bead Supply
Supply

C C C C
10 mF 0.1 mF (x3) 10 mF 0.1 mF (x3)

Figure 19. Recommended Power-Supply Decoupling

Output Termination
The CDCM61002 is a 3.3-V clock driver with the following output options: LVPECL, LVDS, or LVCMOS.

LVPECL Termination
The CDCM61002 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required
to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL is
50 Ω to (VCC–2) V, but this dc voltage is not readily available on most PCBs. Thus, a Thevenin equivalent circuit
is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled cases, as shown in
Figure 20 and Figure 21. It is recommended to place all resistive components close to either the driver end or the
receiver end. If the supply voltage of the driver and receiver are different, ac-coupling is required.

130 W 130 W

VCC_OUT VCC_OUT

CDCM61002 LVPECL

82 W 82 W

Figure 20. LVPECL Output DC Termination

VBB
CDCM61002 LVPECL

150 W 150 W 50 W 50 W

Figure 21. LVPECL Output AC Termination

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 CDCM61002

www.ti.com SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011

LVDS Termination
The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs, as shown
in Figure 22 and Figure 23. It is recommended to place all resistive components close to either the driver end or
the receiver end. If the supply voltage of the driver and the receiver are different, ac-coupling is required.

CDCM61002 100 W LVDS

Figure 22. LVDS Output DC Termination

CDCM61002 100 W LVDS

Figure 23. LVDS Output AC Termination

LVCMOS Termination
Series termination is a common technique used to maintain the signal integrity for LVCMOS drivers, if connected
to a receiver with a high-impedance input with a pull-up or a pulldown resistor. For series termination, a series
resistor (RS) is placed close to the driver, as shown in Figure 24. The sum of the driver impedance and RS
should be close to the transmission line impedance, which is usually 50 Ω. Because the LVCMOS driver in the
CDCM61002 has an impedance of 30 Ω, RS is recommended to be 22 Ω to maintain proper signal integrity.

RS = 22 W
CDCM61002 LVCMOS

Figure 24. LVCMOS Output Termination

Copyright © 2009–2011, Texas Instruments Incorporated 25

CDCM61002

SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011 www.ti.com

Interfacing Between LVPECL and HCSL

Because the LVPECL common-mode voltage is different from the HCSL common-mode voltage, ac-coupled
termination is used. The 150-Ω resistor ensures proper biasing of the CDCM61002 LVPECL output stage, while
the 471-Ω and 56-Ω resistor network biases the HCSL receiver input stage, as shown in Figure 25.

471 W 471 W

VCC_OUT VCC_OUT
0W

CDCM61002 HCSL
0W

150 W 150 W 56 W 56 W

Figure 25. LVPECL to HCSL Interface

26 Copyright © 2009–2011, Texas Instruments Incorporated

 CDCM61002

www.ti.com SCAS870F – FEBRUARY 2009 – REVISED JUNE 2011

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (July, 2009) to Revision C Page

• Deleted references to Single-Ended and LVCMOS input throughout document ................................................................. 1

• Deleted fIN, ΔV/ΔT, and DutyREF parameters from Electrical Characteristics ..................................................................... 4
• Added LVCMOS Input Interface section ............................................................................................................................. 20

Changes from Revision C (February 2010) to Revision D Page

• Added reference to LVCMOS reference in first Features bullet ........................................................................................... 1

• Added reference to LVCMOS input in first paragraph of Description ................................................................................... 1
• Updated Figure 1 .................................................................................................................................................................. 2
• Changed name of Control Pin LVCMOS Input Characteristics section in Electrical Characteristics table .......................... 4
• Added reference to LVCMOS input in XIN parameter of Pin Functions table ...................................................................... 8
• Changed description of Crystal Input Interface section ...................................................................................................... 18
• Changed description of LVCMOS Input Interface section .................................................................................................. 20

Changes from Revision D (July 2010) to Revision E Page

• Changed Note 1 of the Pin Functions table From: Pull-up and Pull-down refer to...To:Pull-up refers to ............................. 8
• Deleted RPULLDOWN from Table 1 ........................................................................................................................................... 8
• Changed values in row 24.75 of Table 2 ............................................................................................................................ 11
• Changed the text of Configuring the PLL, deleted the last sentence ................................................................................. 18
• Changed the On-Chip VCO section .................................................................................................................................... 20
• Changed the Output Buffer section .................................................................................................................................... 20
• Changed the power dissipation equation From: 3.3 V × (65 + 2 × 28 + 10) mA = 429 mW To: 3.3 V × (65 + 2 × 28 +
10) mA = 432.3 mW ............................................................................................................................................................ 22
• Changed the power dissipation equation From: 439 mW – 2 × 50 mW = 339 mW To: 432.3 mW – 2 × 50 mW =
332.3 mW ............................................................................................................................................................................ 22
• Deleted figure "Recommended PCB Layout for CDCM61001" from the Thermal Management section. Added text
"See the mechanical data at the end of the data sheet.." .................................................................................................. 23

Changes from Revision E (March 2011) to Revision F Page

• Changed the On-Chip VCO section .................................................................................................................................... 20

• Changed Figure 17 ............................................................................................................................................................. 20
• Moved the LVCMOS INPUT INTERFACE section prior to the Output Divider section ...................................................... 20

Copyright © 2009–2011, Texas Instruments Incorporated 27

 PACKAGE OPTION ADDENDUM

www.ti.com 23-Apr-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CDCM61002RHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 CDCM
61002
CDCM61002RHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 CDCM
61002

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-Apr-2022

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCM61002RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
CDCM61002RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCM61002RHBR VQFN RHB 32 3000 356.0 356.0 35.0
CDCM61002RHBT VQFN RHB 32 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224745/A

www.ti.com
 PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.1 B
A
4.9

PIN 1 INDEX AREA

5.1 (0.1)
4.9

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS
20.000

C
1 MAX

SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17 SEE SIDE WALL
DETAIL

2X SYMM
33
3.5

0.3
32X
0.2
24 0.1 C A B
1
0.05 C

32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM
32 25
32X (0.6)

1 24

32X (0.25)

(1.475)
28X (0.5)

33 SYMM

(4.8)
( 0.2) TYP
VIA

8 17

(R0.05)
TYP

9 16
(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4223442/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)

1 24

32X (0.25)

28X (0.5)
(0.845)
SYMM
33

(4.8)

8 17

METAL
TYP

9 16
SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4223442/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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