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    436674ff88b4ec1e

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    Siddhesh Yevale

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    436674ff88b4ec1e

    Uploaded by

    Siddhesh Yevale
    4 views19 pages

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    © © All Rights Reserved

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    4 views19 pages

    436674ff88b4ec1e

    Uploaded by

    Siddhesh Yevale

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 19

     CAPTURE/COMPARE/PWM MODULES

     Each Capture/Compare/PWM (CCP) module


    contains
    a 16-bit register which can operate as a:
     • 16-bit Capture register

     • 16-bit Compare register

     • PWM Master/Slave Duty Cycle register

     Both the CCP1 and CCP2 modules are identical


    in operation, with the exception being the
    operation of the special event trigger.
     CCP1 Module:

     Capture/Compare/PWM Register1 (CCPR1) is


    comprised of two 8-bit registers: CCPR1L (low
    byte) and CCPR1H (high byte). The CCP1CON
    register controls the operation of CCP1.

     The special event trigger is generated by a


    compare match and will reset Timer1
     CCP2 Module:

     Capture/Compare/PWM Register2 (CCPR2) is


    comprised of two 8-bit registers: CCPR2L (low
    byte) and CCPR2H (high byte). The CCP2CON
    register controls the operation of CCP2.

     The special event trigger is generated by a


    compare match and will reset Timer1 and start
    an A/D conversion (if the A/D module is
    enabled).
    Capture Mode
    In Capture mode, CCPR1H:CCPR1L captures the
    16-bit value of the TMR1 register when an event
    occurs on pin RC2/CCP1. An event is defined as one of
    the following:
    • Every falling edge
    • Every rising edge
    • Every 4th rising edge
    • Every 16th rising edge
    The type of event is configured by control bits
    CCP1M3:CCP1M0 (CCPxCON<3:0>). When a capture
    is made, the interrupt request flag bit CCP1IF
    (PIR1<2>) is set. The interrupt flag must be cleared in
    software. If another capture occurs before the value in
    register CCPR1 is read, the old captured value is
    overwritten by the new value. In Capture mode, the
    RC2/CCP1 pin should be configured as an input by
    setting the TRISC<2> bit.
    Compare Mode
    In Compare mode, the 16-bit CCPR1 register value
    is constantly compared against the TMR1
    register pair value. When a match occurs, the
    RC2/CCP1 pin is:
    • Driven high
    • Driven low
    • Remains unchange

    The action on the pin is based on the value of


    control bits CCP1M3:CCP1M0 (CCP1CON<3:0>).
    At the same time, interrupt flag bit CCP1IF is
    set.
    TIMER1 MODE SELECTION
     Timer1 must be running in Timer mode, or
    Synchronized Counter mode, if the CCP module
    is using the compare feature. In Asynchronous
    Counter mode, the compare operation may not
    work.

    CCP PIN CONFIGURATION


    The user must configure the RC2/CCP1 pin as an
    output by clearing the TRISC<2> bit.
    SPECIAL EVENT TRIGGER
    In this mode, an internal hardware trigger is
    generated, which may be used to initiate an
    action.
    The special event trigger output of CCP1 resets the
    TMR1 register pair. This allows the CCPR1
    register to effectively be a 16-bit programmable
    period register for Timer1.

    The special event trigger output of CCP2 resets the


    TMR1 register pair and starts an A/D conversion (if
    the A/D module is enabled).
    PWM Mode (PWM)
    In Pulse Width Modulation mode, the CCPx pin
    produces up to a 10-bit resolution PWM output.
    Since the CCP1 pin is multiplexed with the
    PORTC data latch, TRISC<2> bit must be
    cleared to make the CCP1 pin an output.
    A PWM output has a time-base (period) and a time
    that the output stays high (duty cycle). The
    frequency of the PWM is the inverse of the period
    (1/period).
    PWM Period
    The PWM period is specified by writing to the PR2
    register.
    The PWM period can be calculated using the following
    formula:
    PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale
    value), specified in units of time
    PWM frequency (FPWM) is defined as 1 / [PWM period].
    When TMR2 is equal to PR2, the following three events
    occur on the next increment cycle:
    • TMR2 is cleared
    • The CCPx pin is set (exception: if PWM duty cycle =
    0%, the CCPx pin will not be set)
    • The PWM duty cycle is latched from CCPRxL into
    CCPRxH
    PWM Duty Cycle
    The PWM duty cycle is specified by writing to the
    CCPRxL register and to the (CCPxCON<5:4>)
    bits. Up to 10-bit resolution is available: the
    CCPRxL contains the eight MSbs and
    CCPxCON<5:4> contains the two LSbs

    The following equation is used to calculate the


    PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •TOSC •
    (TMR2 prescale value)
     The maximum PWM resolution (bits) for a given
    PWM frequency is given by the formula
     In order to achieve higher resolution, the PWM
    frequency must be decreased. In order to achieve
    higher PWM frequency, the resolution must be
    decreased.

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