Integrated circuits

LABORATORY MANUAL (ECE - 328)

3
III/IV ECE SEM - II

Ms.D.Nagamani Dr. V. Rajya Lakshmi

Professor & HOD, ECE
Dr.K.V.G.Srinivas

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY & SCIENCES (A)

(Affiliated to AU, Approved by AICTE & Accredited by NBA)
Sangivalasa-531
531 162, Visakhapatnam District, Phone: 08933-225083/84/87
225083/84/87
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, Bheemunipatnam Mandal, Visakhapatnam District

Vision of the Institute

ANITS envisions to emerge as a world-class technical institution whose products represent a good blend of
technological excellence and the best of human values.

Mission of the Institute

To train young men and women into competent and confident engineers with excellent communication skills, to
face the challenges of future technology changes, by imparting holistic technical education using the best of
infrastructure, outstanding technical and teaching expertise and an exemplary work culture, besides molding
them into good citizens

Vision of the Department

To become a centre of excellence in Education, research and produce high quality Engineers in the field of
Electronics and Communication Engineering to face the challenges of future technological changes.

Mission of the Department

To achieve vision department will

Transform students into valuable resources for industry and society by imparting contemporary technical
education.

Develop interpersonal skills and leadership qualities among students by creating an ambience of academic
integrity to participate in various professional activities

Create a suitable academic environment to promote research attitude among students .

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, Bheemunipatnam Mandal, Visakhapatnam District

Program Educational Objectives (PEOs):

PEO1 : Graduates excel in their career in the domains of Electronics, Communication and Information
Technology.
PEO2 : Graduates will practice professional ethics and excel in professional career through interpersonal skills
and leadership qualities.
PEO3 : Graduates demonstrate passion for competence in higher education, research and participate in various
professional activities.
Program Outcomes (POs):
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an
engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems
reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health
and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and
IT tools including prediction and modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health,
safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal
and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams,
and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering community
and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and
life-long learning in the broadest context of technological change.

Program Specific Outcomes (PSOs):

PSO1 : Implement Signal & Image Processing techniques using modern tools.
PSO2 : Design and analyze Communication systems using emerging techniques.
PSO3 : Solve real time problems with expertise in Embedded Systems.
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, BheemunipatnamMandal, Visakhapatnam District

INTEGRATED CIRCUITS LABORATORY

ECE328 Credits:1.5
Instruction: 3 Practical’s &1 O/week Sessional Marks:50
End Exam: 3 Hours End Exam Marks:50
Pre -requisites: Digital Electronics, Integrated Circuits and Applications, VHDL/Verilog Language

Course objectives:
 To understand the non-linear applications of operational amplifiers (IC741).
 To familiarize with theory and applications of IC555 timers.
 To design and construct multivibrators using Op-Amp and 555 Timer.
 To design and verify various combinational circuits using HDL.
 To design and verify various sequential logic circuits using HDL.

COURSE OUTCOMES:
By the end of the course student will be able to:
CO1: Design the circuits using op-amps for various applications like Schmitt Trigger, Precision
Rectifier, Comparators and three terminal IC 78XX regulator.
CO2: Design active filters for the given specifications and obtain their frequency response
characteristics.
CO3: Design and analyze multivibrator circuits using Op-amp and 555Timer.
CO4: Design and Verify various combinational circuits like multiplexers, and de-multiplexers,
encoder, decoder, ALU, code converters etc using FPGA.
CO5: Design and Verify various sequential circuits like flip-flops, counters using FPGA.

Mapping of Course Outcomes with Program Outcomes & Program Specific Outcomes:
PO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
1
3 2 3 3 1 1 1 1 2
2 3 2 3 3 1 1 1 1 2
CO 3 3 3 3 3 1 1 1 1 2
4 3 2 3 3 2 1 1 1 1 2
5 3 2 3 3 2 1 1 1 1 2

3: high correlation, 2: medium correlation, 1: low correlation

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, BheemunipatnamMandal, Visakhapatnam District

LIST OF EXPERIMENTS
S.No Name of the Experiment
CYCLE-I: Analog Circuits
1. Frequency response of Op-amp in Inverting and Non-inverting modes.
2. Design an amplifier using Op-amp for the given specifications.
3. Measurement of Op-amp parameters.
4. Design and verification of Op-amp adder, subtractor, Integrator, Differentiator.
5. Design of Schmitt Trigger using op-amp.
6. Design and verification of Active LPF & HPF using op-amp.
7. Comparison of functionality of Astable multivibrator using a) Op-amp b) IC
555.
8. Verification of functionality of R-2R ladder DAC.
CYCLE-II: Experiments Using FPGA
9. Verify the functionality of parallel adder using FPGA.
10. Verify the functionality of 4x1 Multiplexer using FPGA.
11. Verify the functionality of 1x4 Demultiplexer using FPGA.
12. Verify the functionality of 4:2 encoder using FPGA.
13. Verify the functionality of 3:8 decoder using FPGA.
14. Design and verify the functionality of Binary to Gray Code converter.
15. Verify the functionality of 2-bit Comparator using FPGA.
16. Verify the functionality of ALU using FPGA.
17. Verify the functionality of Mod-4 Counter using FPGA.
18. Verify the functionality of Delay Flip flop using FPGA.

Note: A minimum of any five experiments have to be done from each cycle.
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, Bheemunipatnam Mandal, Visakhapatnam District

Scheme of Evaluation
(INTEGRATED CIRCUITS LABORATORY)

Total marks for each student to evaluate in lab: 100 marks

Total marks for each student to evaluate in lab: 100

Out of 100 marks:
1. External exam Evaluation : 50marks
2. Internal Evaluation : 50 marks
i. Internal exam : 25marks
ii. Continuous Evaluation : 25 marks

1. Internal Evaluation (50M)

i. Continuous Evaluation(25M)
I. Preparation of Observation – 5M(The appropriate aim, experimental design,
Circuit diagram , selection of components, & Model Graph)
II. Execution of Experiment/Result – 5M(The procedure of doing experiment,
Apparatus usage& accurate Output(Theoretical & Practical correlation ), valid
Result Statements)
III. Record – 5M (The record submitted in time and with neat & clear(Write-
up,Aim,Appratus,Procedure,Theory), Circuit diagram, Experimental design, Graphs
& valid Result Statements)
IV. Pre lab & Post lab questions – 5M(The number of questions answered before and
after doing the each lab experiment)
V. Attendance ---- 5M

ii. Internal End Exam – 25M

(Write up – 10M, Performance – 5M , Result/Graph – 5M, Viva – 5M)

2. External exam Evaluation: (50M)

I. Write up – 5M
II. Design /Circuit Diagram – 15M
III. Experiment/Output – 10M
IV. Result/Graph – 10M
V. Viva – 10M
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, BheemunipatnamMandal, Visakhapatnam District

RUBRICS
IC Laboratory
S.No Performance Indicator Excellent Good Average Poor
>80% to ≤100% >60% to ≤80% >40% to ≤60% performance
≤40%
1. An ability to identify, formulate and Able to apply the concepts of Shows nearly complete Unable to apply the concept Poor
solve Electronic Circuit problems electronic circuits to solve understanding of concepts of of electroniccircuits in knowledge on
with Linear/Digital Integrated given problem statement. electronics in problem solving. solving problems effectively. electronics
circuit knowledge and to design as Able to Develop a design Developed a design Strategy, Developed the design concept.
well as analyze and interpret data. Strategy, analyzed the circuit analyzed the circuit with some strategy with Guidance and Developed
(Based on Observation) (max:5M) as an individual or with a guidance. unable to analyze the circuit design
(PO1, PO2, PO3) team. Must be assisted in integrating properly. contains many
Able to relate theoretical Previous knowledge and More Guidance is need to errors.
concepts with practical relating theoretical concepts integrating previous Unable to
problem solving. to problem solving. knowledge. recollect the
theoretical
knowledge
with practical
problem
solving.

2. An ability to conduct experimentsto Able to conduct the Able to conduct the Able to conduct the Unable to use
perform certain operation as an experiment and validate the experiment and validate the experiment but not validated the
individual or with a team and results with the theoretical results partially with the the results with the components
represent data from the results so as value and drawn the theoretical value and drawn theoretical value and conduct
to facilitate analysis and conclusions. the conclusions. experiment.
explanations of the data, and write Able to use Ability to use
conclusions. components/modern tool components/modern tool is
An ability to simulate circuits using effectively to produce less and/or need guidance to
modern tool desired output. know the usage of
(Based on Execution & components.
Result)(max:5M)
(PO4, PO5, PO9)

3. Graduates to acquire the ability to Report is presented very Report is presented good and Report is presented with Report
communicate effectively when neatly and used very good used good professional poor organization of the contains many
employing written professional writing style writing style with the content. errors and
Communications by following the with the professional code of professional code of ethics. having
ethical principle of report writing. ethics. Use graphs, tables and inadequate
(5M) Use graphs, tables and diagrams to support points, information.
(Based on Record)(max:5M) diagrams to support points, interpret and assess
(PO8,PO10) interpret and assess information. Few desired
information. information is missing in the
report.
4. An ability to communicate effectively Able to listen carefully and Able to listen carefully and Able to listen carefully and Unable to
when employing oral able to describe the purpose able to describe the purpose less knowledge on purpose of listen carefully
communications. of the experiments and its of the experiments and its doing experiments and its and unable to
(Based on pre-lab and post-lab scope. scope. scope. describe the
viva) (5M). Able to deliver a well- Unable to deliver a well- purpose of
(PO10) organized oral presentation organized oral presentation doing
after doing an experiment after doing an experiment experiment
and relevant
theoretical
information
clearly.
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, Bheemunipatnam Mandal, Visakhapatnam District

ABOUT LAB:
Linear ICs are employed in many electronic equipment like Audio amplifiers, A/D (analog-to-digital)
converters, Integrators, Multivibrators, Oscillators, Audio filters etc. Keeping these factors into the
considerations basic and most commonly used linear IC 741 op-amp and IC 555 are introduced. Digital
Experiments like Parallel adder, Multiplexer, De-Multiplexer, Encoder, Decoder, Flip flops, Counters, Code
convertors, ALU are introduced and their functionality is verified using FPGA Kits. This laboratory is to cater
the needs of under graduate students to practically explore the fundamental concepts of electronics. It helps the
students to gaining knowledge about electronic system and IC design and pursuing projects in electronics. The
students are also encouraged to implement the designed circuits using discrete components on the breadboard.

LAB PHOTO:
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, Bheemunipatnam Mandal, Visakhapatnam District

LIST OF MAJOR EQUIPMENT IN (ANALOG / DIGITAL) COMMUNICATIONLABORATORY

S.NO NAME OF THE EQUIPMENT MAKE QUANTITY

1. 50 MHZ DIGITAL STORAGE TEKTRONICS 12
OSCILLOSCOPE
2. 0-30V REGULATED POWER SUPPLY ITL /FALCON/APLAB 14
3. 1MHZ FUNCTION GENERATOR APLAB 07
4. 20 MHZ DUAL TRACE OSCILLOSCOPE CADO 04
5. 3KVA ONLINE UPS MEGAPOWER 01
6. BLOCK CODE ENCODER&DECODER SCIENTECH 02
7. CONVOLUTION CODE SCIENTECH 02
ENCODER&DECODER
8. ACL-AMPLITUDE AKADEMIKA LAB SOLUTIONS 02
MODULATION&DEMODULATION
9. PL-DSP TRAINER KIT AKADEMIKA LAB SOLUTIONS 02
10. PERSONAL COMPUTER SYSTEM HCL 06
11. SPECTRUM ANALYZER AGILENT TECHNOLOGIES 01
PVT.LIMITED

TOTAL EXPENDITURE OF THE LABORATORY(including consumables) :Rs.27,79,409.37/-

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Anil Neerukonda Institute of Technology & Sciences (Autonomous)
Sangivalasa-531 162, BheemunipatnamMandal, Visakhapatnam District

Integrated Circuits Laboratory

Do’s
1. Be punctual and regular to the laboratory.

2. Maintain Discipline all the time and obey the instructions.

3. Read and understand how to carry out an experiment thoroughly before coming to the laboratory.

4. Check the connections properly before turning ON the circuit.

5. Turn OFF the circuit immediately if you see any component heating.

6. Dismount all the components and wires before returning the kit.

7. Report any broken plugs/apparatus or exposed electrical wires to the faculty

member/laboratory technician immediately.

8. Shut down the systems properly

Don’ts
1. Don’t touch live electric wires.

2. Don’t turn ON the circuit unless it is completed.

3. Avoid making loose connections.

4. Do not remove anything from the kits/experimental set up without permission.

5. Do not handle any equipment without reading the instructions/Instruction manuals

6. Don’t leave the lab without permission.

 Cycle: I
(Analog ICs)
 EXPERIMENT NO: 1
Frequency Response of Op-amp in Inverting & non-inverting modes
Objective:
To plot the frequency responses for both inverting and non-inverting modes of the given
OP – AMP and to obtain its bandwidth.

S.No Apparatus Range Quantity

01 Operational Amplifier LM 741IC 01
02 Resistance 10K (1) , 1KΩ (1)
03 Regulated Power supply (0-30V) 01
04 DC multi-meter
05 Signal Generator 1M Hz 01
06 CRO 20MHz 01
07 Breadboard and Wires ,CRO Probes

CIRCUIT DIAGRAM:

INVERTING MODE

Rf (10K)

7
R1 (1K) +15V
2_ Vo (CRO)
6

LM 741
Vs +
20mV 3
AFO
- 15V
4
 Input and output waveforms of inverting amplifier

NON – INVERTING MODE

Rf (10K)

7
R1 (1K) +15V
2
_ 6

LM 741
+
3 Vo (CRO)
Vs
20mV - 15V
AFO 4
 Input and output waveforms of non-inverting amplifier

PROCEDURE:
1. The circuit is connected as shown in circuit diagram (1) in inverting mode.
2. A 15v dual supply is given to the op amp from TRPS.
3. Now an input voltage of (Say 20mV to 30mV) is given from the signal generator.
4. By varying the frequency, the output voltage VO is noted from the CRO for different values of
frequencies up to 1MHz.
5. For each value, the gain is calculated by the formula,
V 
AV  20 log O dB
 VI 
6. Now the circuit diagram (2) is connected in non-inverting mode and the above procedure is
repeated.
7. It is observed that the gain (AV) of an op amp is greater in non-inverting mode compared to that in
inverting mode.
THEORETICAL CALCULATIONS:
For Inverting mode:

AV  
R f
AV  20 log 10  AV 
R1
For Non-Inverting mode:

AV   1 
 R f 
  

AV  20 log 10  AV 
 R
 1 
TABULAR FORM :
 INVERTING MODE : Vi =
FREQUENCY (Hz) O/P VOLTAGE GAIN AV = 20 log Vo / Vi
Vo (V) (dB)

100
200
300
500
700
1k
2k
3k
5k
7k
10k
20k
30k
50k
70k
100k
200k
300k
500k
700k
1M

NON INVERTING MODE : Vi =

FREQUENCY (Hz) O/P VOLTAGE GAIN AV = 20 log Vo / Vi
Vo (V) (dB)

100
200
300
500
700
1k
2k
3k
5k
7k
10k
20k
30k
50k
70k
100k
200k
300k
500k
700k
1M
MODEL GRAPH :

Non-inv mode
AVmax(Ninv)
}-3dB
Inv mode
AVmax(inv)
}-3dB

Gain in
dB

fh fh
Freq in Hz
Bandwidth ≈ fh
GRAPH:
A graph is plotted between voltage gain (dB) and frequency (Hz) both for inverting and non-
inverting amplifiers.
PREACAUTION:
1. Avoid loose and wrong connections.
2. The output signal should be free from distortions.
3. Avoid parallax error while taking readings from CRO.
RESULT:
The frequency responses characteristics of the given Op-amp in both inverting & non
inverting modes are Obtained.

VIVA:
1. Why response of Op-amp starts from constant.
2. What are the difference between inverter & non-inverter Amplifier?
3. What are the types of packages for op-amp?
4. What is inverting and non-inverting amplifier?
5. What is the non-inverter closed-loop op-amp gain factor?
 EXPERIMENT NO:2

MEASUREMENT PARAMETERS OF OP – AMP

Objective:

Measurement of Op – Amp Parameters: To determine the CMRR and slew rate of operational
amplifier.

APPARATUS:

S.No Apparatus Type Range Quantity

01 Operational Amplifier LM 741IC 01
02 Resistance 100Ω (2),100KΩ (2),
10K (1) , 1KΩ (4) 15KΩ(1)
03 Regulated Power supply (0-30V) 01
04 DC multi meter 0-20v
05 Signal Generator 1M Hz 01
06 CRO 01
07 Breadboard and Wires ,CRO Probes

THE IDEAL OP AMP:

An ideal op amp would exhibit the following electrical characteristics.
1. Infinite voltage gain A.
2. Infinite input resistance Ri so that almost any signal source can drive it and there is no loading of
the preceding stage.
3. Zero output resistance R0 so that output can drive an infinite number of other devices.
4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth so that any frequency signal from 0 to ∞ Hz can be amplified without
attenuation.
6. Infinite common mode rejection ratio so that output common – mode noise voltage is zero.
7. Infinite slew rate so that output voltage changes occur simultaneously with input voltage changes.
Op-amp LM 741 Pin diagram:

CIRCUIT DIAGRAM: a) Measurement of Op – Amp Parameters

1. CALCULATION OF CMRR

100K

R1 (100ohms) +15V
2
6
LM 741
R1 (100ohms)

3 Vo (CRO)
- 15V
20V
1KHz
100K

2. SLEW RATE:

+15V
2

LM 741
3
Vo (CRO)
2V at 1KHz - 15V
10K
Procedure:
COMMON MODE REJECTION RATIO:
1. Connections are made as shown in circuit diagram.
2. A DC supply of 15V is given.
3. An input signal of 20V at 1 KHz is given from the signal generator.
4. The output voltage Vo is measured from the CRO is calculated by the formula
 R  V 
CMRR  1  F  S 
 R1  VO 

SLEW RATE:
1. Connections are made as shown in circuit
2. A DC dual supply of 15V is given from the TRPS.
3. An input signal of 2V at 1 KHz is given from the signal generator.
4. The frequency is increased gradually and the voltage at which square wave transforms into
triangular wave is noted. The value of frequency is also noted.
5. The slew rate is calculated by the formula.
2f mVM V
SlewRate  Sec
10 6 

PRECAUTIONS :
1. Loose and wrong connections should be avoided.
2. Readings are to be taken without parallax error.
3. The power should be turned off before making and breaking circuit connections.

Result: Measurement of Op – Amp Parameters: Determined the CMRR and slew rate of operational
amplifier.

VIVA:

1. What do you mean by op-amp?

2. List the ideal characteristics of op-amp?
3. Draw the pin diagram of LM741.
4. What is inverting and non-inverting amplifier?
5. What is offset current, offset voltage, slew rate, CMRR?
 EXPERIMENT NO: 3

Verify Different Applications of an Operational Amplifier

Objective:

Applications of Op – Amp: To realize Summing Amplifier and Subtracting Amplifier by using 741 Op-
Amp.

b) Applications of Op – Amp: To realize Integrator and Differentiator by using 741 Op-Amp.

S.No Apparatus Range Quantity

01 Operational Amplifier LM 741IC 01
02 Resistance 100Ω (2),100KΩ (2) ,10K (1) ,
1KΩ (4) 15KΩ(1)
03 Capacitors 0.01 µf, 330pf 01
04 Regulated Power supply (0-30V) 01
05 DC multi-meter
06 Signal Generator 1M Hz 01
07 CRO 01
08 Breadboard and Wires ,CRO Probes

CIRCUIT DIAGRAM:

a) Applications of Op – Amp To realize Summing Amplifier and Subtracting Amplifier by using

741 Op-Amp

i) Summer R1=R2=R3=1KΩ

Vcc = +15
4
R
2 - 7
LM
R 6
3 + 4

V
-Vee = -15

V V
ii) Subtractor: R1=R2=R3=R4=1KΩ

R1

Vcc = +15V
4
R2
2 - 7
LM
R3 6
741
3 + 4

Vo
R4 -VEE = -15V

V1 V2

Procedure:
I. Summing Amplifier:
Op amp may be used to design a circuit whose output is the sum of several input signals. Such a circuit

is called a summing amplifier or a summer. If V1 , V2 are two input signals given to the inverting
RF
terminal, then VO   V1  V2 
R
Summing Amplifier Procedure:
1. Connections are made as per the circuit diagram.
2. Input voltages V1 and V2 are given and the corresponding output voltage Vo is measured from
CRO.
3. Output varies as VO  V1  V 2  , since RF = R.
II. Subtracting Amplifier:
The function of a subtractor is to provide an output, which is equal to the difference of two input
signals (or) proportional to the difference of two input signals. If V 1 and V2 are the input voltages at
RF
inverting and non – inverting terminals, then VO   V1  V2 
R
Subtracting Amplifier Procedure:
1. Connections are made as per the circuit diagram.
2. Input voltage V1 and V2 are given to the inverting and non – inverting terminals respectively
and corresponding output voltage is measured from CRO.
3. Output varies as VO  V2  V1 

b) Applications of Op – Amp: To realize Integrator and Differentiator

Op Amp as Integrator:
A circuit in which the output voltage waveform is the integral of the input voltage waveform is the
integrator or the integration amplifier. Such a circuit is obtained by using a basic inverting amplifier
configuration with the feedback resistor RF replaced by a capacitor CF. The output voltage is given by
1
RC 
VO   V1dt

Integrator is used in signal wave shaping circuits and in analog computers. If the input is a sine wave,
the output is a cosine wave. If the input is a square wave, the output will be a triangular wave. In the
practical integrator, RF is connected across feedback capacitors CF. This RF limits the low frequency
gain and minimizes the variation in the output voltage. The input signal will be integrated properly if
the time constant
T = R1 CF is larger than the time period T of the input signal.
R1=10KΩ, R2=100KΩ, C2

C2=0.01µf
R2

Vcc = +15 V
4
R1
2 - 7
LM 741
6
3 + 4

4V Vo
Vin -Vee = -15 V

10KHz
 Op Amp as Differentiator:
The function of a differentiator is to give an output voltage, which is proportional to the rate of change
of input voltage. The differentiator may be constructed from a basic inverting amplifier if an input
resistor is replaced by capacitor C1. The output voltage is given by
dVI
VO   RC
dt

The condition for differentiator is τ << T where τ = C1RF for sine wave and square wave inputs, the
resulting differentiated outputs are cosine wave and spike outputs respectively. Differentiator is used to
detect high frequency components in an input signal.
CIRCUIT DIAGRAM:

Practical Differentiator: R1=10KΩ, R2=15KΩ C1=0.01µf, C2=330pf

C2

R2

Vcc = +15 V
C1
4
R1
2 - 7
LM 741
6
3 + 4

0.4V Vo
-Vee = -15 V

1KHz

PROCEDURE:
I. Integrator:
1. Connections are made as per the circuit diagram.
2. By using a function generator, a square wave input 4Vp-p is given.
3. The frequency applied is 10 KHz.
4. A perfect triangular wave is obtained. The peak-to-peak voltage and the time period of input and
 output waves are measured from CRO.
5. The waveforms are plotted.
II Differentiator:
1. Connections are made as per the circuit diagram.
2. A square wave input of 4V (p-p) and frequency of 1KHZ is applied from function generator.
3. Output waveform is observed. Corresponding amplitude and time period is observed and
frequency is calculated.
4. With the above data plot the output graphs with time on X-axis and voltage on Y-axis.
MODEL GRAPHS:
DIFFERENTIATOR: INTEGRATOR:

PRECAUTIONS :
1. Loose and wrong connections should be avoided.
2. Readings are to be taken without parallax error.
3. The power should be turned off before making and breaking circuit connections.
Result:
a) Applications of Op – Amp: Realized the Summing Amplifier and Subtracting Amplifier by
using 741 Op-Amp.
b) Applications of Op – Amp: Realized the Integrator and Differentiator by using 741 Op-Amp.

VIVA:
1. What are the applications of op-amp?
2. What is difference between integrator and differentiator?
3. Why is RC differentiator known as a high pass filter?
4. What is the function of integrator?
5. What are the applications of integrator and differentiator?
 EXPERIMENT NO: 4
Design of Schmitt Trigger using op-amp
Objective:
To observe the output waveform of a Schmitt trigger circuit and to note down the hysteresis voltage
VHY with the reference of VUT and VLT .
Apparatus:
S.No Apparatus Type Range Quantity
1. OP-AMP IC 741 02
2. Resistance 2.2KΩ ,10KΩ 2,1
3. Regulated Power supply (0-30V) 01
4. Signal Generator 1MHz 01
5. CRO 01
6. Breadboard and Wires ,CRO Probes

Theory:
The circuit shown is known as the Schmitt trigger or Squaring Circuit. It shows an working
comparator with positive feedback. This circuit converts an irregular shaped waveform to a square
wave hence it is called as a square wave generator. If positive feedback is added to a basic comparator
circuit, Gain can be increased greatly. The input voltage Vin triggers the output Vo every time it exceeds
certain voltage levels called upper threshold voltage V UT and lower threshold voltage VLT.
The threshold voltages are obtained by using the voltage divider R 1 - R2 where the voltage across R1 is
fed back to the (+) input. The voltage across R1 is variable reference threshold voltage that depends on
the value the polarity of the output voltage V0 . When V0 = + VSAT the voltage across R1 is called the
upper threshold Voltage VUT.
The input voltage Vin must be slightly more positive than VUT in order to cause the output Vo to switch
from
 V SAT to  VSAT as long as Vin  VUT , Vo is at  VSAT
R2
VUT 
R2
 VSAT  & VLT   VSAT 
R f  R2 R f  R2

The hysteresis voltage is equal to difference between V UT and VLT

 VHY  VUT  VLT

 R2   R2 
VHY  
R R
 VSAT   
 R R
 VSAT 

 f 2   f 2 

Circuit Diagram:
MODEL GRAPHS:

Input and output waveform of Schmitt trigger:

PROCEDURE:
1. The circuit for Schmitt trigger is connected as per the given circuit diagram.
2. A sinusoidal input of 1 KHz is applied with the help of function generator.
3. A square wave output is obtained for the corresponding input for which the positive peak voltage
(+Vsat) and negative peak voltage (-Vsat) are noted.
4. The upper threshold voltage (VUT) and lower threshold voltage (VLT) are calculated for the
corresponding output.
5. The shift angle (θ) is calculated using the formula
V UT  V P Sin 
V UT
Sin  
VP
 V UT 
  Sin 1
 
 VP 
6. The hysteresis voltage (VH) is calculated using the formula

VHY  VUT  VLT

Observations:
Input applied: Vi (p-p mV) = , T=

Output obtained:  V SAT =

 V SAT 
T=
Calculations:
R2
Upper threshold voltage: VUT   VSAT 
R f  R2

R2
Lower threshold voltage: VLT   VSAT 
R f  R2

Hysteresis voltage VHY  VUT  VLT

 VUT 
Shift angle   Sin 1  
 VP 
Tabular Form:
Amplitude Time period
Input applied Vi (p-p) =

output applied  V SAT =

 V SAT 

PRECAUTIONS:

1. Loose and wrong connections are to be avoided.

2. The output waveforms should be obtained without and distortion.
3. Parallax error should be avoided.

RESULT: Observed the output waveform of a Schmitt trigger circuit and noted down the hysteresis
voltage VHY with the reference of VUT and VLT.

Viva questions:
1. What do mean by Schmitt trigger?
2. What are the applications of Schmitt triggers?
3. What is meant by Hysteresis voltage?
4. What is meant by threshold voltage?
5. What is the difference between a Binary and Schmitt Trigger?
 EXPERIMENT NO: 5
Design and Verification of Active LPF & HPF Using Op-Amp

Objective:
To obtain the frequency response of the active filters LPF & HPF Using Op-Amp by varying the
frequency.

APPARATUS:
S.No Apparatus Type Range Quantity
1. OP-AMP LM 741 IC 01
2. Resistance 10kΩ, 16 KΩ 2,1
3. Capacitors 0.01μF 01
4. Function generator 1MHz
5. Regulated Power supply (0-30V) 01
6. Breadboard and Wires ,CRO Probes

THEORY:

Filters are frequency selective networks, which can allow desired range of frequencies and
attenuates other frequencies. Filters are classified:

1. Passive and Active filters

2. Analog and Digital Filters

Depending on the type of the elements used as resistor, capacitor, and inductor such a type of
filter is called as passive filters. By using op-amp and transistor on addition to passive elements, they
are called as active filters.

Depending on the range of frequencies the active filters can be classified as low pass, band pass,
high pass, all pass, band reject filters.
CIRCUIT DIAGRAM:
HIGH PASS BUTTERWORTH FILTER

10K
Circuit diagram

10K
2 7 +VCC(+15V)
-
741C
0.01µFD
6
3 +
Vi(100 mv) P-P 16K 4 Vo

-VEE(-15V)

LOW PASS BUTTERWORTH FILTER

MODEL GRAPHS:
HGIH PASS BUTTERWORTH FILTER & LOW PASS BUTTERWORTH FILTER

DESIGN:

Design of Ist order Butter worth filter:

(i) Given the cut off frequency FL, AO,
1
FL 
2RC
Assume C and then substituting the value in the above formula
(ii) Find R, using AO and assuming R1 find RF

PROCEDURE:
1. The circuit is connected as per the circuit diagram
2. The Frequency of the input signal is varied and the Corresponding out put voltage is noted. The
magnitude of the input Signal is kept constant throughout the experiment.
3. The gain for each frequency is calculated using the formula
V 
Gain in dB  20 log o 
 VI 
4. A graph for gain v/s frequency is plotted which is known as Frequency response.
TABULAR FORM:
HIGH PASS BUTTERWORTH FILTER
Input Voltage: 100 mv (p-p)

Frequency Out Put Gain=20log(v0/vi)

(Hz) Voltage(V) (dB)
100
200
300
500
700
1k
2k
3k
5k
7k
10k
20k
30k
50k
70k
100k
200k
300k
500k
700k
1M
LOWPASS BUTTERWORTH FILTER

Input Voltage: 100 mv (p-p)

Frequency Out Put Gain=20log(v0/vi)

(Hz) Voltage(V) (dB)
100
200
300
500
700
1k
2k
3k
5k
7k
10k
20k
30k
50k
70k
100k
200k
300k
500k
700k
1M
PRECAUTIONS:

1. Loose and wrong connections should be avoided.

2. Parallax error should be avoided.

RESULT: Designed and obtained the response of active filters by varying the frequency

Viva questions
1. What is filter?
2. What is an active filter?
3. What is high pass filters & low pass filters?
4. Name the types of filters?
5. What is butter worth filter?
 EXPERIMENT NO: 6
ASTABLE MULTIVIBRATOR USING 555 IC TIMER

Objective:

To obtain a symmetric square wave output by maintaining certain duty cycle by using 555 IC.

APPARATUS:

S.No Apparatus Type Range Quantity

1. Timer 555 IC 02
2. P N diode 1N4007 01
3. Resistance 3.3KΩ 02
4. Capacitors 0.1μF, 0.01μF 01
5. Potentiometer 10KΩ 01
6. Regulated Power supply (0-30V) 01
7. Breadboard and Wires ,CRO Probes

CIRCUIT DIAGRAM:

Vcc =12v

8 4
RA
10K

1N 4007
7 555 3
1
Output
RB 3.3K
TIMER

0.1µFD 6 5

2 1
0.01µFD
PIN DIAGRAM:
MODEL GRAPHS:

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Now the potentiometer is adjusted till the 50% duty cycle is achieved. Output waveform is
observed on the CRO.
3. Time periods of the output waveform are noted and output waveform is plotted to the scale.
4. The corresponding waveforms for other duty cycles are also obtained and plotted to scale.
Duty cycle:
The capacitor voltage for a low pass RC circuit subjected to a step input of VCC volts is given by
 t 
   
  RC  
 
VC  VCC 1  exp 
 
 
2
The time t1 taken by the circuit to charge from 0 to VCC is,
3
 t 
  1  
 
2  RC 
V  VCC 1  exp    t1  1.09 RC
3 CC  
 
 
1
The time t2 to charge from 0 to VCC is,
3
 1  
  t2 

VCC  VCC 1  exp  RC  
3  
 
t 2  0.405RC
1 2
So the time to charge from VCC to VCC is
3 3
t HIGH  t1  t 2  1.09 RC  0.405 RC
 0.69 RC

So, for the given circuit, t HIGH  0.69RA  RB C

2 1
The output is low while the capacitor discharges from VCC to VCC and the voltage across
3 3

1 2   
 t 

the capacitor is given by VCC  VCC exp  RC  


3 3  
 
t LOW  0.69 RC

For the given circuit, t LOW  0.69 RB C

Total time period, T  t HIGH  t LOW  0.69R A  RB C

Duty cycle =
t HIGH

 R A  RB  (without diode)
T R A  2 RB 

For the modified circuit Duty cycle 

R A  (with diode)
R A  RB 
Tabular Form:

Duty RA(Ω) Thigh Tlow Across pin O/P Frequency Frequency

cycle µ Sec µ Sec No:6 Voltage Theoretical Practical
1 2 Across pin
VCC VCC
3 3 No:3

(v) (v)

PRECAUTIONS:

1. Loose and wrong connections should be avoided.

2. Parallax error should be avoided.

RESULT:
Obtained a symmetric square wave output by maintaining certain duty cycle by using 555 IC

Viva questions
1. What do mean by duty cycle?
2. What is RS flip flop?
3. What is comparator?
4. What are the applications of astable multivibrator?
5. What is quasi stable state?
 EXPERIMENT: 7
Operation of R-2R ladder DAC and flash type ADC

Objective:
To study the operation of
i) R-2R DAC
ii) Flash type ADC

APPARATUS REQUIRED:
S.NO APPARATUS RANGE QUANTITY
1. OP-AMP LM 741 IC 1

2. Resistor 1KΩ, 2KΩ 1

3. Multimeter - 1
4. RPS DUAL(0-30) V 1
5. Breadboard and Wires ,CRO Probes Connecting Wires

THEORY:

In weighted resistor type DAC, op-amp is used to produce a weighted sum of digital
inputs where weights are produced to weights of bit positions of inputs. Each input is
amplified by a factor equal to ratio of feedback resistance to input resistance to which it is
connected.
 RF  1 1 1 
VOUT   D3  D2  D1  D0 
R  2 4 8 
The R-2R ladder type DAC uses resistor of only two values R and2R.The inputs to resistor
network may be applied through digitally connected switches or from output pins of a counter.
The analogue output will be the maximum, when all inputs are of logic high.
RF 1 1 1 1 
V  D3  D2  D1  D0 
R 2 4 8 16 

In a 3 input ADC, if the analog signal exceeds the reference signal, comparator turns
on. If all comparators are off, analog input will be between 0 and V/4.If C1 is high and C2 is
low input will be between V/4 and V/2.If C1 andC2 are high and C3 is low input will be
between 3V/4 and V.
CIRCUIT DIAGRAM: a) R-2R Ladder DAC:

R=1KΩ , Rf=2R Input and Output Table

S.No. I2 I1 I0 Vth Vprac

1) 0 0 0 0 0
2) 0 0 1 1.25 1.3
3) 0 1 0 2.5 2.7
4) 0 1 1 3.75 3.5
5) 1 0 0 5 4.9
6) 1 0 1 6.25 6.5
7) 1 1 0 7.5 7.2
8) 1 1 1 8.75 8.3
 b) 2-Bit Flash type ADC

Input and Output Table:

PROCEDURE:

1. Connect the circuit as shown in circuit diagram.

2. For various inputs, measure the outputs using multimeter.

PRECAUTIONS:

1. Loose and wrong connections should be avoided.

2. Parallax error should be avoided.

RESULT:
The operation of R-2R ladder DAC and Flash type ADC was studied

Viva Questions:

1. Which types of switches are not preferable for a simple weighted resistor DAC?
2. The inverted R-2R ladder can also be operated in?
3. What are the Multiplying DAC uses?
4. List out the direct type ADCs.
5. What are the main advantages of integrating type ADCs & State the Dis-advantages of ADCs?
 Cycle: II
(FPGA Based Experiments)
 EXPERIMENT: 1
Verify the functionality of Parallel adder using FPGA

Aim: : To develop a HDL Code for Parallel Adder using full adder as a sub module and
verify its functionality using Xilinx Vivado.

Apparatus: Personal Computer

Xilinx Vivado 2016
Basys3 Artix7 FPGA
Logic Diagram:

Figure: 4-Bit Parallel Adder logic diagram

Verilog Program:

Main Module Program Sub-module Verilog program

Module paralleladder(A, B, S, Co); Module fulladder(A, B, Ci, S, Co);

input [3:0] A, B;// Two 4-bit inputs Input A, B, Ci;
output[3:0] S; outputS, Co;
output Co; wire w1,w2,w3;
wire w1, w2, w3; //Structural code for one bit full adder
// instantiating four1-bit full adders in Verilog xor G1(w1, A, B);
fulladder u1(A[0], B[0], 1'b0, S[0], w1); xor G2(S, w1, Ci);
fulladder u2(A[1], B[1], w1, S[1], w2); and G3(w2, w1, Ci);
and G4(w3, A, B);
fulladder u3(A[2], B[2], w2, S[2], w3);
or G5(Co, w2, w3);
fulladder u4(A[3], B[3], w3, S[3], Co);
endmodule
endmodule
Testbench:
module paralleladdertb;
reg [3:0]A,B;
wire [3:0]S;
wire carry;
paralleladder dut(A,B,S,carry);
initial
begin
A=4'b0000;B=4'b0000;
#2 A=4'b0001;B=1'b0010;
#2 A='b1000;B=4'b0111;
#2 A=4'b1111;B=4'b1111;
#5 $stop;
end
endmodule

RTL SCHEMATIC:

Figure: 4-Bit Parallel Adder RTL diagram

Simulation Waveform

Figure: 4-Bit Parallel Adder simulation waveform

RESULT: Hence the 4-bit parallel adder is programmed using verilog and its functionality is verified
through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is HDL?
2. What is the need for Verilog HDL?
3. What is meant by simulation?
4. What is meant by synthesis?
5. What is Parallel adder?
 EXPERIMENT: 2
Verify the functionality of 4:1 Multiplexer using FPGA

Aim: To develop a HDL Code for 4:1 Multiplexer using 4:1 MUX using Gate level and Behavioral
modeling and verify its functionality using Xilinx Vivado.

Apparatus: Personal Computer

Xilinx Vivado
Basys3 Artix7 FPGA

Logic Diagram:

Figure:4x1 Multiplexer logic diagram

Verilog Program:

4x1 mux Verilog Program

Behavioral Modeling Structural Modeling

module mux41( sel, in, out ); module mux41(a,b,c,d,s0,s1,y);

input [1:0] sel; input a,b,c,d,s0,s1;
input [3:0] in; output y;
output reg out; wire w1,w2,w3,w4,w5,w6;
always @(sel or in ) not(w1,s0);
begin not(w2,s1);
if( sel == 0) and(w3,a,w1,w2);
out = in[0]; and(w4,w1,s1,b);
else if( sel == 1) and(w5,s0,w2,c);
out = in[1]; and(w6,s0,s1,d);
else if( sel == 2) or(y,w3,w4,w5,w6);
 out = in[2]; endmodule
else if( sel == 3)
out = in[3];
else
out=1’bX
end
endmodule

8:1 Multiplexer Verilog:

// 8:1 Mux using 4:1 and 2:1 Multiplexers

Figure:8x1 Multiplexer logic diagram

module mux_8x1(O,s,i);
input [7:0]i;input [2:0]s;
output O;
mux41 a0 ({s[1:0]},{ i[3:0]},w1);
mux41 a1 ({s[1:0]},{ i[7:4]},w2);
m21 a2 (w1,w2,s[2],O);
endmodule
** Sub-module Verilog programs**

2x1 mux Verilog Program

Behavioral Modeling Structural Modeling
module mux_2to1_behavioral (S,A,B,Y); module m21(Y, D0, D1, S);
input S,A,B; output Y;
output Y; input D0, D1, S;
 always @(*) begin wire T1, T2, Sbar;
if (S == 0) begin and (T1, D1, S), (T2, D0, Sbar);
Y = A; not (Sbar, S);
end or (Y, T1, T2);
else begin endmodule
Y = B;
end
end
endmodule

Testbench: 4x1 Multiplexer

module mux41_tb;
rega,b,c,d;
reg s0,s1;
wire y;
mux41 dut(a,b,c,d,s0,s1,y);
initial
begin
a=1'b1;b=1'b0;c=1'b0;d=1'b0;s0=1'b0;s1=1'b0;
#5 a=1'b0;b=1'b1;c=1'b0;d=1'b0;s0=1'b0;s1=1'b1;
#5 a=1'b0;b=1'b0;c=1'b1;d=1'b0;s0=1'b1;s1=1'b0;
#5 a=1'b0;b=1'b0;c=1'b0;d=1'b1;s0=1'b1;s1=1'b1;
#5 $stop;
end
endmodule

RTL SCHEMATIC:

Figure:8x1 Multiplexer RTL diagram

Simulation Waveform

Figure:8x1 Multiplexer Simulation waveform

RESULT: - Hence the 8x1 Multiplexer is programmed using verilog and its functionality is verified
through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is Blocking assignment?
2. What is the use of Concurrent assignments?
3. What is the difference between dataflow and Behavioral Modeling?
4. What are the applications of Multiplexers?
5. What is the difference between always and initial block?
 EXPERIMENT: 3
Verify the functionality of 1:4 Demultiplexer using FPGA

Aim: To develop a HDL Code for 1x4 Demultiplexer and verify its functionality using Xilinx Vivado.

Apparatus: Personal Computer

Xilinx Vivado
Basys3 Artix7 FPGA

Logic Diagram:

Figure:1x4 Demultiplexer logic diagram

Verilog Program:
Behavioral Modeling: Structural Modeling
module demux1_4(a_in, sel, y_out); module demux4x1(a,so,s1,y0,yl,y2,y3):
input a_in; input a,s0,s1;
input [1:0] sel; output yo, yl, y2, y3;
output [3:0] y_out; wire wi,w2:
reg [3:0] y_out; not (w1,s0);
always @(a_in, sel) not (w2,s1);
begin and (y0,a,wl,w2):
case (sel) and (yl,a,w2,s0);
2'b00:begin y_out[0]=a_in; y_out[1]= 1'b0; and (y2,a,sl,wl);
y_out[2]= 1'b0;y_out[3]=1'b0; end and (y3,a,s1,s0);
2'b01: begin y_out[0]= 1'b0;y_out[1]=a_in; endmodule
y_out[2]= 1'b0;y_out[3]=1'b0; end
2'b10: begin y_out[0]= 1'b0;y_out[1]=1'b0;
y_out[2]=a_in; y_out[3]=1'b0; end
2'b11: begin y_out[0]= 1'b0; y_out[1]= 1'b0;
y_out[2]=1'b0;y_out[3]=a_in; end
default: y_out=3'b000;
endcase
end
endmodule

Testbench:

module demux102_tb;
reg a,s0,s1:
wire y0, yl,y2, y3;
demux102dut (a, so, sl, y0, yl, y2, y3);
initial
begin
a=1'b1;
s0=1'b0;sl=1'b0;
#5 s0=1'b0;s1=1'b1;
#5 s0=1'bi:sl=1'b0;
#5 s0=1'bl:s1=1'b1;
#5 $stop:
end
endmodule

RTL Schematic:
Simulation Waveform:

RESULT: - Hence the 1x4 DeMultiplexer is programmed using verilog and its functionality is verified
through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of case statement?
2. What is the use of Non-blocking assignments?
3. What is the syntax of equality Operator?
4. What are the applications of DeMultiplexers?
5. What is the Testbench?
 EXPERIMENT: 4
Verify the functionality of 8:3 Encoder and Priority Encoder using FPGA

Aim: To develop a HDL Code for 8:3 encoder using behavioral and Gate level modeling and verify its
functionality using Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Logic Diagram:

Figure:8:3Encoder logic diagram

Verilog Program:
////8:3 Encoder using Structural Modeling
Behavioral Modeling: Structural Modeling

module encoder (din, dout); input [7:0] din; module en(a,y);

output [2:0] dout; reg[2:0] dout; always
@(din) begin if (din ==8'b00000001) input [7:0]y;
dout=3'b000; else if (din==8'b00000010) output [2:0]a;
dout=3'b001; else if (din==8'b00000100)
dout=3'b010;else if (din==8'b00001000) or(a[0],y[7],y[5],y[3],y[1]);
dout=3'b011;else if (din==8'b00010000)
or(a[1],y[7],y[6],y[3],y[2]);
dout=3'b100; else if (din ==8'b00100000)
dout=3'b101; else if (din==8'b01000000) or(a[2],y[7],y[6],y[5],y[4]);
dout=3'b110; else if (din==8'b10000000)
dout=3'b111; elsedout=3'bX; end endmodule endmodule
Testbench:
module en_tb;
reg [7:0]y;
wire [2:0]a;
en dut (a,y);
initial
begin
y=8'b00000001;
#5 y=8'b00000010;
#5 y=8'b00000100;
#5 y=8'b00001000;
#5 y=8'b00010000;
#5 y=8'b00100000;
#5 y=8'b01000000;
#5 y=8'b10000010;
#5 $stop;
end
endmodule

Simulation Results:
RTL SCHEMATIC:

8:3 Priority encoder

Structural Modeling Behavioral Modeling

Module prior_otb_enco(DOUT, D); output module encoder (din, dout);
[2:0] DOUT; input [7:0] din; wire din7_not, input [7:0] din;
din6_not, din5_not, din4_not, din2_not; wire output [2:0] dout;
wa0, wa1, wa2, wa3, wa4;;//instanitate gates reg [2:0] dout;
not g0 (din7_not, din[7]), g1 (din6_not, always @(din) begin
din[6]), g2 (din5_not, din[5]), g3 (din4_not, if (din ==8'b00000001) dout=3'b000;
din[4]), g4 (din2_not, din[2]); else if (din==8'b0000001X) dout=3'b001;
and g5 (wa0, din6_not, din4_not, din[3]), g6 else if (din==8'b000001XX) dout=3'b010;
(wa1, din5_not, din4_not, din[3]), g7 (wa2, else if (din==8'b00001XXX) dout=3'b011;
din5_not, din4_not, din[2]),g8 (wa3, din6_not, else if (din==8'b0001XXXX) dout=3'b100;
din[5]), g9 (wa4, din6_not, din4_not, din2_not, else if (din ==8'b001XXXXX) dout=3'b101;
din[1]); or g11(dout[2], din[7], din[6], din[5], else if (din==8'b01XXXXXX) dout=3'b110;
din[4]), g12(dout[1], din[7], din[6], wa1, wa2), else if (din==8'b1XXXXXXX) dout=3'b111;
g13(dout[0], din[7], wa0, wa3, wa4), g14(V, elsedout=3'bX; end endmodule
din[0], din[1], din[2], din[3], din[4], din[5],
din[6], din[7]); endmodule

Testbench:
module pe_tb;
reg [7:0]y;
reg en;
wire [2:0]a;
encoder dut(y,a,en);
initial
begin
en=1'b1;y=8'b00000001;
#5 en=1'b1;y=8'b00000010;
#5 en=1'b1;y=8'b00000100;
#5 en=1'b1;y=8'b00001000;
#5 en=1'b1;y=8'b00010000;
#5 en=1'b1;y=8'b00100000;
#5 en=1'b1;y=8'b01000000;
#5 en=1'b1;y=8'b10000000;
#5 $stop;
end
endmodule

Simulation Results:

RTL SCHEMATIC:
RESULT: Hence the 8:3 encoder and priority encoder is programmed using verilog and its
functionality is verified through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is priority encoder?
2. What is the use of $stop?
3. What is RTL Schematic?
4. What are the applications of encoders?
 EXPERIMENT: 5
Verify the functionality of 3:8 Decoder using FPGA

Aim: To develop a HDL Code for 3:8 decoder using behavioral and Gate level modeling and verify its
functionality using Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Logic Diagram:

Figure: 3:8 Decoder logic diagram

Verilog Program:

Behavioral Modeling Structural Modeling

module decoder3_to_8( in,out, en); module de(a,din,y)
input [2:0] in; input [2:0]a;
input en; input din;
output [7:0] out; output [7:0]y;
reg [7:0] out; wire w0,w1,w2;
always @( in or en) not(w0,a[0]);
begin not(w1,a[1]);
if (en) not(w2,a[2]);
begin and(y[0],din,w2,w1,w0);
out=8'd0; and(y[1],din,w2,a[1],w0);
case (in) and(y[2],din,w2,a[1],a[0]);
3'b000: out[0]=1'b1; and(y[3],din,w0,w1,a[2]);
3'b001: out[1]=1'b1; and(y[4],din,a[2],w1,a[0]);
3'b010: out[2]=1'b1; and(y[5],din,a[2],a[1],w0);
 3'b011: out[3]=1'b1; and(y[6],din,a[0],w1,w2);
3'b100: out[4]=1'b1; and(y[7],din,a[0],a[1],a[2]);
3'b101: out[5]=1'b1; endmodule
3'b110: out[6]=1'b1;
3'b111: out[7]=1'b1;
default: out=8'd0;
endcase
end
else
out=8'd0;
end
endmodule

Testbench
module de_tb;
wire[7:0]y;
reg[2:0]a;
de dut(a,y,din);
initial
begin
din=1'b1;a=3'b000;
#5 din=1'b1;a=3'b001;
#5 din=1'b1;a=3'b010;
#5 din=1'b1;a=3'b011;
#5 din=1'b1;a=3'b011;
#5 din=1'b1;a=3'b100;
#5 din=1'b1;a=3'b101;
#5 din=1'b1;a=3'b110;
#5 din=1'b1;a=3'b111;
#5 din=1'b0;a=3'b000;
#5 din=1'b0;a=3'b001;
#5 din=1'b0;a=3'b010;
#5 din=1'b0;a=3'b011;
#5 din=1'b0;a=3'b100;
#5 din=1'b0;a=3'b101;
#5 din=1'b0;a=3'b110;
#5 din=1'b0;a=3'b111;
#5 $stop:
end
endmodule
Simulation Results:

RTL SCHEMATIC:

Simulation Waveform:

RESULT: - Hence the 3:8 Decoder is programmed using verilog and its functionality is verified
through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of conditional statement?
2. What is the use of Nested if statements?
3. What is the syntax of equality Operator?
4. How many 2:4 decoders required for 3:8 decoder?
5. What is the use of $monitor?
 EXPERIMENT: 6
Verify the functionality of Binary to Gray code converter using FPGA

Aim: To develop a HDL Code for Binary to Gray code converter using dataflow modeling and verify
its functionality using Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Verolog Program:
module binary2gray(
input [3:0] a,
output [3:0] g
);
assign g[0]=a[0]^a[1];
assign g[1]=a[1]^a[2];
assign g[2]=a[2]^a[3];
assign g[3]=a[3];
endmodule

Testbench
module b2g_tb;
reg [3:0]a;
wire [3:0]g;
binary2gray dut(a,g);
initial
begin
a=4'b0000;
#5 a=4'b0001;
#5 a=4'b0010;
#5 a=4'b0011;
#5 a=4'b0100;
#5 a=4'b0101;
#5 a=4'b0110;
#5 a=4'b0111;
#5 a=4'b1000;
#5 a=4'b1001;
#5 a=4'b1010;
#5 a=4'b1011;
#5 a=4'b1100;
#5 a=4'b1101;
#5 a=4'b1110;
#5 a=4'b1111;
#5 $stop;
end
endmodule
Simulation Results:

RTL Schematic:

RESULT: - Hence the Binary to Gray code converter is programmed using verilog and its functionality
is verified through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of Code converters ?
2. What is the use of assignment statement?
3. What are the different operators available in Verilog
4. What are the applications of Code converters?
5. What is the Testbench?
 EXPERIMENT: 7
Verify the functionality of Comparator using FPGA

Aim: To develop a HDL Code for comparator using Gate Level modeling and verify its functionality
using Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Verilog Program:
module comparator(
input a,
input b,
output c,
output d,
output e
);
wire w0,w1;
not(w0,a);
not(w1,b);
and(c,w0,b);
and(e,w1,a);
nor(d,c,e);
endmodule

Testbench:
module c_tb;
reg a,b;
wire c,d,e;
comparator dut(a,b,c,d,e);
initial
begin
#5 a=2;b=3;
#5 a=3;b=2;
#5 a=2;b=2;
#5 $stop;
end
endmodule
Simulation Waveform:

RTL schematic:

RESULT: - Hence the Comparator is programmed using verilog and its functionality is verified
through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of Comparator ?
2. What are the primitive gates available in HDL?
3. What are the different Shifting available in Verilog
4. What are the applications of Comparators?
5. What is the Testbench?
 EXPERIMENT: 8
Verify the functionality of Arithmetic and Logic Unit using FPGA

8. Design and Verify the functionality of Arithmetic and Logic Unit using FPGA

Aim: To develop a HDL Code for ALU using behavioral modeling and verify its functionality using
Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Verilog Program:

module alu(result,data1,data2,select);
output reg [7:0] result;
input [7:0] data1,data2;
input [2:0] select;
always @(*)
begin
case (select)
3'b000:
result = data1+data2; //add
3'b001:
result = data1 - data2; //subtraction
3'b010:
result = data1 * data2; //product
3'b011:
result = data1 / data2; //divison
3'b100:
result=data1&data2;//and
3'b101:
result=~data2;//not
3'b110:
result=data1|data2;//or
3'b111:
result=data1^data2;//xor
default:
result = 8'b00000000;
endcase
end
endmodule
Testbench
module alu_tb;
reg [7:0] data1,data2; //inputs
reg [2:0] select; //control input
wire [7:0] result; //output
alu dut(result,data1,data2,select);
initial
begin
data1=8'b00000101;
data2=8'b00000011;
#5select=3'b000;
#5select=3'b001;
#5select=3'b010;
#5select=3'b011;
#5select=3'b100;
#5select=3'b101;
#5select=3'b110;
#5select=3'b111;
#5 $stop;
end
endmodule
Simulation results:
RTL SCHEMATIC:

RESULT: - Hence the ALU is programmed using verilog and its functionality is verified through
simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of ternary operator?
2. What is the use of conditional assignments?
3. What are the different operators available in Verilog?
4. What are the applications of ALU?
5. What is the Testbench?
 EXPERIMENT: 9
Verify the functionality of Counter using FPGA

Aim: To develop a HDL Code for Counter using Gate Level modeling and verify its functionality
using Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Verilog Program:
module counter(clk,rst,count);
input clk,rst;
output reg [3:0]count;
always@(posedge clk) begin
if(rst == 1 || count == 9)
count <= 0;
else
count <= count + 1;
end
endmodule

Testbench:
module tb();
reg clk,rst;
wire [3:0]count;
counter c1(clk,rst,count);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 0;
#5 rst = 1;
#10 rst = 0;
#200 $finish;
end
initial
$monitor("%d%d",clk,count);
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule
Simulation Waveform:

RESULT: - Hence the Mod-10 Counter is programmed using verilog and its functionality is verified
through simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of Counter ?
2. What are the primitive gates available in HDL?
3. What are the different Counters available?
4. What are the applications of Counters?
5. What is the difference between of Synchronus and Asynchronous Counters?
 EXPERIMENT: 10
Verify the functionality of D-Flip Flop using FPGA

Aim: To develop a HDL Code for D-flipflop using Gate Level modeling and verify its functionality
using Xilinx Vivado.
Apparatus: Personal Computer
Xilinx Vivado
Basys3 Artix7 FPGA

Verilog Programme:

//Rising Edge D Flip Flop:

module RisingEdge_DFlipFlop(D,clk,Q);
input D; // Data input
input clk; // clock input
output Q; // output Q
always @(posedge clk)
begin
Q <= D;
end
endmodule

Testbench:
module tb_DFF();
reg D;
reg clk;
reg reset;
wire Q;

RisingEdge_DFlipFlop_SyncReset dut(D,clk,reset,Q);

initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
reset=1;
D <= 0;
#100;
reset=0;
D <= 1;
 #100;
D <= 0;
#100;
D <= 1;
end
endmodule

Simulation Waveform:

RESULT: - Hence the D-flipflop is programmed using verilog and its functionality is verified through
simulation and synthesis using Xilinx Vivado.

VIVA QUESTIONS:
1. What is the use of D-FF ?
2. What are the keywords used for representing clock signal in Verilog HDL?
3. What is the difference between Latch and Flipflop?
4. What are the applications of flipflops?
5. What is the difference between initial and always keyword?
 Hardware Implementation steps
Introduction to the XILINX Vivado

In this part, you will use Xilinx's Vivado to design, simulate and implement all the
digital circuits. Once completed the simulation, implementation will be downloaded
to the BASYS board and then tested using the on board LED's and switches.

1. Double click on the Vivado icon on your desktop to open up the welcome window
of the development tool (as shown below). Three main sections can be observed in
this window:“Quick Start”, “Tasks”, and “Learning Center”.

2. Now, click on “Create Project” to create a new project. You have to be careful about
where to save your project file in the computer lab. The computers in the lab run a hard
disk protection program that could interfere with Xilinx. So, if you save your project in
a preserved folder, Xilinx might have problem with running the simulation. You have
two choices: (1) either save the project directly on your USB flash disk. This option is
good since your USB disk have normal read/write access and Xilinx runs correctly.
However, this option can be slow for USB flash disks. The option (2)is to save the
project in a folder that’s in the desktop. Then, compress the folder into a ZIP file and
email it to yourself. Start by creating a folder on the desktop called‘Lab_1’. Create this
folder in Windows, not from Xilinx. Then, in Xilinx, create a new project
inside“Lab_1”.Name your project, ‘Test_1’andit will be in the folder
“\Desktop\Lab_1\Test_1”. When you finish your lab, you can copy your project on
your flash disk.
3. In the next window, choose “RTL Project” as the project type. You can the
description of this type in the window.

4. In the opened window, you can create source file (Verilog/Verilog Header/System
Verilog/VHDL/Memory File) for your new project or add sources from the existing
projects. Click on “Create File”, and in the opened window choose “Verilog” for the
“File type”, write a name for your file (“Part_1”), and click on “Ok”. Continue
clicking on Next until reaching the “Default Part” window.
5. In this window, choose “Artix-7” for the “Family”, “-1” for “Speed grade”,
and“cpg236” for “Package”. In the shown parts, select “xc7a35tcpg236-1”. Take a
look at the configuration of this part for your own familiarity.
6. Look at your new project summary.

7. Define the input and the output ports of your module according to the shown window.
8. The opened window is the main environment for your project that is called “Project
Manager”. You can explore it by seeing the options of each category in the toolbar on
top of the window. In the left side, you can see the “Settings”, “Add
Sources”,“”Language Template”, “IP Catalog”, “IP Integrator”, “Simulation”, “RTL
Analysis”, “Synthesis”, “Implementation”, and “Program and Debug”. Each of these
serves apart of the digital design flow. In the middle, you can see the windows for
“Sources”, “Properties”, “Project Summary”, and the reports and summaries for the
execution of the project files.
9. Double click on the “Part_1.v” file (*.v) in the “Sources” window. The VERILOG
source file appears where the window is located in right side. Note that the module
shows the defined inputs and outputs that were selected previously.
Now that the design is finished, you must build the project. Click Run Synthesis on the left
hand menu towards the bottom, on successful completion click on Run Implementation. On
successful completion of implementation click on “Open Implemented Design” in the dialog
box that appears. Proceed to the next steps.”
10. We do the “RTL Analysis”. Expand the Open Elaborated Design entry under the RTL
Analysis tasks of the Flow Navigator pane and click on Schematic. The model(design)
will be elaborated and a logic view of the design is displayed. Notice that some of the
switch inputs go through gates before being output to LEDs and the rest go straight
through to LEDs as modeled in the file.
11. Once RTL analysis is performed, another standard layout called the I/O Planning is
available. Click on the drop-down button and select the I/O Planning layout.

12. Notice that the Package view is displayed in the Auxiliary View area, Device
Constraints tab is selected, and I/O ports tab is displayed in the Console View area.
Also notice that design ports (led and swt) are listed in the I/O Ports tab with both
having multiple I/O standards. Move the mouse cursor over the Package view,
highlighting different pins. Notice the pin site number is shown at the bottom of the
Vivado GUI, along with the pin type (User IO, GND, VCCO…) and the I/O bank it
belongs to.

13. The user should imply input the “Site” table next to the input/output to the desired
pin. From Appendix D, for BASYS board, SW0 is located on pin V17, SW1 is located
on pin V16 and LED0 is located on pin U16. These names can also be found inside the
parentheses below the switches and the ones in the right side of the LEDs on the board.
The value of I/O Std for all of these switches should be setto“LVCMOS33”.
 14. Select File>Save Constraints. Name and save the constraint file.

Then we should simulate the design using the XSim Simulator. Click Add Sources under the Project

Manager tasks of the Flow Navigator pane. Select the Add or Create Simulation Sources option and
click Next. We create a new file for simulation, andnameitasPart_1_Sim.
15. For the simulation file, we don’t need to set the I/O. Click OK in this step.
16. Double click on the “Part_1_Sim.v” in the Sources window to type the following
contents into the file. Within the Test-bench file, the simulation step size and
theresolutioncanbespecifiedinline1.TheTest-benchmodule definition begins on line 23.
Line 33 instantiates the UUT (unit/module under test). Also, it should be mentioned
that the timescale for both the Verilog module and the test-bench module is set to 1
ns/1 ps.
17. Click on Run Simulation >Run Behavioral Simulation under the Project Manager
tasks of the Flow Navigator window. The test-bench and source files are compiled and
the XSim simulator is run (assuming no errors). Click on the “Zoom Fit” icon to see all
the spectrum of simulation.
18. In the last part, let’s click on the Generate Bit stream on the left hand menu towards
the bottom. Vivado runs through both Run Synthesis and Run Implementation before it
generates the bit stream automatically. This process generates the *.BIT file needed to
program the FPGA. The following window will be opened if the bit stream is
generated.
19. Go to “Flow  Hardware Manager” in the toolbar. Turn ON your board by pushing
up its power switch. Click on “Auto Connect” icon in the Hardware Manager window.
Click on the board name “xc7a35t_0 (1)”. In the opened “Hardware Device
Properties” window, make sure the bit file is selected for the “Programming file”.
Next, right click on the board name and choose “Program Device…”. Once the status
of the board goes to “Programmed”, then you can check the design functionality on
the board by changing the state of switches.
20. Check the operation for the two-input AND gate and fill out the following
table. Remember we have selected switch SW0 for input “Inp_1”, switch SW1
for input “Inp_2” and led LED0 for the output “Outp”. Toggle the switches for
the states shown in the table below and fill in the output by observing LED0.
This table should confirm the truth table for a two-input AND gate.

SW0 SW1 LED0

0 0 Off
0 1 Off
1 0 Off
1 1 ON

88