1. One way is to use External Clock with duty cycle 50-50 and in a frequency range 1 MHz to 50 MHz connected to XTAL1 Pin. 2. The second way is by connecting External Crystal Oscillator but its range is lower between 1 MHz to 30 MHz. 3. We can also use on-chip PLL Oscillator but here external clock frequency should not exceed range from 10 MHz to 25 MHz 07-11-2024 Dr. Anuja A Odhekar LPC 2148-PLL • PLL is used to generate system clock from between 10 MHz to 25 MHz. • PLL may multiply frequency to range from 10 MHz to 60 MHz (LPC21xx Series) and 48 MHz for USB if used. • PLL uses frequency multiplier which can be in a range from 1 to 32, in real world situation this value should not be higher than 6 due to upper frequency limit. • PLL generator allows running ARM at high speed with low frequency oscillator connected. • Also, this minimizes EMC emission as frequency is multiplied inside ARM Chip. PLL allows changing frequency dynamically. • In LPC2148 microcontrollers there are two PLLs which provide programmable frequencies to the CPU and USB System. [PLL0: For System Clock, PLL1: For USB Clock]
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL • LPC2148 Microcontroller needs two clocks; one is for its peripherals and other for its CPU. • CPU works faster with higher frequencies whereas peripheral needs lower frequency to work with. • The Peripheral Clock (PCLK) and CPU Clock (CCLK) gets clock input from a PLL or from external source. • After RESET, configuration of PLL (Phase Lock Loop) and VPB (VLSI Peripheral Bus) Divider would be first thing to do. 07-11-2024 Dr. Anuja A Odhekar LPC 2148-PLL
CCO-Current Controlled Oscillator
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
LPC-2148 PLL unit itself uses CCO (Current Controlled Oscillator) which operates in the range between 156 MHz to 320 MHz.
• So there is additional divider which keeps CCO within its range, while PLL provides desired frequency.
• Output clock is generated by dividing CCO frequency by 2, 4, 8, 16. Minimum divider is ‘2’ so output of PLL will always have duty cycle 50% for sure.
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL-CCLK The Peripheral Clock i.e. PCLK is derived from CPU Clock i.e. CCLK.
The APB Divider decides the operating frequency of PCLK.
The input to APB Divider is CCLK and output is PCLK. By Default PCLK runs at 1/4th the speed of CCLK.
To control APB Divider we have a register called VPBDIV.
The value in VPBDIV controls the division of CCLK to generate PCLK as shown below: APB bus clock (PCLK) is one fourth of the VPBDIV=0x00 processor clock (CCLK) APB bus clock (PCLK) is the same as the VPBDIV=0x01 processor clock (CCLK) APB bus clock (PCLK) is one half of the VPBDIV=0x02 processor clock (CCLK) Reserved. If this value is written to the APBDIV VPBDIV=0x03 register, it has no effect (the previous setting is retained). 07-11-2024 Dr. Anuja A Odhekar LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL-Setting UP for PLL
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
LPC 2148-PLL
07-11-2024 Dr. Anuja A Odhekar
07-11-2024 Dr. Anuja A Odhekar 07-11-2024 Dr. Anuja A Odhekar LPC 2148-PLL
