Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki Politechniki Gdańskiej Nr 49

XLVIII Międzyuczelniana Konferencja Metrologów

MKM 2016
Akademia Górniczo-Hutnicza w Krakowie, 5-7 września 2016

HIGH-VOLTAGE DIVIDER WITH AUTOMATIC CALIBRATION - MODEL TESTS

Szymon BARCZENTEWICZ1, Jerzy NABIELEC2, Andrzej WETULA3

1. AGH w Krakowie, Katedra Wydział Elektrotechniki, Automatyki i Inżynierii Biomedycznej

tel.: +48 12 617 28 57 e-mail: barczent@agh.edu.pl
2. AGH w Krakowie, Wydział Elektrotechniki, Automatyki i Inżynierii Biomedycznej
tel.: +48 12 617 27 11 e-mail: jena@agh.edu.pl
3. AGH w Krakowie, Wydział Elektrotechniki, Automatyki i Inżynierii Biomedycznej
tel.: +48 12 617 27 11 e-mail: wetula@agh.edu.pl

Abstract: This paper describes structure and method of operation uncertainty (at or below 0.1%) together with wide band,
of active high voltage divider with automatic calibration capable of while keeping low cost due to lack of high precision
measuring multi-harmonic signals. With the use of this structure components in a circuit.
identification of varying parameters of the measurement instrument
is possible. Measured signal is used for automatic calibrations as
the only excitation. To achieve such performance modification of
1.1. The two-sensor method
two-sensor method was proposed. Simulation studies on proposed The two-sensor method also being referred as blind
model were conducted that examined influence of Analog to Digital method was proposed in 1936 by H. von Pfriem. The basic
Converters (ADCs) quantization and amplifier parameters, and also version of method was proposed for sensors of inertial
ability of self-identification of structure’s parameters. Relative character, which can be described by first order differential
errors of divider ratio estimation were calculated for different cases: equation. A system realizing this method is presented in
the structure with an ideal amplifier, the structure with an amplifier Figure 1.
with defined parameters and the structure with an amplifier with
defined parameters with gain correction procedures.

Keywords: voltage divider, self calibration, two-sensor method,

frequency characterization, frequency response.

1. INTRODUCTION

HIGH voltage measurement is very common and

important task of electrical engineering. Transformers and
capacitive dividers are most frequently used devices for high Fig. 1. The two-sensor method of auto-calibration. T1,T2 - time
voltage measurement. Unfortunately, both of them have constants, u - input signal, p, x - output signals, Tc1, Tc2 - adjustable
limited operational bounds. Moreover, they cannot be used dynamic parameters, Req - value of criterion used by the regulator.
in HVDC (High-Voltage Direct Current) systems, as they
operate only with alternating current. Another type of high It consists of 2 sensors characterized by time constants
voltage transceivers are resistive dividers. They have a broad T1 and T2, which can simultaneously measure the input
frequency band and are capable of converting DC voltage. signal u. Output signals p and x of these sensors are supplied
However, they are expensive, hard to design and prone to to inputs of serial correctors with adjustable dynamic
environmental conditions like temperature and external parameters Tc1 and Tc2. Based on the difference between
electrical fields as it was shown in [1] and [2]. For these output signals of correctors, the value of criterion used by
reasons their use in power grid is limited. Mentioned papers the regulator Reg is brought down to zero by adjusting the
describe passive resistive dividers, based on Park divider. dynamic properties of correctors. Once this criterion is
Another type of dividers are active dividers proposed and fulfilled, the output signals of both correctors reproduce the
described in e. g. [7], [8] and [10]. In this paper we propose measured signal reliably. The original method was able to
an active high voltage divider with automatic calibration identify dynamic characteristics of transducers only. The
procedure. It’s operation principles are based on a modified novelty of our application is that it allows to identify static
two-sensor method [3] discussed and improved in [4] and characteristics as well. The presented idea of voltage divider
[5]. The main idea of the proposal is construction of a low allows to find coefficients of its mathematical model during
cost divider that is not prone to negative influence of its operation, using measured signal as the only excitation
environmental condition, aging of components or undefined for identification procedures. Our application is also capable
load impedance. Described divider can be used, among other of measuring broadband signals.
applications, in input circuitry of an energy meter or a power
quality meter. In such an application it can provide very low
2. THE STRUCTURE OF THE DIVIDER Step 2: Left branch of the divider changes its
AND OPERATING PRINCIPLES structure (Fig. 2b). Impedances Z1 and Z2 along with an
amplifier create an active attenuator circuit. Impedance Z1 is
The main parameter of every voltage divider is divider connected in between high voltage and virtual ground. This
ratio k. The value of measured high voltage UA is calculated way the high current is flowing trough impedance Z1, as well
by multiplying low voltage U2 by ratio k = (Z3+Z4)/Z4 , as it as trough impedance Z2. Impedance Z2 has no influence on
is shown in the right branch in Figure 2a. In standard voltage current flowing through Z1. Measuring voltage U3 current
transducers k is considered as a real constant number. For flowing trough Z1 and Z2 can be estimated. Divider ratio k is
voltage transformers it is usually only defined for 50Hz, estimated as a complex number
while for resistive dividers a frequency response is given,
but precise load impedance is required in order to keep it Z3  Z4 U1 (2)
within declared uncertainty. In this paper k is considered as a k  .
Z4 U
complex number, defined separately for each analyzed U 2  U1 4
U3
frequency of measured signal (as a frequency response). It is
also assumed that k fluctuates in time, taking into account
aforementioned changes of divider parameters. The proposed Voltages UA and UB are calculated using updated k
divider can be used in both AC and DC systems, depending
on an implementation. For AC version inductors or U A  kU 2 , (3)
capacitors might be used as impedances in conjunction with
resistors. In [6] several embodiments of high voltage divider U B  kU 4 , (4)
with automatic calibration have been introduced. This paper
takes under consideration an active divider, which contains Equation (2) is true only for an ideal operational
an operational amplifier [7], [8]. Presented device was amplifier. Finite gain of an amplifier forces us to calculate
designed in a way it could adapt the two-sensor method. In real amplifier’s transfer function. The influence of amplifier
this method measuring transducer consists of two parallel transfer function is calculated in the correction (third) step.
branches which measure the same value. The main Step 3: Additional impedance Z5 is connected to the
assumption of the proposed structure is that one branch with circuit as it is shown in Figure 3a, afterward like in Figure
Z3 and Z4 has constant structure and is used for the 3b.
continuous measurement. The other branch with Z1 and Z2
changes its structure and performs a series of auxiliary
measurements. These measurements allow to perform self-
identification process of both dynamic and static properties.

Fig. 3. A structure for estimating amplifier’s transfer function

influence. A – amplifier gain, UEa; UEb – input voltages, Z5 –
additional impedance, U5; U6; U7; U8 – voltages.

Equations describing the circuit in Figure 3 are given

by (5).
 U6  U8
U Ea  A U Eb   A
a)  b)  (5)
Fig. 2. Two stable configurations of the divider structure. Z1; Z2; Z3; U 5  U Ea U Ea  U 6 U 7  U Eb U Eb  U 8
Z4– impedances, U1; U2; U3; U4 – measured voltages, ADC1; ADC2    
– analog to digital converters.  Z 5 Z2  Z 2 Z5

Figure 2 shows the simplified circuit of active Using (5) the gain of amplifier A is calculated
adaptive divider in two stable configurations. In order to
maintain transparency of the picture we do not show digital U 6U 7  2U 6U 8  U 8U 5 (6)
control and synchronization system. Constantly repeated A .
U 6U 8  U 5U 7
operation cycle of adaptive divider is divided into three
distinctive steps:
Step 1: Left and right branch of the adaptive divider Evaluation of A is prone to accuracy of voltages U5 U8
circuit are made of unknown impedances (Fig.2a) – Z1 and measurement like (2) due to bad condition number of the
Z2 for the left branch and Z3 and Z4 for the right branch. denominator.
Voltages U1 and U2 on Z2 and Z4 impedances are acquired by Modified divider constant is given by
ADCs. Parallel connected unknown input impedances of
ADCs and impedances of divider itself are considered U1 (7)
k .
together as a single object in self-identification process.  1 U4
U 2 1    U 1
Voltage UA is computed based on U1 andU2 measurement  A U3

Z1  Z 2 Z  Z4 (1)
UA  U1  3 U2.
Z2 Z4

18 Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki PG, ISSN 2353-1290, Nr 49/2016

3. SIMULATION RESULTS for 24 bit resolutions equals 2.224e-6. As expected, errors δk
for 24 bit quantization are smaller than for 18 bit
In order to verify proposed structure of adaptive quantization due to a smaller quantization noise.
active divider a number of simulations were performed. All
simulations were conducted in Matlab environment. Results 3.2. The influence of a real amplifier's gain and its
are presented for models of various complexity. To examine correction
an accuracy of a divider constant estimation, relative error δk Table 1 shows maximum value of estimation error δk
(8) was introduced. Amplitude and phase differences in a for each harmonic for Z 2  700;950 and Z 2    / 2;  / 2
reference divider constant and an evaluated divider constant,
for various gains of amplifier modeled as a first order inertial
considered as complex numbers, were accounted together
object. Gain values were chosen based on the real
with a quality called total vector error (TVE), as for
operational amplifiers OP07 and OP37 working in closed-
Synchrophasor IEEE Standard C38.118.1 [9].
loop for cutoff frequency fc = 1000 Hz. Gains of these
amplifiers equals respectively 4·105 and 1.8·106.
k  k ref Calculations for gain 108 were also performed to verify how
k  (8)
k ref the proposed structure would work with very high, but finite
gain.
The results in the first part of Table II called ”Without
where kref is a reference divider constant, k is an evaluated
correction” refer to situation described in Step 1 and Step 2.
constant and | · | stands for modulus. All simulations were
The second part of the Table II called ”With correction”
conducted for multi-harmonic signal uA = Umax1cos(2πf0t +
refers to situation with additional Step 3.
ϕ10) + Umax5cos(2π5f0t + ϕ50) + Umax7cos(2π7f0t + ϕ70), where
For nominal frequency for algorithm without
basic frequency f0 = 50Hz. Maximum voltage values:
correction, for both resolutions, errors decrease with the
Umax1 = 1kV, Umax5 = 5.5V and Umax7 = 4.2V were chosen
growth of gain of the amplifier. Divider ratio for higher
according to results of actual measurements in power
harmonic is estimated with bigger error than in case of
system. Phase of harmonic components are: ϕ10= ϕ50= ϕ70= 0
nominal frequency. Use of the amplifier gain correction
rad. Signal was sampled with a frequency of Fs = 50kHz,
results in a significant decrease of a divider ratio estimation
and the number of samples N = Fs/f0 = 1000. The ADCs’
error for each harmonic. The Table 1 presents the worst case
ranges was ±10V.
results of several simulation experiments. In authors'
Impedance Z1 = 99kΩ, and Z2= 1kΩ. This is
opinion, bad numerical condition of the denominator in (2)
considered as operating point. Z2 is fluctuated around this
may cause the misaligned result for the 24-bit resolution and
operating point with respect to module and phase. kref is
gain 1.8 106.
referenced to distorted Z2. Impedances Z3 = 99kΩ and Z4 =
1kΩ are fixed.
Table 1. Estimation error δk for 18 and 24 bit quantization for
different gains of amplifier.
3.1. The effect of quantization with ideal amplifier Without correction
In configuration for Step 2, for an ideal amplifier k is Bits 18 24
given by equation (2). Amp. 4·105 1.8·106 108 4·105 1.8·106 108
Influence of ADCs resolution of 18 and 24 bits on δk 1st har. 4.9e-4 2.3e-4 1.5e-4 3.8e-4 8.4e-4 3.7e-4
was checked. Figure 4 shows estimation errors δk for 5 th har. 0.086 0.086 0.086 0.002 0.001 0.001
7 th har. 0.070 0.070 0.070 0.002 0.001 0.001
nominal frequency in the case of 24 bit resolution. With correction
Bits 18 24
Amp. 4·105 1.8·106 108 4·105 1.8·106 108
1st har. 1.5e-4 1.4e-4 1.4e-4 2.4e-6 2.7e-6 2.1e-6
5 th har. 0.079 0.078 0.078 9.5e-4 9.7e-4 9.2e-4
7 th har. 0.072 0.071 0.070 0.001 0.001 9.6e-4

4. CONCLUTIONS

The presented theory and simulation validate the

concept of an active high-voltage divider with automatic
calibration. The proposed divider has the unique ability of
identifying its parameters while being constantly connected
to the Grid, which eliminates the necessity of periodic
manual calibrations, but considerable modification of legal
regulations and standards are required in order to make it
possible.
Fig. 4. Estimation error δk in the case of 24 bit quantization. In simulations calculated error δk arises mainly due to
insufficient resolution of ADCs. For nominal frequency for
The increase of errors for impedance |Z2| close to 18 bit ADC maximum error in examined range equals 1.5e-4
1000Ω is caused by saturation of ADCs. The change of and for 24 bit ADC maximum error drops to 2.4e-6. Such
phase of impedance Z2 has no influence on estimation. results were achieved due to amplifier gain correction
Maximum value of estimation error δk for Z 2  700;950 procedures. For higher harmonics maximum errors are
several orders higher but still reasonable. Simulation results
and Z 2    / 2;  / 2 for 18 bit and 24 bit resolution was
show that the use of the correction procedure allows to
calculated. Error δk for 18 bit resolution equals 1.516e-4 and achieve errors of the same order of magnitude as for an ideal
Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki PG, ISSN 2353-1290, Nr 49/2016 19
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being another step towards industrial implementation. 2012/066147, 2012-08-17.
7. Petersons O., Metha S.P.: An Active High-Voltage
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Error for the Second Order System, Proceedings of

AKTYWNY DZIELNIK WYSOKIEGO NAPIĘCIA Z AUTOKALIBRACJĄ -

BADANIA MODELOWE
Niniejszy artykuł opisuje budowę i zasadę działania aktywnego dzielnika napięciowego z autokalibracją. Układ ten
jest w stanie zidentyfikować swoje parametry. Sygnał mierzony jest jedynym potrzebnym w tym celu wymuszeniem. Zasada
działania układu bazuje na modyfikacji metody dwuczujnikowej. Przeprowadzone zostały symulacyjne badania modelowe
proponowanego układu. Zbadany został wpływ wykorzystywanych w układzie przetworników AC, wpływ kwantyzacji, oraz
możliwość autoidentyfikacji parametrów dzielnika. Obliczone zostały błędy względne estymacji przekładni dzielnika (stałej
dzielnika) dla różnych przypadków: układu z idealnym wzmacniaczem operacyjnym, układu z wzmacniaczem o
zdefiniowanych parametrach i układu ze wzmacniaczem o zdefiniowanych parametrach wraz z zaimplementowaną
procedurą identyfikacji jego wzmocnienia i korekcją negatywnego wpływu ograniczonej wartości wzmocnienia.

Słowa kluczowe: dzielnik napięcia, autokalibracja, metoda dwuczujnikowa, charakterystyki częstotliwościowe, odpowiedź
częstotliwościowa.

20 Zeszyty Naukowe Wydziału Elektrotechniki i Automatyki PG, ISSN 2353-1290, Nr 49/2016