TDA7718N

3 band car audio processor

Features
■ Input multiplexer
– QD1: quasi-differential stereo inputs
– SE1: stereo single-ended input
– SE2: stereo single-ended input
– SE3: stereo single-ended input TSSOP28
– FD1 / SE4+SE5: 1 full-differential input or 2
stereo single-ended inputs ■ Speaker
■ Loudness – 4 independent soft step speaker controls
– 2nd order frequency response – +15 dB to -79 dB with 1 dB steps
– Programmable center frequency – Direct mute
(400 Hz / 800 Hz / 2400 Hz) ■ Subwoofer
– 15 dB with 1 dB steps – 2nd order low pass filter with programmable
– Selectable high frequency boost cut off frequency
– Selectable flat-mode (constant attenuation) (55 Hz / 85 Hz / 120 Hz / 160 Hz)
– 2 independent soft step level control,
■ Volume
+15 dB to –79 dB with 1 dB steps
– +23 dB to -31 dB with 1 dB step resolution
■ Mute functions
– Soft-step control with programmable blend
times – Direct mute
– Digitally controlled SoftMute with 4
■ Bass
programmable mute-times
– 2nd order frequency response (0.48 ms/0.96 ms/8 ms/16 ms)
– Center frequency programmable in 4 steps
■ Offset detection
(60 Hz / 80 Hz / 100 Hz / 200 Hz)
– Offset voltage detection circuit for on-board
– Q programmable 1.0/1.25/1.5/2.0
power amplifier failure diagnosis
– DC gain programmable
– -15 dB to 15 dB range with 1 dB resolution
Description
■ Middle
– 2nd order frequency response The TDA7718N is a high performance signal
– Center frequency programmable in 4 steps processor specifically designed for car radio
(500 Hz / 1 kHz / 1.5 kHz / 2.5 kHz) applications. The device includes a high
– Q programmable 0.75/1.0/1.25 performance audioprocessor with fully integrated
– -15 dB to 15 dB range with 1 dB resolution audio filters and new Soft Step architecture. The
digital control allows programming in a wide range
■ Treble
of filter characteristics.
– 2nd order frequency response
(10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz)
Table 1. Device summary
– Center frequency programmable in 4 steps
(10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) Order code Package Packing
– -15 dB to 15 dB with 1 dB resolution
TDA7718N TSSOP28 Tube
TDA7718NTR TSSOP28 Tape and reel

September 2013 Doc ID 16502 Rev 2 1/40

www.st.com 1
Contents TDA7718N

Contents

1 Block circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin connection and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Description of the audioprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.1 Quasi-differential stereo input (QD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.2 Single-ended stereo input (SE1, SE2, SE3) . . . . . . . . . . . . . . . . . . . . . 13
4.1.3 Full-differential stereo input or single-ended input (FD1/QD2/SE4+SE5) 13
4.2 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.1 Loudness attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.2 Peak frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.3 High frequency boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.4 Flat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 SoftMute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 SoftStep volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.1 Bass attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.2 Bass center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.3 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.4 DC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Middle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.1 Middle attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.2 Middle center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.3 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7 Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/40 Doc ID 16502 Rev 2

TDA7718N Contents

4.7.1 Treble attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.7.2 Center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8 Subwoofer filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9 Softstep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.10 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.11 Audioprocessor testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 I2C bus electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.1 Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.2 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.3 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Doc ID 16502 Rev 2 3/40

List of tables TDA7718N

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I2C bus electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Main selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Soft mute / others (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. SoftStep I (5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11. SoftStep II / DC detector (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Loudness (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Volume / output gain (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Treble filter (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Middle filter (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Bass filter (11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Subwoofer / middle / bass (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Testing audio processor 1 (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. Testing audio processor 2 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. Testing audio processor 3 (21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4/40 Doc ID 16502 Rev 2

TDA7718N List of figures

List of figures

Figure 1. Block circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. FD / QD / SE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Loudness attenuation @ fP = 400 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Loudness center frequencies @ attn. = 15 dB.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Loudness attenuation, fc = 2.4 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7. SoftMute timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Bass control @ fC = 80 Hz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Bass center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Bass quality factors @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Middle control @ fC = 1 kHz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. Middle center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Middle quality factors @ gain = 14 dB, fC = 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Treble control @ fC = 17.5 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Treble center frequencies @ gain = 14 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Subwoofer cut frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. DC offset detection circuit (simplified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. I2C bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21. I2C bus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. TSSOP28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 16502 Rev 2 5/40

 1

6/40
Figure 1.
Block circuit diagram

MUTE

MONO FADER OUTLF

SOFT
LOUDNESS VOLUME TREBLE MIDDLE BASS
MUTE
MONO FADER OUTRF

SE1L
SE1R MONO FADER OUTLR
Block circuit diagram
Block circuit diagram

SE2L
SE2R MONO FADER OUTRR

SE3L
SE3R MONO FADER OUTSWL
QD1L

Doc ID 16502 Rev 2

QD1G SUBWOOFER
MONO FADER OUTSWR
QD1R
FD1L+/QD2L/SE4L

MAIN INPUT MULTIPLEXER

FD1L-/QD2G/SE4R
FD1R-/QD2G/SE5L
FD1R+/QD2R/SE5R

DC-Offset
DIGITAL Detector
SUPPLY I2C BUS
CONTROL

VCC GND CREF SCL SDA WIN_IN WIN_TC DC_ERR

TDA7718N
TDA7718N Pin connection and pin description

2 Pin connection and pin description

2.1 Pin connection

Figure 2. Pin connection (top view)

SE1L 1 28 Winin
SE1R 2 27 DCErr
SE2L 3 26 SDA
SE2R 4 25 SCL
SE3L 5 24 VCC
SE3R 6 23 MUTE
QD1L 7 22 WINTC
QD1G 8 21 OUTLF
QD1R 9 20 OUTLR
FD1L+/QD2L/SE4L 10 19 OUTRR
FD1L-/QD2G/SE4R 11 18 OUTRF
FD1R-/QD2G/SE5L 12 17 OUTSWL
FD1R+/QD2R/SE5R 13 16 OUTSWR
CREF 14 15 GND

2.2 Pin description

Table 2. Pin description
No. Pin name Description I/O

1 SE1L Single-end input left I

2 SE1R Single-end input right I
3 SE2L Single-end input left I
4 SE2R Single-end input right I
5 SE3L Single-end input left I
6 SE3R Single-end input right I
7 QD1L quasi-differential stereo inputs left I
8 QD1G quasi-differential stereo inputs common I
9 QD1R quasi-differential stereo inputs right I
10 FD1L+/QD2L/SE4L Full differential + input left or quasi-differential left or single-end input left I

Doc ID 16502 Rev 2 7/40

Pin connection and pin description TDA7718N

Table 2. Pin description (continued)

No. Pin name Description I/O

11 FD1L-/QD2G/SE4R Full differential - input left or quasi-differential ground or single-end input right I
12 FD1R-/QD2G/SE5L Full differential - input right or quasi-differential ground or single-end input left I
13 FD1R+/QD2R/SE5R Full differential + input right or quasi-differential right or single-end input right I
14 CREF Reference capacitor O
15 GND Ground S
16 OUTSWR Subwoofer right output O
17 OUTSWL Subwoofer left output O
18 OUTRF Front right output O
19 OUTRR Rear right output O
20 OUTLR Rear left output O
21 OUTLF Front left output O
22 WinTC DC offset detector filter output O
23 MUTE External mute pin I
24 VCC Supply S
2C
25 SCL I bus clock I
26 SDA I2C bus data I/O
27 DC_ERR DC offset detector output O
28 WIN_IN DC offset detector input I

8/40 Doc ID 16502 Rev 2

TDA7718N Electrical specifications

3 Electrical specifications

3.1 Thermal data

Table 3. Thermal data
Symbol Description Value Unit

Rth-j amb Thermal resistance junction-to-ambient 114 °C/W

3.2 Absolute maximum ratings

Table 4. Absolute maximum ratings
Symbol Parameter Value Unit

VS Operating supply voltage 10.5 V

Vin_max Maximum voltage for signal input pins 7 V
Tamb Operating ambient temperature -40 to 85 °C
Tstg Storage temperature range -55 to 150 °C

3.3 Electrical characteristics

VS = 8.5 V; Tamb= 25 °C; RL= 10 k; all gains = 0 dB; f = 1 kHz; unless otherwise specified

Table 5. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Supply
Vs Supply voltage - 7.5 8.5 10 V
Is Supply current - 23 29 35 mA
Input selector
Rin Input resistance All single ended inputs 70 100 130 k
VCL Clipping level Input gain = 0 dB 2 - - VRMS
SIN Input separation - - 95 - dB
Differential stereo inputs
Rin Input resistance Differential 70 100 - k
Common mode rejection ratio for VCM = 1 VRMS @ 1 kHz 44 60 - dB
CMRR
main source VCM = 1 VRMS @ 10 kHz 44 60 - dB
20 Hz - 20 kHz, A-weighted;
eNo Output noise @ speaker outputs - 12 22 µV
all stages 0 dB

Doc ID 16502 Rev 2 9/40

Electrical specifications TDA7718N

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Loudness control
AMAX Max attenuation - 14 15 16 dB
ASTEP Step resolution - 0.5 1 1.5 dB
fP1 - 400 - Hz
fPeak Peak frequency fP2 - 800 - Hz
fP3 - 2400 - Hz
Volume control
GMAX Max gain - 22 23 24 dB
AMAX Max attenuation - - -31 -30 dB
ASTEP Step resolution - 0.5 1 1.5 dB
EA Attenuation set error - -0.75 0 +0.75 dB
ET Tracking error - - - 2 dB
Adjacent attenuation steps -3 0.1 3 mV
VDC DC steps
From 0 dB to GMIN -5 0.5 5 mV
Soft mute
AMUTE Mute attenuation - 80 100 - dB
T1 0.35 0.48 0.65 ms
T2 0.7 0.96 1.3 ms
TD Delay time
T3 5.6 7.6 9.6 ms
T4 12.3 15.3 18.3 ms
VTH Low Low threshold for SM pin - - - 1 V
VTH High High threshold for SM pin - 2.5 - - V
RPU Internal pull-up resistor - 32 45 58 k
VPU Internal pull-up voltage - 3 3.3 3.6 V
Bass control
fC1 - 60 - Hz
fC2 - 80 - Hz
Fc Center frequency
fC3 - 100 - Hz
fC4 - 200 - Hz
Q1 - 1 - -
Q2 - 1.25 - -
QBASS Quality factor
Q3 - 1.5 - -
Q4 - 2 - -
CRANGE Control range - ±14 ±15 ±16 dB
ASTEP Step resolution - 0.5 1 1.5 dB
DC = off -1 0 +1 dB
DCGAIN Bass-DC-gain
DC = on, gain = ±15 dB ±4.3 ±4.7 ±5.1 dB

10/40 Doc ID 16502 Rev 2

TDA7718N Electrical specifications

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Middle control
CRANGE Control range - ±14 ±15 ±16 dB
ASTEP Step resolution - 0.5 1 1.5 dB
fC1 - 500 - Hz
fC2 - 1 - kHz
fc Center frequency
fC3 - 1.5 - kHz
fC4 - 2.5 - kHz
Q1 - 0.75 - -
QMIDDLE Quality factor Q2 - 1 - -
Q3 - 1.25 - -
Treble control
CRANGE Clipping level - ±14 ±15 ±16 dB
ASTEP Step resolution - 0.5 1 1.5 dB
fC1 - 10 - kHz
fC2 - 12.5 - kHz
fc Center frequency
fC3 - 15 - kHz
fC4 - 17.5 - kHz
Speaker attenuators
GMAX Max gain - 14 15 16 dB
AMAX Max attenuation - - -79 -74 dB
ASTEP Step resolution - 0.5 1 1.5 dB
AMUTE Mute attenuation - 80 90 - dB
EE Attenuation set error - - - 2 dB
VDC DC steps Adjacent attenuation steps - 0.1 5 mV
Audio outputs
d = 0.3 %; byte8_D6=1 2 - - VRMS
VCL Clipping level
d = 1 %; byte8_D6=0 2.2 - - VRMS
ROUT Output impedance - - 30 100 
RL Output load resistance - 2 - - k
CL Output load capacitor - - - 10 nF
VDC DC voltage level - 3.8 4.0 4.2 V
Subwoofer lowpass
fLP1 - 55 - Hz
fLP2 - 85 - Hz
fLP Lowpass corner frequency
fLP3 - 120 - Hz
fLP4 - 160 - Hz

Doc ID 16502 Rev 2 11/40

Electrical specifications TDA7718N

Table 5. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

DC offset detection circuit

V1 ±10 ±25 ±40 mV
V2 ±30 ±50 ±70 mV
Vth Zero comp. window size
V3 ±50 ±75 ±100 mV
V4 ±70 ±100 ±130 mV
- 2 11 30 µs
- 5 22 50 µs
tsp Max rejected spike length
- 10 33 70 µs
- 15 44 90 µs
ICHDCErr DCErr charge current - 2 5 8 µA
IDISDCErr DCErr discharge current - 4 5 9 mA
VOutH DCErr high voltage - 3 3.3 3.6 V
VOutH DCErr low voltage - - 100 300 mV
General
BW=20 Hz to 20 kHz A-
- 12 22 µV
Weighted, all gain = 0 dB
eNO Output noise
BW=20 Hz - 20 kHz A-
- 7 12 µV
Weighted, Output muted
all gain = 0 dB, A-weighted;
S/N Signal to noise ratio 98 104 - dB
Vo = 2 VRMS
D Distortion VIN =1 VRMS; all stages 0 dB - 0.01 0.1 %
SC Channel separation left/right - - 90 - dB

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4 Description of the audioprocessor

4.1 Input stages

One quasi-differential stereo input, one full-differential stereo input and maximum five
single-ended inputs are available.

4.1.1 Quasi-differential stereo input (QD1)

The QD input is implemented as a buffered quasi-differential stereo stage with 100 k input-
impedance at each input. There is -3 dB attenuation at QD input stage.

4.1.2 Single-ended stereo input (SE1, SE2, SE3)

The input-impedance at each input is 100 k and the attenuation is fixed to -3 dB for
incoming signals.

4.1.3 Full-differential stereo input or single-ended input (FD1/QD2/SE4+SE5)

This device provides a full-differential stereo input stage (FD1) or 2nd quasi-differential
stereo input stage. The full differential is a buffered full-differential stereo stage with 100 k
input-impedance at each input. When using as QD2 application, it needs to connect the two
QD2G pins together from external and the input impedance at QDG becomes 50 k. This
stage can be also configured as 2 single-ended stereo input stages (SE4 and SE5). The
configuration is done with the input selector control bits and the selection of FD1 and QD2 is
controlled by a separate bit. There is -3 dB attenuation at the input stage. Figure 3 shows
the block diagram of this input stage.

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Figure 3. FD / QD / SE block diagram

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4.2 Loudness
There are four parameters programmable in the loudness stage.

4.2.1 Loudness attenuation

Figure 4 shows the attenuation as a function of frequency at fP = 400 Hz.

Figure 4. Loudness attenuation @ fP = 400 Hz.

4.2.2 Peak frequency

Figure 5 shows the four possible peak-frequencies at 400, 800 and 2400 Hz.

Figure 5. Loudness center frequencies @ attn. = 15 dB.

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4.2.3 High frequency boost

Figure 6 shows the different Loudness shapes in low and high frequency boost.

Figure 6. Loudness attenuation, fc = 2.4 kHz

4.2.4 Flat mode

In flat mode the loudness stage works as a 0 dB to -15 dB attenuator.

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4.3 SoftMute
The digitally controlled SoftMute stage allows muting/demuting the signal with a I2C bus
programmable slope. The mute process can either be activated by the SoftMute pin or by
the I2C bus. This slope is realized in a special S-shaped curve to mute slow in the critical
regions (see Figure 7).
For timing purposes the bit 0 of the I2C bus output register is set to 1 from the start of muting
until the end of demuting.

Figure 7. SoftMute timing

1
EXT.
MUTE

+SIGNAL

REF

-SIGNAL

1
I2C BUS
OUT
D97AU634 Time

Note: Please notice that a started mute-action is always terminated and could not be interrupted
by a change of the mute –signal.

4.4 SoftStep volume

When the volume-level is changed audible clicks could appear at the output. The root cause
of those clicks could either be a DC-offset before the volume-stage or the sudden change of
the envelope of the audio signal. With the SoftStep-feature both kinds of clicks could be
reduced to a minimum and are no more audible. The blend-time from one step to the next is
programmable as 5 ms or 10 ms. The SoftStep control is described in detail in Chapter 4.9.

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4.5 Bass
There are four parameters programmable in the bass stage:

4.5.1 Bass attenuation

Figure 8 shows the attenuation as a function of frequency at a center frequency of 80 Hz.

Figure 8. Bass control @ fC = 80 Hz, Q = 1

4.5.2 Bass center frequency

Figure 9 shows the four possible center frequencies 60, 80, 100 and 200 Hz.

Figure 9. Bass center frequencies @ gain = 14 dB, Q = 1

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4.5.3 Quality factors

Figure 10 shows the four possible quality factors 1, 1.25, 1.5 and 2.

Figure 10. Bass quality factors @ gain = 14 dB, fC = 80 Hz

4.5.4 DC mode
In this mode the DC-gain is increased by 4.4 dB. In addition the programmed center
frequency and quality factor is decreased by 25 % which can be used to reach alternative
center frequencies or quality factors.

Figure 11. Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz

1. The center frequency, Q and DC-mode can be set fully independently.

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4.6 Middle
There are three parameters programmable in the middle stage:

4.6.1 Middle attenuation

Figure 12 shows the attenuation as a function of frequency at a center frequency of 1 kHz.

Figure 12. Middle control @ fC = 1 kHz, Q = 1

4.6.2 Middle center frequency

Figure 13 shows the four possible center frequencies 500 Hz, 1 kHz, 1.5 kHz and 2.5 kHz.

Figure 13. Middle center frequencies @ gain = 14 dB, Q = 1

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4.6.3 Quality factors

Figure 14 shows the three possible quality factors 0.75, 1 and 1.25.

Figure 14. Middle quality factors @ gain = 14 dB, fC = 1 kHz

4.7 Treble
There are two parameters programmable in the treble stage:

4.7.1 Treble attenuation

Figure 15 shows the attenuation as a function of frequency at a center frequency of
17.5 kHz.

Figure 15. Treble control @ fC = 17.5 kHz.

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4.7.2 Center frequency

Figure 16 shows the four possible center frequencies 10 k, 12.5 k, 15 k and 17.5 kHz.

Figure 16. Treble center frequencies @ gain = 14 dB

4.8 Subwoofer filter

The subwoofer lowpass filter has Butterworth characteristics with programmable cut-off
frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz). The output phase can be selected between 0
deg and 180 deg. The input of subwoofer takes signal from bass filter output or output of
input mux.

Figure 17. Subwoofer cut frequencies

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4.9 Softstep control

In this device, the softstep function is available for volume, speaker, loudness, treble, middle
and bass block. With softstep function, the audible noise of DC offset or the sudden change
of signal can be avoided when adjusting gain setting of the block.
For each block, the softstep function is controlled by softstep on/off control bit in the control
table. The softstep transient time selection (5 ms or 10 ms) is common for all blocks and it is
controlled by softstep time control bit. The softstep operation of all blocks has a common
centralized control. In this case, a new softstep operation can not be started before the
completion previous softstep.
There are two different modes to activate the softstep operation. The softstep operation can
be started right after I2C data sending, or the softstep can be activated in parallel after data
sending of several different blocks. The two modes are controlled by the ‘act bit’ (it is
normally bit7 of the byte.) of each byte. When act bit is ‘0’, which means action, the softstep
is activated right after the date byte is sent. When the act bit is ‘1’, which means wait, the
block goes to wait for softstep status. In this case, the block will wait for some other block to
activate the operation. The softstep operation of all blocks in wait status will be done
together with the block which activate the softstep. With this mode, all specific blocks can do
the softstep in parallel. This avoids waiting when the softstep is operated one by one.

Chip Addr Sub Addr 0xxxxxxx

| Softstep start here

Chip Addr Sub Addr 1xxxxxxx 1xxxxxxx ...... 0xxxxxxx

| Softstep start
here for all

4.10 DC offset detector

Using the DC offset detection circuit (Figure 18) an offset voltage difference between the
audio power amplifier and the APR's Front and Rear outputs can be detected, preventing
serious damage to the loudspeakers. The circuit compares whether the signal crosses the
zero level inside the audio power at the same time as in the speaker cell. The output of the
zero-window-comparator of the power amplifier must be connected with the WinIn-input of
the APR. The WinIn-input has an internal pull-up resistor connected to 5.5 V. It is
recommended to drive this pin with open-collector outputs only.
To compensate for errors at low frequencies the WinTC-pin are implemented, with external
capacitors introducing the same delay  = 7.5 k * Cext as the AC-coupling between the
APR and the power amplifier introduces. For the zero window comparators, the time
constant for spike rejection as well as the threshold are programmable.
For electrical characteristics see Chapter 3 on page 9.
A low-active DC-offset error signal appears at the DCErr output if the next conditions are
both true:
a) Front and rear outputs are inside zero crossing windows.
b) The Input voltage VWinIn is logic low whenever at least one output of the power
amplifier is outside the zero crossing windows.

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After power-on, the external attached capacitor is rapidly charged (fast-charge) to overcome
a false indication.

Figure 18. DC offset detection circuit (simplified)

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4.11 Audioprocessor testing

In the test mode, which can be activated by setting bit D7 of the I2C subaddress byte and bit
D0 of the testing audioprocessor byte, several internal signals are available at the SE1L pin.
In this mode, the input resistance of 100 k is disconnected from the pin. Internal signals
available for testing are listed in the data-byte specification.

Figure 19. Test circuit

100nF
SE1L SE1L WnIn

100nF
SE1R SE1R DCErr

100nF
SE2L SE2L SDA

100nF
SE2R SE2R SCL

100nF
SE3L SE3L VCC
100nF 10uF
100nF
SE3R SE3R MUTE

100nF
QD1L QD1L TSSOP28 WINTC

22u 4.7u
QD1G QD1G OUTLF OUTLF

100nF 4.7u
QD1R QD1R OUTLR OUTLR

4.7u 4.7u

FD1L+/QD2L/SE4L FD1L+/QD2L/SE4L OUTRR OUTRR

4.7u 4.7u

FD1L-/QD2G/SE4R FD1L-/QD2G/SE4R OUTRF OUTRF

4.7u 4.7u

FD1R-/QD2G/SE5L FD1R-/QD2G/SE5L OUTSWL OUTSWL

4.7u 4.7u

FD1R+/QD2R/SE5R FD1R+/QD2R/SE5R OUTSWR OUTSWR

CREF GND
10uF

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I2C bus specification TDA7718N

5 I2C bus specification

5.1 Interface protocol

The interface protocol comprises:
● a start condition (S)
● a chip address byte (the LSB determines read/write transmission)
● a subaddress byte
● a sequence of data (N-bytes + acknowledge)
● a stop condition (P)
● the max. clock speed is 400 kbit/s
● 3.3 V logic compatible

Figure 20. I2C bus interface protocol

1. S = Start
2. ACK = Acknowledge

5.2 I2C bus electrical characteristics

Table 6. I2C bus electrical characteristics
Symbol Parameter Min Max Unit

fSCL SCL clock frequency - 400 kHz

VIH High level input voltage 2.4 - V
VIL Low level input voltage - 0.8 V
tHD,STA Hold time for START 0.6 - µs
tSU,STO Setup time for STOP 0.6 - µs
tLOW Low period for SCL clock 1.3 - µs
tHIGH High period for SCL clock 0.6 - µs
tF Fall time for SCL/SDA - 300 ns
tR Rise time for SCL/SDA - 300 ns
tHD,DAT Data hold time 0 - ns
tSU,DAT Data setup time 100 - ns

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Figure 21. I2C bus data

5.2.1 Receive mode

S 1 0 0 0 1 0 0 R/W ACK TS X AI A4 A3 A2 A1 A0 ACK DATA ACK P

S = Start
R/W = "0" -> Receive Mode (Chip can be programmed by µP)
"1" -> Transmission Mode (Data could be received by µP)
ACK = Acknowledge
P = Stop

TS = Testing mode
AI = Auto increment

5.2.2 Transmission mode

S 1 0 0 0 1 0 0 R/W ACK X X X X X X BZ SM ACK P

SM = Soft mute activated for main channel

BZ = Softstep Busy (‘0’ = Busy)
X = Not used
The transmitted data is automatic updated after each ACK. Transmission can be repeated
without new chip address.

5.2.3 Reset condition

A Power-On-Reset is invoked if the supply voltage is below than 3.5 V. After that the
registers are initialized to the default data written in following tables.

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Table 7. Subaddress (receive mode)

MSB LSB
Function
I2 I1 I0 A4 A3 A2 A1 A0

Testing mode
0 - - - - - - - Off
1 On
- x - - - - - - Not used
Auto increment mode
- - 0 - - - - - Off
1 On
- - - 0 0 0 0 0 Main selector
- - - 0 0 0 0 1 Not used
- - - 0 0 0 1 0 Not used
- - - 0 0 0 1 1 Not used
- - - 0 0 1 0 0 Soft mute / others
- - - 0 0 1 0 1 Soft step I
- - - 0 0 1 1 0 Soft step II / DC-detector
- - - 0 0 1 1 1 Loudness
- - - 0 1 0 0 0 Volume / output gain
- - - 0 1 0 0 1 Treble
- - - 0 1 0 1 0 Middle
- - - 0 1 0 1 1 Bass
- - - 0 1 1 0 0 Subwoofer / middle / bass
- - - 0 1 1 0 1 Speaker attenuator left front
- - - 0 1 1 1 0 Speaker attenuator right front
- - - 0 1 1 1 1 Speaker attenuator left rear
- - - 1 0 0 0 0 Speaker attenuator right rear
- - - 1 0 0 0 1 Subwoofer attenuator left
- - - 1 0 0 1 0 Subwoofer attenuator right
- - - 1 0 0 1 1 Testing audio processor 1
- - - 1 0 1 0 0 Testing audio processor 2
- - - 1 0 1 0 1 Testing audio processor 3

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5.3 Data byte specification

Table 8. Main selector (0)
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0

Main source selector

0 0 0 SE1
0 0 1 SE3
0 1 0 QD1
- - - - - 0 1 1 QD2 / FD1
1 0 0 SE2
1 0 1 SE4
1 1 0 SE5
1 1 1 Mute
FD / QD2 selection
- - - - 0 - - - FD
1 QD2
Main source input gain select
- - - 0 - - - - 0 dB
1 3 dB
Subwoofer flat
- - 0 - - - - - Off
1 On
x x - - - - - - Not used

Not used (1-3)

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Table 9. Soft mute / others (4)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0

Soft mute
- - - - - - - 0 On
1 Off
Pin influence for mute
- - - - - - 0 - Pin and IIC
1 IIC
Soft mute time
0 0 0.48 ms
- - - - 0 1 - - 0.96 ms
1 0 7.68 ms
1 1 15.36 ms
Subwoofer input source
- - - 0 - - - - Input mux
1 Bass output
Subwoofer enable (OUTSWL & OUTSWR)
- - 0 - - - - - On
1 Off
Fast charge
- 0 - - - - - - On
1 Off
Anti-alias filter
0 - - - - - - - On
1 Off (bypass)

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Table 10. SoftStep I (5)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0

Loudness soft step

- - - - - - - 0 On
1 Off
Volume soft step
- - - - - - 0 - On
1 Off
Treble soft step
- - - - - 0 - - On
1 Off
Middle soft step
- - - - 0 - - - On
1 Off
Bass soft step
- - - 0 - - - - On
1 Off
Speaker LF soft step
- - 0 - - - - - On
1 Off
Speaker RF soft step
- 0 - - - - - - On
1 Off
Speaker LR soft step
0 - - - - - - - On
1 Off

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Table 11. SoftStep II / DC detector (6)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0

Speaker RR soft step

- - - - - - - 0 On
1 Off
Subwoofer left soft step
- - - - - - 0 - On
1 Off
Subwoofer right soft step
- - - - - 0 - - On
1 Off
Soft step time
- - - - 0 - - - 5 ms
1 10 ms
Zero-comparator window size
0 0 ±100 mV
- - 0 1 - - - - ±75 mV
1 0 ±50 mV
1 1 ±25 mV
Spike rejection time constant
0 0 11 µs
0 1 - - - - - - 22 µs
1 0 33 µs
1 1 44 µs

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Table 12. Loudness (7)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Attenuation
0 0 0 0 0 dB
0 0 0 1 -1 dB
- - - -
: : : : :
1 1 1 0 -14 dB
1 1 1 1 -15 dB
Center frequency
0 0 Flat
- - 0 1 - - - - 400 Hz
1 0 800 Hz
1 1 2400 Hz
High boost
- 0 - - - - - - On
1 Off
Soft step action
0 - - - - - - - Act
1 Wait

Table 13. Volume / output gain (8)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Gain/attenuation
0 0 0 0 0 0 +0 dB
0 0 0 0 0 1 +1 dB
: : : : : : :
0 0 1 1 1 1 +15 dB
0 1 0 0 0 0 +16 dB
: : : : : : :
0 1 0 1 1 1 +23 dB
- -
0 1 1 0 0 0 Not used
: : : : : : :
0 1 1 1 1 1 Not used
1 0 0 0 0 0 -0 dB
: : : : : : :
1 0 1 1 1 1 -15 dB
: : : : : : :
1 1 1 1 1 1 -31 dB
Output gain
- 0 - - - - - - 1 dB
1 0 dB
Soft step action
0
- - - - - - - Act
1
Wait

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Table 14. Treble filter (9)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Gain/attenuation
0 0 0 0 0 -15 dB
0 0 0 0 1 -14 dB
: : : : : :
0 1 1 1 0 -1 dB
- - - 0 1 1 1 1 0 dB
1 1 1 1 1 0 dB
1 1 1 1 0 +1 dB
: : : : : :
1 0 0 0 1 +14 dB
1 0 0 0 0 +15 dB
Treble center frequency
0 0 10.0 kHz
- 0 1 - - - - - 12.5 kHz
1 0 15.0 kHz
1 1 17.5 kHz
Soft step action
0 - - - - - - - Act
1 Wait

Table 15. Middle filter (10)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0

Gain/attenuation
0 0 0 0 0 -15 dB
0 0 0 0 1 -14 dB
: : : : : :
0 1 1 1 0 -1 dB
- - - 0 1 1 1 1 0 dB
1 1 1 1 1 0 dB
1 1 1 1 0 +1 dB
: : : : : :
1 0 0 0 1 +14 dB
1 0 0 0 0 +15 dB
Middle Q factor
0 0 0.75
- 0 1 - - - - - 1
1 0 1.25
1 1 Reserved
Soft step action
0 - - - - - - - Act
1 Wait

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Table 16. Bass filter (11)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Gain/attenuation
0 0 0 0 0 -15 dB
0 0 0 0 1 -14 dB
: : : : : :
0 1 1 1 0 -1 dB
- - - 0 1 1 1 1 0 dB
1 1 1 1 1 0 dB
1 1 1 1 0 +1 dB
: : : : : :
1 0 0 0 1 +14 dB
1 0 0 0 0 +15 dB
Bass Q factor
0 0 1.0
- 0 1 - - - - - 1.25
1 0 1.5
1 1 2.0
Soft step action
0 - - - - - - - Act
1 Wait

Table 17. Subwoofer / middle / bass (12)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Subwoofer cut-off frequency
0 0 55 Hz
- - - - - - 0 1 85 Hz
1 0 120 Hz
1 1 160 Hz
Subwoofer output phase
- - - - - 0 - - 180 deg
1 0 deg
Middle center frequency
0 0 500 Hz
- - - 0 1 - - - 1000 Hz
1 0 1500 Hz
1 1 2500 Hz
Bass center frequency
0 0 60 Hz
- 0 1 - - - - - 80 Hz
1 0 100 Hz
1 1 200 Hz
Bass DC mode
0 - - - - - - - On
1 Off

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Table 18. Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Gain/attenuation
0 0 0 0 0 0 0 0 dB
0 0 0 0 0 0 1 1 dB
: : : : : : : :
0 0 0 1 1 1 1 +15 dB
- 0 0 1 0 0 0 0 -0 dB
0 0 1 0 0 0 1 -1 dB
: : : : : : : :
1 0 1 1 1 1 0 -78 dB
1 0 1 1 1 1 1 -79 dB
1 1 x x x x x mute
Soft step action
0 - - - - - - - Act
1 Wait

Table 19. Testing audio processor 1 (19)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Audio processor testing mode
- - - - - - - 0 Off
1 On
Test multiplexer at SE1L (1)
0 0 0 0 SSCLK
0 0 0 1 REQ
0 0 1 0 SMCLK
0 0 1 1 DCDet Vth High
0 1 0 0 DCDet Vth Low
- - - -
0 1 0 1 IntZeroErr
0 1 1 0 Ref5V5
0 1 1 1 VGB1.95
1 0 0 0 Clock200k
1 0 0 1 SDCLK
1 0 1 0 VrefDCO
Clock fast mode (2)
- - 0 - - - - - On
1 Off
Clock source (2)
- 0 - - - - - - External
1 Internal (200 kHz)
Attenuator gain clock control (2)
0 - - - - - - - On
1 Off
1. The control bit needs both I2C test mode on & sub-address test mode on.
2. The control bit does not depend on test mode.

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Table 20. Testing audio processor 2 (20)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Test architecture (1)
- - - - - - - 0 Normal
1 Split
Oscillator clock (2)
- - - - - - 0 - 400 kHz
1 800 kHz
Softstep curve (2)
- - - - - 0 - - S-Curve
1 Linear curve
Manual set busy signal (1)
0 0 Auto
- - - 0 1 - - - Auto
1 0 0
1 1 1
Request for clk generator (1)
0 0 Allow
- - - 0 1 - - - Allow
1 0 Stopped
1 1 Stopped
No DCO spike rejection(1)
- - 0 - - - - - On
1 Off
x x - - - - - - Not used
1. The control bit needs sub-address test mode on.
2. The control bit does not depend on test mode.

Table 21. Testing audio processor 3 (21)

MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
Enable clock for FL/FR/RL/RR/SWL/SWR
- - - - - - - 0 On
1 Off
Enable clock for volume
- - - - - - 0 - On
1 Off
Enable clock for treble and bass
- - - - - 0 - - On
1 Off
Enable clock for loudness and middle
- - - - 0 - - - On
1 Off
x x x x - - - - Not used

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Package information TDA7718N

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 22. TSSOP28 mechanical data and package dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 1.200 0.047

A1 0.050 0.150 0.002 0.006

A2 0.800 1.000 1.050 0.031 0.039 0.041

b 0.190 0.300 0.007 0.012

c 0.090 0.200 0.004 0.008

D1 9.600 9.700 9.800 0.378 0.382 0.386

E 6.200 6.400 6.600 0.244 0.252 0.260

E11 4.300 4.400 4.500 0.170 0.173 0.177

e 0.650 0.026

L 0.450 0.600 0.750 0.018 0.024 0.030

L1 1.000 0.039

k 0˚ (min.), 8˚ (max.)

aaa 0.100 0.004 TSSOP28

Note: 1. D and E1 does not include mold flash or protrusions.
Thin Shrink Small Outline Package
Mold flash or potrusions shall not exceed 0.15mm JEDEC MO-153-AC
(.006inch) per side.

0128292 B

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7 Revision history

Table 22. Document revision history

Date Revision Changes

21-Oct-2009 1 Initial release.

16-Sept-2013 2 Updated Disclaimer

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 TDA7718N

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