Calc Project

COE 718: Scientific Calculator Details
I. Project Requirements
You are asked to develop a scientific calculator using the NIOS II processor and the DE2 development board. The calculator will read in commands from the standard input and display results on the LCD display available on the board. Below is a list of the calculator basic instruction set requirement; your implementation will have to support AT LEAST these operations. You are; however, free to implement additional features for some bonus marks. These bonus marks will be allotted based on the over-all difficulty of the project. Failure to implement the basic feature set will result in marks being deducted from your project mark. Basic Feature Set

Addition, subtraction, multiplication and division of two floating point and integer operands. Memory operations: memory store, memory clear, operations where the memory unit is one of the operands and the result is stored back into memory. sin, cos, tan and log operations.
Deliverables
Your project mark will be based on the following two components: Project Report: In this document you will describe your calculator system, both hardware and software components. The report should include the system software source-code, as well as any hardware description files you may have used besides the standard ALTERA components. Project Demonstration: you will demonstrate the operation of your calculator to the lab supervisor. This means running the calculator on the DE2 hardware and answering questions about your design and implementation.
II. Calculator Hardware Components

The first part of developing the calculator will be to build the core system hardware using the SoPC Builder tool. To implement the basic calculator the following components are required:

Some form of processor (NIOS II in the current case). JTAG UART controller. SDRAM controller. LCD display driver.
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Processor and JTAG UART

You are referred to your Lab 3a documentation for information on adding the NIOS II processor and JTAG UART to your SOPC Builder project.
LCD Driver
The LCD driver is added to the project in the same way as the other components. No parameters have to be specified when the component is added. For information on how to access the LCD through the HAL, refer to the NIOS II Programmers Handbook Chapter 4. Please see section III for information on connecting the LCD wires to the system.
SDRAM Controller
Unlike Lab 3, the calculator code will not fit in the available on-chip memory, meaning an off-chip memory will have to be used. To interface to the off-chip SDRAM, an SDRAM controller will have to be added to the system. The SDRAM Tutorial posted on the course website should be used to determine the parameters of the SDRAM controller (NOTE: ignore the assembly language portions of the document). The document also describes how the SDRAM chip clock should be adjusted using an on-chip PhaseLocked Loop circuit to work with the rest of the system. NOTE: The above-mentioned document has some syntactical errors in the VHDL code it presents for the final system. The following set of commands on page 14:
BA <= (DRAM_BA_1 & DRAM_BA_0); DQM <= (DRAM_UDQM & DRAM_LDQM);
should be replaced with:

DRAM_BA_1 <= BA(1); DRAM_BA_0 <= BA(0); DRAM_UDQM <= DQM(1); DRAM_LDQM <= DQM(0);
III. Top-Level Entity Files and Pin Connections

When the SoPC Builder system is invoked to Generate the core system, it merges several HDL designs together and creates a top-level entity file for the NIOS II system. In order for this system to work, it must be connected to input and output pins, be fed input and clock signals, etc. This is accomplished by instantiating your NIOS II system in your project top-level entity file. In Lab 3 you performed this step using the graphical environment, and the NIOS II system took the form of a block diagram. For the final project, text-based VHDL instantiation will be used. The SDRAM Tutorial (mentioned above) shows examples of this process. Inside the Architecture
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declaration of your top-level entity, the NIOS II system is declared as a component. The system is then instantiated in the design using the PORT MAP command. The DE2 pin assignments are specified in the DE2_pin_assignments.csv file available in the course directory. This pin assignment file should be copied to your home directory and should be included in your project from Quartus II by using the Assignments => Import Assignments ... menu option. Once these assignments are in effect, pin names (such as DRAM_BA_1) will be reserved for use in your project, and will have an associated physical pin mapping. The NIOS II system that you generated has a set of ports for all SoPC components that connect to offchip devices; such components include the SDRAM Controller and the LCD Controller components, both of which are connected to devices external to the Cyclone II FPGA. These ports will have to be connected to the appropriate physical wires, by connecting them to the appropriate input and output ports in your top-level entity. The SDRAM Tutorial shows the proper connections for the SDRAM system. LCD Wires To appropriately connect the LCD to the NIOS II System, you must refer to the DE2 schematics file, see what wires are used by the LCD controller, declare them as input or output ports in your project top-level entity file, and appropriately connect them to the NIOS II System ports, or to constant values, depending on the wire's function.
IV. System Software

Once the system hardware has been created, you can begin work on the software aspect of your project. Lab 3b introduced the basic process of writing C programs for NIOS II based systems. For more detailed information on the NIOS II HAL and the available features, NIOS II Programmers Handbook should be consulted; Chapter 4 outlines the support offered for basic program design.
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COE 718: Scientific Calculator Details

II. Calculator Hardware Components

Processor and JTAG UART

should be replaced with:

III. Top-Level Entity Files and Pin Connections

IV. System Software

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