Lecture (2) | MIPS

Created @October 16, 2024 6:46 AM

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1. Chapter Goals
Objectives:

Introduce the MIPS assembly language and its instruction set.

Illustrate basic instruction set design principles.

Explain the relationship between high-level languages (HLL) and assembly.

Compare CISC (Complex Instruction Set Computer) and RISC (Reduced

Instruction Set Computer).

Key Focus Areas:

Understanding the simplicity of MIPS architecture for easier hardware

implementation.

Demonstrating how instruction sets influence system performance, design

costs, and power consumption.

2. Introduction to Instructions
Definition:

Instructions are commands that tell a computer what operations to

perform.

The instruction set is the complete list of commands that a computer can
execute.

MIPS Architecture:

A type of RISC architecture known for its simplicity and uniformity.

Widely used in various systems like game consoles (e.g., Nintendo),

network devices (e.g., Cisco routers), and embedded systems.

Lecture (2) | MIPS 1

 Goals of Instruction Set Design:

Maximize performance by making common tasks fast.

Minimize hardware complexity and power usage through simpler

instructions.

Reduce design time by making instructions straightforward to implement.

3. Operations in MIPS Assembly Language

Arithmetic Instructions:

Format: operation destination, source1, source2 .

Example: add $t0, $t1, $t2 adds the values in $t1 and $t2 and stores the
result in $t0 .

If $t1 = 5 and $t2 = 3 , then after executing add $t0, $t1, $t2 , $t0 will
be 8 .

Comments:

Comments follow the # symbol to explain the purpose of an instruction.

Example: add $t0, $t1, $t2 # Adds $t1 and $t2, stores the result in $t0 .

Design Principle 1: Simplicity Favors Regularity:

Having a fixed number of operands (three) and a uniform format simplifies

the hardware design.

Example: In contrast, some architectures allow for a variable number of

operands, which can complicate the instruction decoding.

4. Operands
Registers in MIPS:

MIPS uses 32 general-purpose registers ( $0 to $31 ), each 32 bits wide.

Register Naming Conventions:

$zero : Always holds the value 0 .

$v0-$v1 : For return values from functions.

Lecture (2) | MIPS 2

 $a0-$a3 : Used for function arguments.

$t0-$t9 : Temporary registers for intermediate calculations.

$s0-$s7 : Saved registers that preserve values across function calls.

Example:

To add two numbers stored in registers: add $s0, $t1, $t2 adds the values
in $t1 and $t2 and stores the result in $s0 .

Word Size and Data Types:

Each MIPS register holds a 32-bit word (4 bytes), making it a 32-bit

architecture.

Design Principle 2: Smaller is Faster:

Having fewer registers can speed up access time. For example, with 32
registers, the design is simpler than architectures with more registers,
such as 64 or 128.

5. Memory Organization
Linear Addressing:

Memory is viewed as a linear array, where each element is a byte and

each byte has a unique address starting from 0.

Byte Addressing:

Each memory address points to a single byte. To access a 32-bit word, the
address must be a multiple of 4 (word alignment).

Example:

If you want to access the third word (starting at byte 8), its address must
be 8, 12, 16, etc.

Endianness:

Big-Endian (MIPS): Stores the most significant byte at the lowest address.

Example: The number 0x12345678 is stored as 12 34 56 78 .

Lecture (2) | MIPS 3

 Little-Endian (used in x86): Stores the least significant byte at the lowest
address.

Example: 0x12345678 is stored as 78 56 34 12 .

6. Data Transfer Instructions

Load/Store Instructions:

lw (load word): Transfers data from memory to a register.

Example: lw $t0, 4($s1) loads the word from the address at $s1 + 4 into
$t0 .

sw (store word): Transfers data from a register to memory.

Example: sw $t0, 8($s1) stores the value in $t0 to the address at $s1 +

8.

Load/Store Architecture:

MIPS only accesses memory through load and store instructions; all
arithmetic is performed on data in registers.

Base and Offset Addressing:

The base register holds the starting address, and the offset specifies the
distance from that base.

Example: To access the 5th element of an integer array starting at

address in $s3 , use lw $t0, 16($s3) (5th element × 4 bytes).

7. Handling Small Constants

Immediate Instructions:

Allows operations with small constants directly in instructions.

Example: addi $t1, $t2, 10 adds 10 to the value in $t2 and stores the result
in $t1 .

If $t2 = 15 , then $t1 = 25 after execution.

Sign Extension:

Lecture (2) | MIPS 4

 Extends a 16-bit immediate value to 32-bit by copying the sign bit into the
higher bits.

Example: A 16-bit value of 0xFFFE (in two's complement) becomes

0xFFFFFFFE when sign-extended to 32-bit.

Design Principle 3: Make the Common Case Fast:

Small constants are common, and handling them efficiently speeds up

common operations.

8. Logical (Bitwise) Instructions

Common Operations:

AND ( and $t0, $t1, $t2 ): Performs a bitwise AND on $t1 and $t2 , storing
the result in $t0 .

OR ( or $t0, $t1, $t2 ): Performs a bitwise OR.

NOR ( nor $t0, $t1, $t2 ): Performs a bitwise NOR (NOT OR).

Shift Operations:

Shift Left Logical ( sll $t0, $t1, 4 ): Shifts $t1 left by 4 bits, filling with
zeroes.

Shift Right Logical ( srl $t0, $t1, 4 ): Shifts $t1 right by 4 bits, filling
with zeroes.

Shift Right Arithmetic ( sra $t0, $t1, 4 ): Shifts right, filling with the sign
bit.

Example:

To clear the least significant 4 bits of a register, use andi $t0, $t1, 0xFFF0 .

9. Instruction Formats
Types of Formats:

R-Format: For arithmetic/logic instructions.

Example: add $t0, $t1, $t2 (register-based).

I-Format: For immediate and data transfer instructions.

Lecture (2) | MIPS 5

 Example: addi $t0, $t1, 10 (uses a 16-bit immediate).

J-Format: For jump instructions.

Example: j 10000 (jump to the address).

Fields in Each Format:

R-Format Fields:

op : Opcode (6 bits).

rs , rt , rd : Registers (5 bits each).

shamt : Shift amount (5 bits).

funct : Specific operation (6 bits).

Design Principle 4: Good Design Demands Good Compromises:

Different formats allow efficient encoding and flexibility while keeping the
instruction length fixed.

10. Decision-Making Instructions

Conditional Branches:

beq $t0, $t1, Label : Branches to Label if $t0 equals $t1 .

bne $t0, $t1, Label : Branches if they are not equal.

Unconditional Branches:

j Label : Jumps directly to Label .

jr $ra : Jumps to the address stored in $ra .

Basic Blocks:

A sequence of instructions without branches except possibly at the end.

Essential

Lecture (2) | MIPS 6