shreeranjani22@gmail.com 9538418650 Enthusiastic and self-motivated FPGA designer with 6+ years of experience. Eager to join your organization and bring my skills in frontend development. A previous project for redesigning helped in receiving the project for the company.
Career Synopsis Have 6+ years of experience as FPGA design, Coding, and Integration, debugging with excellent exposure to FPGA device. Worked on micro architecture for OFDM 5G Gnode. Expertise in Digital Logic Design and FPGA/RTL design flow implement and verify RTL modules using standard FPGA synthesis and simulation tools. Experience of using real time debugging tools like Xilinx chip scope, ILA in system level. Solid Understanding of the Design and Document the modules as per the standards Knowledge on UVM methodology Hands on experience in writing Test benches for module level and Top level of the design Close Collaboration with peers in FPGA Design using Agile development methodology. High speed digital design knowledge. Good at mentoring Juniors
Technical Skills Programming Language: Verilog, VHDL and System Verilog. Basic C, Python. Tools: MATLAB, Simulink [version 2018a,2021a]. Synthesis: Xilinx, Vivado, Altera, Lattice Diamond. Simulator: ModelSim, QuestaSim, and Xilinx Vivado. Debugging and Testing: Chip scope, ILA, VSA, Oscilloscope, Probing.
Education High School - 89.12% 2011
VTU Belagavi – 75% 2017
Bachelor of Engineering, Electronics and Communication Language Kannada English Telugu Tamil
Working on platform emulation for Base Pre Silicon activity. Currently Testing the SOC for functionality and IO. Knowledge on debugging the SOC emulation.
LTTS | Senior design engineer Lead | HOLOGIC
Analyze the design for modification of the design.
Communicated and worked with other team members to gather modification requirements to sustain existing Client products. Need for change of Obsolete device for required devices. Prepare analyzes report for the same. Verify the test results to check the modified design works as earlier.
Capgemini Engineering | Senior design engineer | OFDM MODEM OCT 2022- Aug 2023 Design of Testbench modules for Validation of 5G flex projects. Verification of OFDM modulator and Demodulator. Integration of SYSGEN generated netlist with hardened FFT IP core on Vivado Platform. Understand the Design and Document the modules. SYSGEN based testbench module development for PRACH demodulator. PRACH demodulator simulation and analysis Port Map of AGC Interface logic in Verilog.
Capgemini Engineering | Senior design engineer | JTAG SWITCHER NOV 2021 - Mar 2022 Worked together with the Hardware and Software teams to deliver the project on time. Implementing the design in Verilog/VHDL per design specification. Synthesized, implemented, and constrained the design. Validated the design on Custom Board. Bharat Electronics Limited | Project engineer | PORTABLE CHECKOUT SYSTEM Mar 2021- Oct 2021
Micro Architecture and documentation of RTL design.
Implement Modem BPSK on SYSGEN. GUI developed using C on visual studio. Software document was implemented for PCS as per RCI requirement. Implement the configuration of ADC modules using SPI interface. Synthesized and implemented the design on Zedboard.
Bharat Electronics Limited | Project engineer | DNR RADIO Oct 2020 - feb 2022
Communicated and worked with other team members to gather modification requirements to sustain existing Client products. Involved in development of RTL design, integration with different clock domains. DNR execution and IO waveform analyzation for Physical Validation of DUT through Logic analyzer, for functional and timing. Documented the design.
Centum Electronics Limited | Design engineer | Controller Interface Mar 2019- Sep 2020
Understanding the input parameters to structure the control signals given to other systems. Establish interface for monitoring temperature of ADC and FPGA using I2C protocol Health diagnostics of subsystems is sent via 1553 Bus protocol Development of Chirp waveform to generate an RF signal at 1.25Ghz. Develop RF enables to control RF system. Design, RTL development, integration, implementation of above-mentioned modules. Support development of unit level, system level test benches, for functional verification. Board level debug using Chip scope analyzer and oscilloscope.
Centum Electronics Limited | Design engineer | FFFE Protocol Oct 2020 - feb 2022 Understanding Design architecture given in flow chart format. Simulate and debug using Xilinx tool. Document the design for customer reference.
Centum Electronics Limited | Design engineer | QDR CONTROLLER DEC 2017 - Feb 2019 Understanding the input parameters to structure the control signals given to other systems. Working on Microarchitecture level for different types of controller card. Document the design for customer reference. Testing done in ISAC ISRO for its functionality check. Some of the tests includes Thermovacc and Vibration Assisted the data acquisition team in capturing the waveforms, interpret the correct results. Board level testing done for controller card.
