Design and FPGA Implementation of Vending Machine

A six week industrial training report submitted in the partial fulfillment

of the requirement for the award of degree of
Bachelor of Technology (Computer Science & Engineering)

(Session: 2017-2021)

Submitted to: Submitted by:

Dr. Deepak Sood Nishant Sharma
ECE Department 251701025
UIET, KUK ECE-A

University Institute of Engineering and Technology

Kurukshetra University, Kurukshetra – 136119
PROJECT REPORT

ON
 VLSI Design and FPGA Implementation

Prepared And Submitted By:

NISHANT SHARMA (UIET KUK)

Summer Training At Centre for Development of Advanced

Computing(C-DAC)mohali
(Training Period: 3 June 2019 to 12 July 2019)

Guided By: Ms. Vemu Sulochana

 Declaration

This is to certify that Report entitled “Design and FPGA Implementation of Vending Machine”
submitted by us in partial fulfillment of the requirement for the Summer training in VLSI Design,
C-DAC, Mohali under the supervision of Ms. Vemu Sulochana , Project Engineer , ACSD
comprises only our original work and due acknowledgement has been made in the text to all other
material used.

Submitted by:
Nishant Sharma
 Acknowledgement

Before we get into the thick of things, we would like to add a few words of appreciation for the
people who have been a part of this project right from its inception. The writing of this project has
been one of the significant academic challenges that we have faced and without the support, patience
and guidance of the people involved, it would not have been possible to accomplish this task. It is to
them we owe our deepest gratitude.

It gives us immense pleasure in presenting the project report on “Design and FPGA
Implementation of Vending Machine”. It has been our privilege to have a project guide who has
assisted us from the commencement of the project. The success of the project is a result of sheer hard
work and determination put in by us and our Project Guide. We, hereby take this opportunity to add
a special note of thanks for Ms.Vemu Sulochana(Project Engineer) who undertook to act as our
mentor despite her many other academic commitments. Without her insight, support and energy, this
project would neither have kick-started, nor would have reached fruitfulness
 Abstract

Machine as we all know is a machine which can vend different products which is more like
an automated process with no requirement of man handling which we normally see in fast
moving cities because of fast paced life. This paper compares different aspects like area,
timing constraint, speed, power dissipation of a vending machine with 2 different design
styles algorithm while installation. FSM based algorithm has been utilized to simulate
model, synthesize the machine on the stratix III family of FPGA provided with quartus
design tool which is logic device design software from Altera
 Table of Contents

S. No. Content Page No.

1. Introduction 1

2. VLSI Design Flow 3

3. Design Simulation and synthesis 4

4. Introduction to FPGA : Spartan 3,3E and 6 6

5. Vending Machine Introduction and Operation 9

6. Implementation of Vending Machine 10

7. VHDL Code 11

8. Synthesis Report 20

9. Implementation on FPGA 23
 INTRODUCTION

VLSI is the field which involves packing more and more logic devices into smaller and smaller
areas. Thanks to VLSI, circuits that would have taken boardfulls of space can now be put into a
small space few millimetres across! This has opened up a big opportunity to do things that were not
possible before. VLSI circuits are everywhere ... your computer, your car, your brand new state-of
the-art digital camera, the cell-phones, and what have you. All this involves a lot of expertise on
many fronts within the same field, which we will look at in later sections

Need, Scope and use

VHDL is a language for describing digital electronic systems. It arose out of the United States
Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. VHSIC
Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by
the Institute of Electrical and Electronic Engineers (IEEE) in the US.

Need

VHDL is designed to fill a number of needs in the design process.

1) It allows description of the structure of a design that is how it is decomposed into sub-designs, and
how those sub designs are interconnected.

2) It allows the specification of the function of designs using familiar programming language forms.

3) As a result, it allows a design to be simulated before being manufactured, so that designers can
quickly compare alternatives and test for correctness without the delay and expense of hardware
prototyping.

Scope

VHDL is suited to the specification, design and description of digital electronic hardware.

System level

VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-software split.
Simulation at this level is usually stochastic, and is concerned with modeling performance,
throughput,
1
queuing and statistical distributions. VHDL has been used in this area with some success, but is best
suited to functional and not stochastic simulation.

Digital

VHDL is suitable for use today in the digital hardware design process, from specification through
high-level functional simulation, manual design and logic synthesis down to gate-level simulation.
VHDL tools usually provide an integrated design environment in this area.VHDL is not suited for
specialized implementation-level design verification tools such as analog simulation, switch level
simulation and worst case timing simulation. VHDL can be used to simulate gate level fan-out
loading effects providing coding

2
 VLSI Design Flow

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC)by combining
thousands of transistors into a single chip .The VLSI IC circuits design flow is shown in the Fig.1.
The various levels of design are numbered and the blocks show processes in the design flow.
Specifications comes first, they describe abstractly, the functionality, interface, and the architecture
of the digital IC circuit to be designed. Behavioral description is then created to analyze the design in
terms of functionality, performance, compliance to given standards, and other specifications. RTL
description is done using HDLs. This RTL description is simulated to test functionality. From here
onwards we need the help of EDA tools

3
Design Simulation and Design Synthesis

Synthesis

Is the process of translating a design description to another level of abstraction, i.e., from behavior to
structure. We achieved synthesis by using a Synthesis tool like Foundation Express which outputs a
net list. It is similar to the compilation of a high level programming language like C into assembly
code

Simulation

Simulation is the execution of a model in a software environment. During design creation/verification, a

design is captured in an RTL-level (behavioral) VHDL source file. After capturing the design, you can
perform a behavioral simulation of the VHDL file to verify that the VHDL code is correct. The code is
then synthesized into a gate-level (structural) VHDL net list. After synthesis, you can perform an
optional pre-layout structural simulation of the design. Finally, an EDIF net list is generated for use in
Designer and a VHDL structural post-layout net list is generated for timing simulation in a VHDL
simulator.

Design Creation/Verification

VHDL Source Entry

Enter your VHDL design source using a text editor or a context-sensitive HDL editor. Your VHDL
design source can contain RTL-level constructs.

Behavioral Simulation

Perform a behavioral simulation of your design before synthesis. Behavioral simulation verifies the
functionality of your VHDL code. Typically, you use zero delays and a standard VHDL test bench to
drive simulation.

Synthesis

After you have created your behavioral VHDL design source, you must synthesize it. Synthesis
transforms the behavioral VHDL file into a gate-level netlist and optimizes the design for a target
technology.
4
Simulation

Then simulator will check functionality. It means that design and code should be working according
to truth table or not. Simulation is just testing the system at software level where as real testing is at
hardware level.

5
 Introduction to FPGA : SPARTAN 3, SPARTAN 3E, SPARTAN 6

Xilinx

Xilinx Inc. is an American technology company, primarily a supplier of programmable logic

devices. It is known for inventing the field-programmable gate array (FPGA) and as the first
semiconductor company with a fabless manufacturing model.

Founded in Silicon Valley in 1984, the company is headquartered in San Jose, USA, with additional
offices in Longmont, USA; Dublin, Ireland; Singapore; Hyderabad, India; Beijing, China; Shanghai,
China; Brisbane, Australia and Tokyo, Japan.

Major FPGA product families include Virtex (high-performance), Kintex (mid-range) and Artix
(low-cost), and the retired Spartan (low-cost) series. Major computer software includes Xilinx ISE
and Vivado Design Suite.

Spartan family

The Spartan series targets low cost, high-volume applications with a low-power footprint e.g.
displays, set-top boxes, wireless routers and other applications.

The Spartan-6 family is built on a 45-nanometer [nm], 9-metal layer, dual-oxide process technology.
The Spartan-6 was marketed in 2009 as a low-cost option for automotive, wireless communications,
flat-panel display and video surveillance applications.

6
Spartan 3E FPGA Family

Spartan-3:

Introduction The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to

meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member
family offers densities ranging from 50,000 to 5,000,000 system gates. The Spartan-3 family builds
on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the
capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as
by improving clock management functions. Numerous enhancements derive from the Virtex®-II
platform technology. These Spartan-3 FPGA enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry. Because of their exceptionally low cost,
Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including
broadband access, home networking, display/projection and digital television equipment. The
Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial
cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also,
FPGA programmability permits design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.

7
 Spartan-6:

General Description

The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for
high-volume applications. The thirteen-member family delivers expanded densities ranging from
3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and
faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process
technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family
offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of
built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation
DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks,
SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express®
compatible Endpoint blocks, advanced system-level power management modes, auto-detect
configuration options, and enhanced IP security with AES and Device DNA protection. These
features provide a lowcost programmable alternative to custom ASIC products with unprecedented
ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-
oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the
programmable silicon foundation for Targeted Design Platforms that deliver integrated software and
hardware components that enable designers to focus on innovation as soon as their development
cycle begins.

8
 Introduction to Project

Vending Machines are used to dispense various products like Coffee, Snacks, and Cold Drink etc.
when money is inserted into it. Vending Machines have been in existence since 1880s. The first
commercial coin operated machine was introduced in London and England used for selling post
cards. The vending machines are more accessible and practical than the convention purchasing
method.Previous CMOS and SED based machines are more time consuming than the FPGA based
machines. The FPGA based machine is also more flexible, programmable and can be reprogrammed.
But in microcontroller based machine, if one wants to enhance the design, he has to change the
whole architecture again but in FPGA user can easily increase the number of products.

In this paper a novel approach is proposed to design a Vending Machine with auto-billing
features.The machines usually work, when some money (usually coins or paper money) is put in a
slot. Then a button needs to be pushed, or a lever pulled. If there is enough money in the machine,
the selected item will be dropped to a tray, where it can be taken out by the person making the
purchase.

Operation of Vending Machine .

I. When the user puts in money, money counter tells the control unit, the amount of money
inserted in the Vending Machine.

II. When the user presses the button to purchase the item that he wants, the control unit turns on
the motor and dispenses the product if correct amount is inserted.

III. If there is any change, machine will return it to the user.

9
 IMPLEMENTATION OF VENDING MACHINE

In this paper a state diagram is constructed for the proposed machine which can vend four products
that is Ice cream, cold drink, candies and snacks. select_product is a 2 bit vector which is used for
the selection of products available in the vending machine.money_enter i/p is used to identify the
coin entered into the vending machine.If the inserted money is more than the total money of
products then the change will be returned through the money_return
signal.ColdDrink,Candy,Snacks and Icecream are the outputs only one of them would be high at a
time and others would be low. There are also two input signal clk and reset. The machine will
work on the positive edge of clock and will return to its initial state when reset button is pressed.
The proposed vending machine is designed using FSM modelling and is coded in VHDL
language.

Table: Products with their Prices

S.no. Products Price

1. Cold drink 40

2. Snacks 20

3. Candy 10

4. Ice cream 30

1
0
 VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity project_vendingmachine is
port(select_product:in std_logic_vector(1

downto 0); rst,clk,money_enter:in std_logic;

money_return:out std_logic; clock_out:inout

std_logic;

ColdDrink,Snacks,Icecream,Candy:out std_logic);
end project_vendingmachine;

architecture Behavioral of
project_vendingmachine is type state
is(state0,colddrink_in,candy_in,snacks_in,

icecream_in,state_out,C_10,C_20,C_30,CD_10,CD_20,CD_30,CD_50,CD_40,S_10,S_20,I_10,I
_20, I_30,I_40);
signal nxt_state,pst_state:state;
signal count: integer range 0 to 99999999 :=0; //count is set in order to get clock for 2 sec

signal tmp : std_logic;

begin

clock_divider:process(clk,rst,tmp)
// design a clock divider circuit for clock
begin synchronization
if(rst='1') then
count<=0;
tmp<='0';
11
elsif(clk'event and clk='1') then
count <=count+1;
if (count = 99999999) then
tmp <= NOT tmp;
count <= 1;
end if;
end if;
clock_out <= tmp;
end process;

L1: process(clock_out,rst)
begin
if(rst='1')then
pst_state<=state0;
elsif(clock_out'event and clock_out='1')then
pst_state<=nxt_state;
end if;
end process;
L2:process(pst_state,select_product,money_enter)
begin
case pst_state is
when state0=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';

12
if(select_product="00")then
nxt_state<=colddrink_in;
elsif(select_product="01")then
nxt_state<=candy_in;
elsif(select_product="10")then
nxt_state<=snacks_in;
elsif(select_product="11")then
nxt_state<=icecream_in;
else
nxt_state<=state0;
end if;
when candy_in=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then
nxt_state<=C_10;
else
nxt_state<=C_20;
end if;
when C_10=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';

13
 money_return<='0';
if(money_enter<='0') then
nxt_state<=C_20;
else
nxt_state<=C_30;
end if;
when C_20=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='1';
money_return<='0';
nxt_state<=state0;
when C_30=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='1';
money_return<='1';
nxt_state<=state0;
when ColdDrink_in=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then

14
 nxt_state<=CD_10;
else
nxt_state<=CD_20;
end if;
when CD_10=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then
nxt_state<=Cd_20;
else
nxt_state<=Cd_30;
end if;
when CD_20=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then
Nxt_state<=cd_30;
else
nxt_state<=cd_40;
end if;
when CD_30=>

15
 ColdDrink<='1';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then
nxt_state<=Cd_40;
else
nxt_state<=CD_50;
end if;
when CD_40=>
ColdDrink<='1';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
nxt_state<=state0;
when CD_50=>
ColdDrink<='1';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='1';
nxt_state<=state0;

when snacks_in=>
ColdDrink<='0';

16
 Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then
nxt_state<=S_10;
else
nxt_state<=S_20;
end if;

when S_10=>
ColdDrink<='0';
Snacks<='1';
Icecream<='0';
candy<='0';
money_return<='0';
nxt_state<=state0;
when S_20=>
ColdDrink<='0';
Snacks<='1';
Icecream<='0';
candy<='0';
money_return<='1';
nxt_state<=state0;
when icecream_in=>
ColdDrink<='0';
Snacks<='0';

17
 Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0') then
nxt_state<=I_10;
else
nxt_state<=I_20;
end if;

when I_10=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0')then
nxt_state<=I_20;
else
nxt_state<=I_30;
end if;
when I_20=>
ColdDrink<='0';
Snacks<='0';
Icecream<='0';
candy<='0';
money_return<='0';
if(money_enter<='0')then

18
 nxt_state<=I_30;
else
nxt_state<=I_40;
end if;
when I_30=>
ColdDrink<='0';
Snacks<='0';
Icecream<='1';
candy<='0';
money_return<='0';
nxt_state<=state0;
when I_40=>
ColdDrink<='0';
Snacks<='0';
Icecream<='1';
candy<='0';
money_return<='1';
nxt_state<=state0;
when others=> null;
end case;
end process;
end Behavioral;

19
 Synthesis Report
Selected Device : 6slx45csg324-2
Slice Logic Utilization:
Number of Slice Registers: 38 out of 54576 0%
Number of Slice
LUTs: 78 out of 27288 0%
Number used as Logic: 78 out of 27288 0%

Slice Logic Distribution:

Number of LUT Flip Flop pairs used: 82
Number with an unused Flip Flop: 44 out of 82 53%
Number with an unused LUT: 4 out of 82 4%
Number of fully used LUT-FF pairs: 34 out of 82 41%
Number of unique control sets: 3

IO Utilization:
Number of IOs: 11
Number of bonded IOBs: 11 out of 218 5%
IOB Flip Flops/Latches: 5

Specific Feature Utilization:

Number of BUFG/BUFGCTRLs: 1 out of 16 6%

Timing Report:
Clock Information:
Clock Signal Clock buffer (FF name) Load
CLK BUFGP 38
clk251 BUFG 70
Asynchronous Control Signals Information:
Clock Signal Clock buffer (FF name) Load
RST IBUF 72

20
Timing Summary:
Speed Grade: -5
Minimum period: 4.942ns (Maximum Frequency: 202.329MHz)
Minimum input arrival time before clock: 2.988ns
Maximum output required time after clock: 5.255ns
Maximum combinational path delay: No path found
Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint:
Default period analysis for Clock 'clk'
Clock period: 4.942ns (frequency: 202.329MHz)
Total number of paths / destination ports: 631 / 22
Delay: 4.942ns (Levels of Logic = 21)
Source: count_1 (FF)
Destination: count_19 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: count_1 to count_19
Total 4.942ns (3.985ns logic, 0.958ns route)
(80.6% logic, 19.4% route)

Delay: 2.964ns (Levels of Logic = 2)

Source: pst_state_17 (FF)
Destination: pst_state_0 (FF)
Source Clock: tmp rising
Destination Clock: tmp rising
Total 2.964ns (2.006ns logic, 0.958ns route)
(67.7% logic, 32.3% route)
Timing constraint: Default OFFSET IN BEFORE for Clock 'tmp'

21
Total number of paths / destination ports: 22 / 18
Offset: 2.988ns (Levels of Logic = 2)
Source: money_enter (PAD)
Destination: pst_state_17 (FF)

Total 2.988ns (1.986ns logic, 1.002ns route)

(66.5% logic, 33.5% route)

Offset: 5.255ns (Levels of Logic = 2)

Source:
pst_state_18 (FF)

Destination:
money_return (PAD)

Source Clock: tmp rising

Data Path: pst_state_18 to money_return

Total
5.255ns (4.295ns logic, 0.960ns route)
(81.7% logic, 18.3% route)
22
RTL SCHEMATIC

SIMULATION

23
 IMPLEMENTATION ON FPGA SPARTAN 6

Steps to be followed:

1.Synthesize the required code

2.In implement design, open place and route and right click back annotate pin locations.

3.Click process properties and create a ucf file.

4.Run implement design.

5.Then run “Generate programming file” ( a ucf will be created).

6. Open ucf File and name each of the location of the inputs and outputs.

7. Now run “Configure target device”.

8. A new window will open on then left side, there is an impact window, from there click boundary
scan and then right click on the main window and click initialize Chain the number of devices that
are allowed will be shown in a diagram .

24
10.Right click on the diagram and click program the machine language programming begins and is
executed.

25