Department of ECE

23EC2106R
PROCESSORS AND CONTROLLERS
CO - 4 & Part – 2

PIC & ARM MICROCONTROLLER

 ARM PROCESSORS: Operating Modes

• Seven operating modes:

– User (Non-Privileged): Only allows read access to the control field in CPSR

– Privileged: Allow full read and write access of CPSR

• System (version 4 and above)
• FIQ (Fast interrupt request queue)
• IRQ (interrupt request queue)
• Abort exception modes
• Undefined
• Supervisor
 ARM PROCESSORS: Operating Modes

➢ Differences between User & Exception modes:

User mode Exception mode

– Normal program execution mode – Entered upon exception

– System resources unavailable – Full access to system resources
– Mode changed by exception only – Mode changed freely
 ARM PROCESSORS: Operating Modes

The ARM has seven basic operating modes:

– User: unprivileged mode under which most tasks run
– System: privileged mode using the same registers as user mode
– FIQ: entered when a high priority (fast) interrupt is raised
– IRQ: entered when a low priority (normal) interrupt is raised
– Supervisor: entered on reset and when a Software Interrupt
instruction is executed
– Abort: used to handle memory access violations
– Undefined: used to handle undefined instructions
 ARM PROCESSORS: Operating Modes
➢ Register Model: System (sys) & User (usr) operating mode
System & User
R0
• These both operating modes has similar register R1
organization. R2
R3
• These both operating modes has 16 general R4
R5
purpose data registers (R0 to R15). R6
R7
• The R15 register acts as a Program Counter (PC) in R8
these operating modes. R9
R10
R11
• These both operating modes has one current
R12
processor status register (CPSR). R13
R14
R15 (PC)
CPSR
 ARM PROCESSORS: Operating Modes
➢ Register Model: Supervisor (svc) operating mode
Supervisor
R0
• This operating mode has 16 general purpose data R1
registers (R0 to R15). R2
R3
• The R15 register acts as a Program Counter (PC) in R4
R5
this operating mode.
R6
R7
• This operating mode has one current processor R8
status register (CPSR). R9
R10
R11
• This operating mode also has one saved processor R12
status register (SPSR). R13_svc
R14_svc
R15 (PC)
CPSR
SPSR_svc
 ARM PROCESSORS: Operating Modes
➢ Register Model: Abort (abt) operating mode
Abort
R0
• This operating mode has 16 general purpose data R1
registers (R0 to R15). R2
R3
R4
• The R15 register acts as a Program Counter (PC) in R5
this operating mode. R6
R7
• This operating mode has one current processor R8
R9
status register (CPSR).
R10
R11
• This operating mode also has one saved processor R12
status register (SPSR). R13_abt
R14_abt
R15 (PC)
CPSR
SPSR_abt
 ARM PROCESSORS: Operating Modes
➢ Register Model: Undefined (und) operating mode
Undefined
R0
• This operating mode has 16 general purpose data R1
registers (R0 to R15). R2
R3
R4
• The R15 register acts as a Program Counter (PC) in R5
this operating mode. R6
R7
• This operating mode has one current processor R8
R9
status register (CPSR).
R10
R11
• This operating mode also has one saved processor R12
status register (SPSR). R13_und
R14_und
R15 (PC)
CPSR
SPSR_und
 ARM PROCESSORS: Operating Modes
➢ Register Model: IRQ operating mode
IRQ
R0
• This operating mode has 16 general purpose data R1
R2
registers (R0 to R15).
R3
R4
• The R15 register acts as a Program Counter (PC) in R5
this operating mode. R6
R7
• This operating mode has one current processor R8
R9
status register (CPSR).
R10
R11
• This operating mode also has one saved processor R12
status register (SPSR). R13_irq
R14_irq
R15 (PC)
CPSR
SPSR_irq
 ARM PROCESSORS: Operating Modes
➢ Register Model: FIQ operating mode
FIQ
R0
• This operating mode has 16 general purpose data R1
R2
registers (R0 to R15).
R3
R4
• The R15 register acts as a Program Counter (PC) in R5
this operating mode. R6
R7_fiq
• This operating mode has one current processor R8_fiq
R9_fiq
status register (CPSR).
R10_fiq
R11_fiq
• This operating mode also has one saved processor R12_fiq
status register (SPSR). R13_fiq
R14_fiq
R15 (PC)
CPSR
SPSR_fiq
 ARM PROCESSORS: Operating Modes
➢ Register Model or Programmer’s Model
System & User Supervisor Abort Undefined IRQ FIQ
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7 R7 R7 R7 R7_fiq
R8 R8 R8 R8 R8 R8_fiq
R9 R9 R9 R9 R9 R9_fiq
R10 R10 R10 R10 R10 R10_fiq
R11 R11 R11 R11 R11 R11_fiq
R12 R12 R12 R12 R12 R12_fiq
R13 R13_svc R13_abt R13_und R13_irq R13_fiq
R14 R14_svc R14_abt R14_und R14_irq R14_fiq
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR
SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq
 ARM PROCESSORS: Registers
• 31 general-purpose 32-bit registers
• 16 Data registers (R0-R15) & one status register (CPSR)
• Others speed up the exception process
• R0 to R13 are orthogonal general-purpose register.
• Orthogonal means, any instruction that you can apply to r0 can equally
be applied to any of the other register.
Eg. ADD r0, r1, r2
ADD r5, r6, r7
• R13 (stack pointer) and stores the top of the stack in the current
processor mode.
• R14(LR) Link Register where the core puts the return address on
executing a subroutine.
• R15(PC) Program counter stores the address of next instruction to be
executed.
• In ARM state all ARM instruction are 32-bit wide.
• In Thumb state all instructions are 16-bit wide.
 ARM PROCESSORS: Registers
➢ Current Processor Status Register (CPSR)
• ARM core uses CPSR to monitor & control internal operations.
 ARM PROCESSORS: Registers
➢ Current Processor Status Register (CPSR)

• CPSR fields is divided in to four fields, each 8-bits wide: flags, status,
extension, and control.

• In some ARM processor cores have extra bits allocated J bit (available
only on Jazelle enabled processing which execute 8-bit instructions).
 ARM PROCESSORS: Registers
➢ Current Processor Status Register (CPSR)
Flag bit Sets when

In case of signed no. operations If result

N- Negative
MSB=1 ;Indicates the result of operation is NEGATIVE

Z- Zero The result of operation is zero

C- Carry The result causes an unsigned carry(carry out of MSB)
V-Overflow The result causes a signed overflow

I- Interrupt request Disable If set interrupt request channel is disabled

F- Fast interrupt request Disable If set fast interrupt request channel is disabled

T-Thumb instruction set If set processor will execute Thumb Instruction set

J- Jazelle instruction set If set processor will execute Jazelle instructions

 ARM PROCESSORS: Registers
➢ Current Processor Status Register (CPSR)
• Processor Operating Modes:
 ARM PROCESSORS: Exceptions
➢ Exceptions of ARM processor
• Exception types, sorted by Interrupt Vector addresses
 ARM PROCESSORS: Instruction Set
• ARM instruction set is classified into following categories.

ARM instruction
1. Data processing instructions set

2. Data transfer instructions

Data
Data transfer
processing
instructions
3. Block transfer instructions instructions

4. Branching instructions Block transfer Branching

instructions instructions
5. Multiply instructions
Software
Multiply
6. Software interrupt instructions instructions
interrupt
instructions
 ARM PROCESSORS: Instruction Set

➢ Differences between ARM & THUMB modes:

 ARM PROCESSORS

➢ Question Bank:
• ARM – PROCESSOR OPERATING MODES
• ARM7 Programmer’s Model or Register Model
• ARM –REGISTERS
• CURRENT PROCESSOR STATUS REGISTER (CPSR)
• ARM vs THUMB MODE
THANK YOU

N L PRASAD