MODULE 4 - THE MEMORY SYSTEM

COMPUTER
ORGANIZATION
AND
ARCHITECTURE

Module 4
THE MEMORY SYSTEM

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Some Basic Concepts

● The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
● For example, a 16-bit computer that generates 16-bit addresses is capable of
addressing up to 216 = 64K memory locations.
● Similarly, machines whose instructions generate 32-bit addresses can utilize
a memory that contains up to 232 =4G (giga) memory locations, whereas
machines with 40-bit addresses can access up to 240 =1T (tera) locations.
● The number of locations represents the size of the address space of the
computer. Most modem computers are byte addressable.
● Data transfer between the memory and the processor takes place through the
use of two processor registers, usually called MAR (memory address register)
and MDR (memory data register).
● If MAR is k bits long and MDR is n bits long, then the memory unit may
contain up to 2k addressable locations.
● During a memory cycle, n bits of data are transferred between the memory
and the processor.
● This transfer takes place over the processor bus, which has k address lines
and n data lines.
● The bus also includes the control lines Read/Write̅̅̅̅̅̅̅̅ (R/𝑊
̅ ) and Memory
Function Completed (MFC) for coordinating data transfers. Other control lines
may be added to indicate the number of bytes to be transferred.
● The connection between the processor and the memory is shown
schematically in Figure 5.1.

• The

processor reads data from the memory by loading the address of the required
memory location into the MAR register and setting the R/𝑊 ̅ line to 1.
• The memory responds by placing the data from the addressed location onto
the data lines, and confirms this action by asserting the MFC signal.

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• Upon receipt of the MFC signal, the processor loads the data on the data lines
into the MDR register.
• The processor writes data into a memory location by loading the address of
this location into MAR and loading the data into MDR.
• ̅ line to 0.
It indicates that a write operation is involved by setting the R/𝑊
• If read or write operations involve consecutive address locations in the main
memory, then a "block transfer" operation can be performed in which the only
address sent to the memory is the one that identifies the first location.
• Memory accesses may be synchronized using a clock, or they may be
controlled using special signals that control transfers on the bus, using the
bus signaling schemes.
• Memory read and write operations are controlled as input and output bus
transfers, respectively.

● Memory Access Time: the time that elapses between the initiation of an
operation and the completion of that operation.
● For example, the time between the Read and the MFC signals.
● Memory Cycle Time: which is the minimum time delay required between the
initiation of two successive memory operations.
● For example, the time between two successive Read operations.
● Random Access Memory (RAM): A memory unit is called random-access
memory (RAM) if any location can be accessed for a Read or Write operation
in some fixed amount of time that is independent of the location's address.
● The basic technology for implementing the memory uses semiconductor
integrated circuits.
● The processor of a computer can usually process instructions and data faster
than they can be fetched from a reasonably priced memory unit.
● The memory cycle time, then, is the bottleneck in the system.
● One way to reduce the memory access time is to use a cache memory.
● This is a small, fast memory that is inserted between the larger, slower main
memory and the processor.
● It holds the currently active segments of a program and their data.
● Virtual memory is another important concept related to memory organization.
● Data may be stored in physical memory locations that have addresses
different from those specified by the program.
● The memory control circuitry translates the address specified by the program
into an address that can be used to access the physical memory.
● In such a case, an address generated by the processor is referred to as a
virtual or logical address.
● The virtual address space is mapped onto the physical memory where data
are actually stored.

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● The mapping function is implemented by a special memory control circuit,

often called the memory management unit.
● This mapping function can be changed during program execution according
to system requirements.

Semiconductor RAM Memories

• Semiconductor memories are available in a wide range of speeds. Their cycle
times range from 100 ns to less than 10 ns.

Internal Organization of Memory Chips

• Memory cells are usually organized in the form of an array, in which each
cell is capable of storing one bit of information. A possible organization is
illustrated in Figure 5.2.
• Each row of cells constitutes a memory word, and all cells of a row are
connected to a common line referred to as the word line, which is driven by
the address decoder on the chip.
• The cells in each column are connected to a Sense/Write circuit by two bit
lines.
• The Sense/Write circuits are connected to the data input/output lines of
the chip.

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• During a Read operation, these circuits sense, or read, the information

stored in the cells selected by a word line and transmit this information to
the output data lines.
• During a Write operation, the Sense/Write circuits receive input
information and store it in the cells of the selected word.
• Figure 5.2 is an example of a very small memory chip consisting of 16 words
of 8 bits each. This is referred to as a 16 x 8 organization.
• The data input and the data output of each Sense/Write circuit are
connected to a single bidirectional data line that can be connected to the
data bus of a computer.
• Two control lines, R/𝑊 ̅ and CS, are provided in addition to address and data
lines.
• The R/𝑊 ̅ (Read/𝑊𝑟𝑖𝑡𝑒
̅̅̅̅̅̅̅̅) input specifies the required operation, and the CS
(Chip Select) input selects a given chip in a multichip memory system.
• The memory circuit in Figure 5.2 stores 128 bits and requires 14 external
connections for address, data, and control lines.
• Of course, it also needs two lines for power supply and ground connections.
• Consider now a slightly larger memory circuit, one that has 1K (1024)
memory cells. This circuit can be organized as a 128 x 8 memory, requiring
a total of 19 external connections.
• Alternatively, the same number of cells can be organized into a 1K x I
format. In this case, a 10-bit address is needed, but there is only one data
line, resulting in 15 external connections.
• Figure 5.3 shows such an organization.

• The required 10-bit address is divided into two groups of 5 bits each to form
the row and column addresses for the cell array.

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• A row address selects a row of 32 cells, all of which are accessed in parallel.
• However, according to the column address, only one of these cells is
connected to the external data line by the output multiplexer and input
demultiplexer.
• Commercially available memory chips contain a much larger number of
memory cells than the examples shown in Figures 5.2 and 5.3.
• For example, a 4M-bit chip may have a 512K x 8 organization, in which
case 19 address and 8 data input/output pins are needed.

Static Memories

• Memories that consist of circuits capable of retaining their state as long as

power is applied are known as static memories.
• Figure 5.4 illustrates how a static RAM (SRAM) cell may be implemented.
• Two inverters are cross-connected to form a latch.
• The latch is connected to two bit lines by transistors T1 and T2.
• These transistors act as switches that can be opened or closed under
control of the word line.
• When the word line is at ground level, the transistors are tamed off and the
latch retains its state.
• For example, let us assume that the cell is in state 1 if the logic value at
point X is 1 and at point Y is 0.

• This state is maintained as long as the signal on the word line is at ground
level.

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Read Operation
• In order to read the state of the SRAM cell, the word line is activated to
close switches T1 and T2.
• If the cell is in state 1, the signal on bit line b is high and the signal on
bit line b' is low.
• The opposite is true if the cell is in state 0. Thus, b and b' are
complements of each other.
• Sense/Write circuits at the end of the bit lines monitor the state of b
and b' and set the output accordingly.

Write Operation
• The state of the cell is set by placing the appropriate value on bit line b
and its complement on b', and then activating the word line.
• This forces the cell into the corresponding state.
• The required signals on the bit lines are generated by the Sense/Write
circuit.

CMOS Cell

• CMOS realization of the cell in Figure 5.4 is given in Figure 5.5.

• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch.
• The state of the cell is read or written as just explained.

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• For example, in state 1, the voltage at point X is maintained high by

having transistors T3 and T6 on, while T4 and T5 are off.
• Thus if T1 and T2 are turned on (closed), bit lines b and b' will have
high and low signals, respectively.
• The power supply voltage, V supply, is 5 V in older CMOS SRAMs or 3.3
V in new low-voltage versions.
• Note that continuous power is needed for the cell to retain its state.
• If power is interrupted, the cell's contents will be lost.
• When power is restored, the latch will settle into a stable state, but it
will not necessarily be the same state the cell was in before the
interruption.
• Hence, SRAMs are said to be volatile memories because their contents
are lost when power is interrupted.
• A major advantage of CMOS SRAMs is their very low power
consumption because current flows in the cell only when the cell is
being accessed.
• Otherwise, T1, T2, and one transistor in each inverter are turned off,
ensuring that there is no active path between Vsupply and ground.
• Static RAMs can be accessed very quickly. Access times of just a few
nanoseconds are found in commercially available chips.
• SRAMs are used in applications where speed is of critical concern.

Asynchronous DRAMs
• Static RAMs are fast, but they come at a high cost because their cells
require several transistors.
• Less expensive RAMs can be implemented if simpler cells are used.
• How-ever, such cells do not retain their state indefinitely; hence, they
are called dynamic RAMs (DRAMs).
• Information is stored in a dynamic memory cell in the form of a charge
on a capacitor, and this charge can be maintained for only tens of
milliseconds.
• Since the cell is required to store information for a much longer time,
its contents must be periodically refreshed by restoring the capacitor
charge to its full value.

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An example of a dynamic memory cell that consists of a capacitor, C,

and a transistor, T, is shown in Figure 5.6.
• In order to store information in this cell, transistor T is turned on and an
appropriate voltage is applied to the bit line.
• This causes a known amount of charge to be stored in the capacitor.
• After the transistor is turned off, the capacitor begins to discharge.
• This is caused by the capacitor's own leakage resistance and by the fact
that the transistor continues to conduct a tiny amount of current,
measured in pico amperes, after it is turned off.
• Hence, the information stored in the cell can be retrieved correctly only if it
is read before the charge on the capacitor drops below some threshold
value.
• During a Read operation, the transistor in a selected cell is turned on. A
sense amplifier connected to the bit line detects whether the charge stored
on the capacitor is above the threshold value.
• If so, it drives the bit line to a full voltage that represents logic value 1.
• This voltage recharges the capacitor to the full charge that corresponds to
logic value 1.
• If the sense amplifier detects that the charge on the capacitor is below the
threshold value, it pulls the bit line to ground level, which ensures that the
capacitor will have no charge, representing logic value 0.
• Thus, reading the contents of the cell automatically refreshes its contents.
• All cells in a selected row are read at the same time, which refreshes the
contents of the entire row.

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• A 16-megabit DRAM chip, configured as 2M x 8, is shown in Figure 5.7.

• The cells are organized in the form of a 4K x 4K array.
• The 4096 cells in each row are divided into 512 groups of 8, so that a row
can store 512 bytes of data.
• Therefore, 12 address bits are needed to select a row.
• Another 9 bits are needed to specify a group of 8 bits in the selected row.
• Thus, a 21-bit address is needed to access a byte in this memory.
• The high-order 12 bits and the low-order 9 bits of the address constitute
the row and column addresses of a byte, respectively.
• To reduce the number of pins needed for external connections, the row and
column addresses are multiplexed on 12 pins.
• During a Read or a Write operation, the row address is applied first.
• It is loaded into the row address latch in response to a signal pulse on the
Row Address Strobe (RAS) input of the chip.
• Then a Read operation is initiated, in which all cells on the selected row are
read and refreshed.
• Shortly after the row address is loaded, the column address is applied to
the address pins and loaded into the column address latch under control
of the Column Address Strobe (CAS) signal.
• The information in this latch is decoded and the appropriate group of 8
Sense/Write circuits are selected.
• If the R/W control signal indicates a Read operation, the output values of
the selected circuits are transferred to the data lines, D7-0.
• For a Write operation, the information on the D7-0 lines is transferred to the
selected circuits.

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• This information is then used to overwrite the contents of the selected cells
in the corresponding 8 columns.
• We should note that in commercial DRAM chips, the RAS and CAS control
signals are active low so that they cause the latching of addresses when
they change from high to low.
• To indicate this fact, these signals are shown on diagrams as ̅̅̅̅̅̅
𝑅𝐴𝑆 and ̅̅̅̅̅
𝐶𝐴𝑆.
• Applying a row address causes all cells on the corresponding row to be read
and refreshed during both Read and Write operations.
• To ensure that the contents of a DRAM are maintained, each row of cells
must be accessed periodically.
• A refresh circuit usually performs this function automatically.
• Many dynamic memory chips incorporate a refresh facility within the chips
themselves.
• In this case, the dynamic nature of these memory chips is almost invisible
to the user.
• In the DRAM described in this section, the timing of the memory device is
con-trolled asynchronously.
• A specialized memory controller circuit provides the necessary control
signals, RAS and CAS, that govern the timing.
• The processor must take into account the delay in the response of the
memory.
• Such memories are referred to as asynchronous DRAMs.
• Because of their high density and low cost, DRAMs are widely used in the
memory units of computers.
• Available chips range in size from 1M to 256M bits, and even larger chips
are being developed.
• To reduce the number of memory chips needed in a given computer, a
DRAM chip is organized to read or write a number of bits in parallel, as
indicated in Figure 5.7.
• To provide flexibility in designing memory systems, these chips are
manufactured in different organizations. For example, a 64-Mbit chip may
be organized as 16M x 4, 8M x 8, or 4M x 16.

Fast Page Mode

• When the DRAM in Figure 5.7 is accessed, the contents of all 4096 cells in
the selected row are sensed, but only 8 bits are placed on the data lines D7-
0.
• This byte is selected by the column address bits A8-0.
• A simple modification can make it possible to access the other bytes in the
same row without having to reselect the row.
• A latch can be added at the output of the sense amplifier in each column.

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• The application of a row address will load the latches corresponding to all
bits in the selected row.
• Then, it is only necessary to apply different column addresses to place the
different bytes on the data lines.
• The most useful arrangement is to transfer the bytes in sequential order,
which is achieved by applying a consecutive sequence of column addresses
under the control of successive CAS signals.
• This scheme allows transferring a block of data at a much faster rate than
can be achieved for transfers involving random addresses.
• The block transfer capability is referred to as the fast page mode feature.
• The faster rate attainable in block transfers can be exploited in applications
in which memory accesses follow regular patterns, such as in graphics
terminals.
• This feature is also beneficial in general-purpose computers for transferring
data blocks between the main memory and a cache.

Read Only Memories

1. ROM

• Figure 5.12 shows a possible configuration for a ROM cell.

• A logic value 0 is stored in the cell if the transistor is connected to
ground at point P; otherwise, a 1 is stored.
• The bit line is connected through a resistor to the power supply.
• To read the state of the cell, the word line is activated.

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• Thus, the transistor switch is closed and the voltage on the bit line
drops to near zero if there is a connection between the transistor
and ground.
• If there is no connection to ground, the bit line remains at the high
voltage, indicating a 1.
• A sense circuit at the end of the bit line generates the proper output
value.
• Data are written into a ROM when it is manufactured.

2. PROM
• Some ROM designs allow the data to be loaded by the user, thus
providing a programmable ROM (PROM).
• Programmability is achieved by inserting a fuse at point P in Figure
5.12. Before it is programmed, the memory contains all 0s.
• The user can insert 1s at the required locations by burning out the
fuses at these locations using high-current pulses.
• Of course, this process is irreversible. PROMs provide flexibility and
convenience not available with ROMs.
• The latter are economically attractive for storing fixed programs and
data when high volumes of ROMs are produced.
• However, the cost of preparing the masks needed for storing a particular
information pattern in ROMs makes them very expensive when only a
small number are required.
• In this case, PROMs provide a faster and considerably less expensive
approach because they can be programmed directly by the user.

3. EPROM
• Another type of ROM chip allows the stored data to be erased and new
data to be loaded.
• Such an erasable, reprogrammable ROM is usually called an EPROM.
• It pro-vides considerable flexibility during the development phase of
digital systems.
• Since EPROMs are capable of retaining stored information for a long
time, they can be used in place of ROMs while software is being
developed.
• In this way, memory changes and updates can be easily made.
• An EPROM cell has a structure similar to the ROM cell in Figure 5.12.
• In an EPROM cell, however, the connection to ground is always made
at point P and a special transistor is used, which has the ability to

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function either as a normal transistor or as a disabled transistor that is

always turned off.
• This transistor can be programmed to behave as a permanently open
switch, by injecting charge into it that becomes trapped inside.
• Thus, an EPROM cell can be used to construct a memory in the same
way as the previously discussed ROM cell.
• The important advantage of EPROM chips is that their contents can be
erased and reprogrammed.
• Erasure requires dissipating the charges trapped in the transistors of
memory cells; this can be done by exposing the chip to ultraviolet light
• For this reason, EPROM chips are mounted in packages that have
transparent windows.

4. EEPROM
• A significant disadvantage of EPROMs is that a chip must be physically
removed from the circuit for reprogramming and that its entire contents
are erased by the ultraviolet light.
• It is possible to implement another version of erasable PROMs that can
be both programmed and erased electrically.
• Such chips, called EEPROMs, do not have to be removed for erasure.
• Moreover, it is possible to erase the cell contents selectively.
• The only disadvantage of EEPROMs is that different voltages are needed
for erasing, writing, and reading the stored data.

5. Flash Memory
• A flash cell is based on a single transistor controlled by trapped charge,
just like an EEPROM cell.
• In EEPROM it is possible to read and write the contents of a single cell.
• In a flash device it is possible to read the contents of a single cell, but
it is only possible to write an entire block of cells.
• Prior to writing, the previous contents of the block are erased.
• Flash devices have greater density, which leads to higher capacity and
a lower cost per bit.
• They require a single power supply voltage, and consume less power in
their operation.
• The low power consumption of flash memory makes it attractive for use
in portable equipment that is battery driven.

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• Typical applications include hand-held computers, cell phones, digital

cameras, and MP3 music players.
• In hand-held computers and cell phones, flash memory holds the
software needed to operate the equipment, thus obviating the need for
a disk drive.
• In digital cameras, flash memory is used to store picture image data.
• In MP3 players, flash memory stores the data that represent sound. Cell
phones, digital cameras, and MP3 players are good examples of
embedded systems.
• Single flash chips do not provide sufficient storage capacity for the
applications mentioned above.
• Larger memory modules consisting of a number of chips are needed.
• There are two popular choices for the implementation of such modules:
flash cards and flash drives.

Flash Cards
• One way of constructing a larger module is to mount flash chips on a
small card.
• Such flash cards have a standard interface that makes them usable in
a variety of products.
• A card is simply plugged into a conveniently accessible slot. Flash cards
come in a variety of memory sizes.
• Typical sizes are 8, 32, and 64 Mbytes.
• A minute of music can be stored in about 1 Mbyte of memory, using the
MP3 encoding formal. Hence, a 64-MB flash card can store an hour of
music.

Flash Drives
• Larger flash memory modules have been developed to replace hard disk
drives.
• These flash drives are designed to fully emulate the hard disks, to the
point that they can be fitted into standard disk drive bays.
• However, the storage capacity of flash drives is significantly lower.
• Currently, the capacity of flash drives is less than one gigabyte.
• In contrast, hard disks can store many gigabytes.
• The fact that flash drives are solid state electronic devices that have no
movable parts provides some important advantages.
• They have shorter seek and access times, which results in faster
response.
• They have lower power consumption, which makes them attractive for
battery driven applications, and they are also insensitive to vibration.

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• The disadvantages of flash drives versus hard disk drives are their
smaller capacity and higher cost per bit.
• Disks provide an extremely low cost per bit.
• Another disadvantage is that the flash memory will deteriorate after it
has been written a number of times. Fortunately, this number is high,
typically at least one million times.

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