COMPUTER ORGANIZATION::: SYLLABUS

MID 2 COMPUTER ORGANIZATION QUESTIONS:

1. . List the functionalities of I/O interface. Draw and explain a combined input/output interface circuit?

2 What is direct memory transfer? Give an overview and the block diagram of a DMA controller

3. Explain internal organization of memory chips

4. Analyze the memory hierarchy in terms of speed, size and Cost.

5. What are the requirements of Memory Mangement System.

6. What is Multiprocessor? Explain various methods of interconnection among two or more processor and shared
memory.(Interconnection structures for multiprocessor systems)

7. What is Parallel Processing? Explain about types of Parallel Processing.

8. What is pipelining? Explain with a example.

IMP QUESTIONS:
UNIT-I

Give an overview of the basic functional units and bus structures of a computer?

Discuss various computer types with their applications in real world environment

Give an overview of the performance measurement of computers

Discuss the Logic Gates with neat sketches.

Convert the following binary number to their equivalent decimal and hexadecimal (base 16) representation. i)
101101.0101 ii) 1010.0111 iii) 10.01

UNIT-II

b Explain various addressing modes.

Explain about sequential and combinational circuits with 2 examples from each.

Consider C=A+B, Explain different ways of writing this instruction with respect to number of addresses used.

Explain the role of stacks and queues in computer organization.

Describe the basic Instruction format. With Example.

Distinguish between fixed point representation and floating point representation with examples.
UNIT 3: THE INPUT-OUTPUT ORGANIZATION.

1. Discuss various types of interrupts.

2. . Demonstrate the mechanism of DMA with diagram.

3. . Explain in detail various I/O modes of transfer.

4. List the functionalities of I/O interface. Draw and explain a combined input/output interface circuit?

5. Explain about standard I/O interfaces.

6 Explain about I/O bus.

UNIT 4- THE MEMORY SYSTEM:

1. . Analyze the memory hierarchy in terms of speed, size and Cost.

2. Explain various mapping procedures of cache memory with an example.
3. What is virtual memory? Explain .
4. Explain various mapping procedures of cache memory with an example.
5. Explain internal organization of memory chips.

6. Explain about DRAM and SRAM.

7. Explain any two Secondary Storage devices.

UNIT 5- PARALLEL PROCESSING:

6. What is Multiprocessor? Explain various methods of interconnection among two or more processor and shared
memory.(Interconnection structures for multiprocessor systems)

7. What is Parallel Processing? Explain about types of Parallel Processing.

3. What is parallel processing? Explain How it works.

8. What is pipelining? Explain with a example.

9. What is Pipelining? Explain the advantages and disadvantages of pipelining.

NOTE: Some questions have similar answers. For clarification refer notes.
ADDITIONAL NOTES:

UNIT-4: MEMORY ORGANIZATION:

CACHE MEMORY:
Cache Mapping
There are three different types of mapping used for the purpose of cache memory which
is as follows:
 Direct Mapping
 Associative Mapping
 Set-Associative Mapping
1. Direct Mapping
The simplest technique, known as direct mapping, maps each block of main memory into
only one possible cache line. or In Direct mapping, assign each memory block to a
specific line in the cache. If a line is previously taken up by a memory block when a new
block needs to be loaded, the old block is trashed. An address space is split into two
parts index field and a tag field. The cache is used to store the tag field whereas the rest
is stored in the main memory. Direct mapping`s performance is directly proportional to
the Hit ratio.
i = j modulo m
where
i = cache line number
j = main memory block number
m = number of lines in the cache

Direct Mapping

For purposes of cache access, each main memory address can be viewed as consisting
of three fields. The least significant w bits identify a unique word or byte within a block of
main memory. In most contemporary machines, the address is at the byte level. The
remaining s bits specify one of the 2 s blocks of main memory. The cache logic interprets
these s bits as a tag of s-r bits (the most significant portion) and a line field of r bits. This
latter field identifies one of the m=2 r lines of the cache. Line offset is index bits in the
direct mapping.

Direct Mapping – Structure

2. Associative Mapping
In this type of mapping, associative memory is used to store the content and addresses
of the memory word. Any block can go into any line of the cache. This means that the
word id bits are used to identify which word in the block is needed, but the tag becomes
all of the remaining bits. This enables the placement of any word at any place in the
cache memory. It is considered to be the fastest and most flexible mapping form. In
associative mapping, the index bits are zero.
 Associative Mapping – Structure

3. Set-Associative Mapping

This form of mapping is an enhanced form of direct mapping where the drawbacks of
direct mapping are removed. Set associative addresses the problem of possible
thrashing in the direct mapping method. It does this by saying that instead of having
exactly one line that a block can map to in the cache, we will group a few lines together
creating a set . Then a block in memory can map to any one of the lines of a specific set.
Set-associative mapping allows each word that is present in the cache can have two or
more words in the main memory for the same index address. Set associative cache
mapping combines the best of direct and associative cache mapping techniques. In set
associative mapping the index bits are given by the set offset bits. In this case, the cache
consists of a number of sets, each of which consists of a number of lines.

Set-Associative Mapping
Relationships in the Set-Associative Mapping can be defined as:
m = v * k
i= j mod v

where
i = cache set number
j = main memory block number
v = number of sets
m = number of lines in the cache number of sets
k = number of lines in each set

Set-Associative Mapping – Structure

Internal Organization of Memory Chips
A memory cell is capable of storing 1-bit of information. A number of memory cells are
organized in the form of a matrix to form the memory chip.

Figure : 16 X 8 Memory Organization

Each row of cells constitutes a memory word, and all cell of a row are connected to a
common line which is referred as word line. An address decoder is used to drive the word
line. At a particular instant, one word line is enabled depending on the address present
in the address bus. The cells in each column are connected by two lines. These are
known as bit lines. These bit lines are connected to data input line and data output line
through a Sense/Write circuit. During a Read operation, the Sense/Write circuit sense, or
read the information stored in the cells selected by a word line and transmit this
information to the output data line. During a write operation, the sense/write circuit
receive information and store it in the cells of the selected word.
A memory chip consisting of 16 words of 8 bits each, usually referred to as 16 x 8
organization. The data input and data output line of each Sense/Write circuit are
connected to a single bidirectional data line in order to reduce the pin required. For 16
words, we need an address bus of size 4. In addition to address and data lines, two
control lines, and CS, are provided. The line is to used to specify the required operation
about read or write. The CS (Chip Select) line is required to select a given chip in a multi
chip memory system.

Consider a slightly larger memory unit that has 1K (1024) memory cells…
128 x 8 memory chips:If it is organised as a 128 x 8 memory chips, then it has got 128
memory words of size 8 bits. So the size of data bus is 8 bits and the size of address bus
is 7 bits (2^7=128). The storage organization of 128 x 8 memory chip is shown in the
figure 3.6.

1024 x 1 memory chips:

If it is organized as a 1024 x 1 memory chips, then it has got 1024 memory words of size
1 bit only.

Therefore, the size of data bus is 1 bit and the size of address bus is 10 bits
(2^10=1024).
A particular memory location is identified by the contents of memory address bus. A
decoder is used to decode the memory address. There are two ways of decoding of a
memory address depending upon the organization of the memory module.

In one case, each memory word is organized in a row. In this case whole memory
address bus is used together to decode the address of the specified location.

UNIT3
SYLLABUS:
Input/Output Organization: Accessing I/O devices, Interrupts,
Processor examples, Direct Memory Access(DMA) , Buses,
Interface circuits, and Standard I/O interfaces.
I/O Interface (Interrupt and DMA Mode)
The method that is used to transfer information between internal storage and external I/O
devices is known as I/O interface. The CPU is interfaced using special communication links by the
peripherals connected to any computer system. These communication links are used to resolve
the differences between CPU and peripheral. There exists special hardware components
between CPU and peripherals to supervise and synchronize all the input and output transfers
that are called interface units.

Functions of Input-Output Interface

The Input-Output Interface serves several critical functions that enable

proper communication between the computer system and peripheral
devices:
1. Speed Synchronization
The interface ensures that the CPU's operating speed is synchronized
with the input-output devices. This prevents data loss due to speed
mismatches.

2. Processor Communication

The interface accepts and decodes commands from the processor,

reports the current status, and recognizes its unique address.

3. Signal Control

It generates and manages control and timing signals needed for data
transfer, ensuring smooth communication between the CPU and
peripherals.

4. Data Buffering

The interface enables buffering, which temporarily stores data as it

moves between devices and the CPU, helping manage the difference in
processing speeds.

5. Error Detection

The interface can detect errors in data transmission, ensuring that errors
are flagged and corrected before they affect system performance.

6. Data Conversion

It converts serial data to parallel data and vice versa, as well as

converting digital data to analog signals and vice versa, and ensures the
format is compatible with the receiving device.
7. Status Reporting

The interface reports the current status of the peripheral device to the
processor.

INPUT-OUTPUT-Modes of Transfer:

The binary information that is received from an external device is usually stored in the
memory unit. The information that is transferred from the CPU to the external device is
originated from the memory unit. CPU merely processes the information but the source
and target is always the memory unit. Data transfer between CPU and the I/O devices
may be done in different modes. Data transfer to and from the peripherals may be
done in any of the three possible ways(TYPES OF INPUT-OUTPUT INTERFACES)

Programmed I/O.
Interrupt- initiated I/O.
Direct memory access( DMA).

Now let’s discuss each mode one by one.

Programmed I/O(PIO): It is due to the result of the I/O instructions that are written in
the computer program. Each data item transfer is initiated by an instruction in the
program. Usually the transfer is from a CPU register and memory. In this case it
requires constant monitoring by the CPU of the peripheral devices.

Example of Programmed I/O: In this case, the I/O device does not have direct access
to the memory unit. A transfer from I/O device to memory requires the execution of
several instructions by the CPU, including an input instruction to transfer the data from
device to the CPU and store instruction to transfer the data from CPU to memory. In
programmed I/O, the CPU stays in the program loop until the I/O unit indicates that it is
ready for data transfer. This is a time consuming process since it needlessly keeps the
CPU busy. This situation can be avoided by using an interrupt facility. This is discussed
below.
Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy
unnecessarily. This situation can very well be avoided by using an interrupt driven
method for data transfer. By using interrupt facility and special commands to inform the
interface to issue an interrupt request signal whenever data is available from any
device. In the meantime the CPU can proceed for any other program execution. The
interface meanwhile keeps monitoring the device. Whenever it is determined that the
device is ready for data transfer it initiates an interrupt request signal to the computer.
Upon detection of an external interrupt signal the CPU stops momentarily the task that
it was already performing, branches to the service program to process the I/O transfer,
and then return to the task it was originally performing.

The I/O transfer rate is limited by the speed with which the processor can test and
service a device.
The processor is tied up in managing an I/O transfer; a number of instructions must be
executed for each I/O transfer.

Terms:

Hardware Interrupts: Interrupts present in the hardware pins.

Software Interrupts: These are the instructions used in the program whenever the
required functionality is needed.

Vectored interrupts: These interrupts are associated with the static vector address.

Non-vectored interrupts: These interrupts are associated with the dynamic vector
address.

Maskable Interrupts: These interrupts can be enabled or disabled explicitly.

Non-maskable interrupts: These are always in the enabled state. we cannot disable
them.

External interrupts: Generated by external devices such as I/O.

Internal interrupts: These devices are generated by the internal components of the
processor such as power failure, error instruction, temperature sensor, etc.

Synchronous interrupts: These interrupts are controlled by the fixed time interval. All
the interval interrupts are called as synchronous interrupts.

Asynchronous interrupts: These are initiated based on the feedback of previous

instructions. All the external interrupts are called as asynchronous interrupts.

Direct Memory Access : The data transfer between a fast storage media such as
magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow
the peripherals directly communicate with each other using the memory buses,
removing the intervention of the CPU. This type of data transfer technique is known as
DMA or direct memory access. During DMA the CPU is idle and it has no control over
the memory buses. The DMA controller takes over the buses to manage the transfer
directly between the I/O devices and the memory unit.

How does DMA work?

Initialization: The procedure begins with the CPU configuring the DMA controller. The CPU provides
the DMA controller with crucial data transfer information such as source and destination memory
addresses, bytes to transfer, and transfer direction.
Peripheral Request: When a peripheral device (such as a network card, disc controller, or sound
card) needs to read or write to memory, it sends a request to the DMA controller.
Permission Granted: The DMA controller takes control of the system bus if the CPU provides
permission (usually via a handshake mechanism or by validating priority settings).
Data Transfer: With control of the system bus, the DMA controller begins data transfer between the
peripheral device and memory. Depending on the operation and setup, it can transport data in blocks
or in a streaming form.
Parallel Operation: It is important to note that the CPU can continue to execute other instructions
and operations while the data transfer process is running. This parallel procedure improves system
efficiency since the CPU is not used by the transfer itself.
Completion Notification: When the data transfer is complete, the DMA controller tells the requesting
peripheral device that the operation is complete. It can also emit an interruption to notify the CPU for
the completion of the transfer or any possible problems.
Bus Release: After completing the data transfer, the DMA controller relinquishes control of the
system bus, enabling the CPU and other devices to use it as needed.
I/O Bus

The Input-Output bus and interface modules play a crucial role in facilitating communication between the CPU
and external devices. The I/O bus connects all the I/O devices to the system, while the interface modules act
as translators between the CPU’s internal bus and the external devices. Let us see each component in detail .

 The I/O bus consists of three primary buses: data bus, address bus, and control bus.
 The data bus carries the actual data being transferred between the processor and peripherals.
 The address bus allows the processor to select a specific peripheral device connected to the
I/O bus.
 The control bus provides control signals for managing data transfer, such as read/write,
start/stop, and error detection.

What is a DMA Controller?

Direct Memory Access (DMA) uses hardware for accessing the memory, that hardware
is called a DMA Controller. It has the work of transferring the data between Input Output
devices and main memory with very less interaction with the processor. The direct
Memory Access Controller is a control unit, which has the work of transferring data.

Working of DMA Controller

The DMA controller registers have three registers as follows.

 Address register – It contains the address to specify the desired location in memory.
 Word count register – It contains the number of words to be transferred.
 Control register – It specifies the transfer mode.

Note: All registers in the DMA appear to the CPU as I/O interface registers. Therefore,
the CPU can both read and write into the DMA registers under program control via the
data bus.
The figure below shows the block diagram of the DMA controller. The unit communicates
with the CPU through the data bus and control lines. Through the use of the address bus
and allowing the DMA and RS register to select inputs, the register within the DMA is
chosen by the CPU. RD and WR are two-way inputs. When BG (bus grant) input is 0, the
CPU can communicate with DMA registers. When BG (bus grant) input is 1, the CPU
has relinquished the buses and DMA can communicate directly with the memory.
 Working Diagram of DMA Controller

Pros and Cons of Direct Memory Access

 Reduced CPU overhead: DMA allows devices to transfer data directly

to and from memory without CPU intervention. This reduces the burden
on the CPU and frees it to perform other tasks, improving overall
system performance and responsiveness.
 Faster data transfer: DMA transfers data between devices and
memory at high speeds, often faster than the CPU could achieve
through programmed I/O. This particularly benefits high-speed
peripherals such as disk drives, network interfaces, and graphics
cards.
 Concurrent processing: DMA enables concurrent processing of tasks
by allowing devices to transfer data independently of the CPU. This
parallelism enhances system efficiency and multitasking capabilities.
  Efficient memory access: DMA controllers optimize memory access
patterns and bus utilization, leading to more efficient use of system
resources and reduced latency in data transfers.
 Supports large data transfers: DMA is well-suited for efficiently
transferring large blocks of data, such as multimedia files or database
records, without imposing significant CPU overhead.

Cons of DMA

 Complexity: Implementing DMA in hardware and software adds

complexity to system design and development. Proper management of
DMA controllers, memory access, and bus arbitration requires careful
attention to detail and may increase system development time and
cost.
 Potential for bus contention: DMA controllers compete for access to
the system bus with other devices and the CPU. Bus contention can
occur if multiple devices request access simultaneously, potentially
leading to delays or performance degradation.
 Risk of data corruption: Improperly managed DMA transfers can
result in data corruption or system instability. DMA operations may
introduce errors into transferred data without proper error handling
mechanisms, leading to data loss or system crashes.
 Security concerns: DMA bypasses certain CPU-based security
features, potentially exposing sensitive data in memory to unauthorized
access or tampering. Malicious DMA attacks, such as DMA-based
memory scraping or injection, pose security risks in certain system
configurations.
 Compatibility issues: DMA functionality and performance may vary
across different hardware platforms and operating systems. Ensuring
compatibility and optimizing DMA performance across diverse
environments can be challenging for system developers and
administrators.

Advantages of I/O interfaces:

Standardization: I/O interfaces provide a standard way of communicating with external

devices. This means that different devices can be connected to a computer using the
same interface, which makes it easier to swap out devices and reduces the need for
specialized hardware.
Modularity: With I/O interfaces, different devices can be added or removed from a
computer without affecting the other components. This makes it easier to upgrade or
replace a faulty device without affecting the rest of the system.
Efficiency: I/O interfaces can transfer data between the computer and the external
devices at high speeds, which allows for faster data transfer and processing times.
Compatibility: I/O interfaces are designed to be compatible with a wide range of
devices, which means that users can choose from a variety of devices that are
compatible with their computer’s I/O interface.

Disadvantages I/O Interfaces:

Cost: I/O interfaces can be expensive, especially if specialized hardware is required to

connect a particular device to a computer system.
Complexity: Some I/O interfaces can be complex to configure and require specialized
knowledge to set up and maintain. This can be a disadvantage for users who are not
familiar with the technical aspects of computer hardware.
Compatibility issues: While I/O interfaces are designed to be compatible with a wide
range of devices, there can still be compatibility issues with certain devices. In some
cases, device drivers may need to be installed to ensure proper functionality.
Security risks: I/O interfaces can be a security risk if they are not properly configured or
secured. Hackers can exploit vulnerabilities in I/O interfaces to gain unauthorized access
to a computer system or steal data.

Interface Circuits

An I/O interface consists of the circuitry required to connect an I/O device to a computer bus. On one side of the
interface, we have bus signals. On the other side, we have a data path with its associated controls to transfer data
between the interface and the I/O device – port.

We have two types:

Serial port and

Parallel port

A parallel port transfers data in the form of a number of bits (8 or 16) simultaneously to or from the device. A serial port
transmits and receives data one bit at a time. Communication with the bus is the same for both formats. The conversion
from the parallel to the serial format, and vice versa, takes place inside the interface circuit. In parallel port, the
connection between the device and the computer uses a multiple-pin connector and a cable with as many wires. This
arrangement is suitable for devices that are physically close to the computer. In serial port, it is much more convenient
and cost-effective where longer cables are needed.

Typically, the functions of an I/O interface are:

• Provides a storage buffer for at least one word of data

• Contains status flags that can be accessed by the processor to determine whether the buffer is full or empty

• Contains address-decoding circuitry to determine when it is being addressed by the processor

• Generates the appropriate timing signals required by the bus control scheme

• Performs any format conversion that may be necessary to transfer data between the bus and the I/O device, such as
parallel-serial conversion in the case of a serial port.

Parallel Port
The hardware components needed for connecting a keyboard to a processor Consider the circuit of input interface
which encompasses (as shown in below figure):

–Status flag, SIN

–R/~W

–Master-ready

–Address decoder

Now, consider the circuit for the status flag (figure 4.30). An edge-triggered D flip-flop is used along with read-data and
master-ready signals
The hardware components needed for connecting a printer to a processor are: the circuit of output interface, and

–Slave-ready

–R/~W

–Master-ready

–Address decoder

–Handshake control

The input and output interfaces can be combined into a single interface. The general purpose parallel interface circuit
that can be configured in a variety of ways. For increased flexibility, the circuit makes it possible for some lines to serve
as inputs and some lines to serve as outputs, under program control.

Serial Port
A serial interface circuit involves – Chip and register select, Status and control, Output shift register, DATAOUT, DATAIN,
Input shift register and Serial input/output
Standard I/O interfaces
Consider a computer system using different interface standards. Let us look in to Processor bus and Peripheral
Component Interconnect (PCI) bus. These two buses are interconnected by a circuit called bridge. It is a bridge between
processor bus and PCI bus.

The three major standard I/O interfaces discussed here are:

–PCI (Peripheral Component Interconnect)

–SCSI (Small Computer System Interface)

–USB (Universal Serial Bus)

Peripheral Component Interconnect (PCI) Bus

Data tansfer:-
The PCI bus is designed primarily to support a brust of data than just one word.
A read or write operation involving a single word treated as a burst of length one.
A bus supports 3 independent address spaces:
->Memory
->I/O
->Configuration
Device Configuration:-
When an I/O device is connected to a computer, several actions are needed to configure both the
devices and software communities with it . A number of switches that have to be set by user to select
certain options. Once the device is connected the software needs to know the address of the device .
It should know other characteristics as
speed
transmission link
whether parity bits are used and so on.

UNIVERSAL SERIAL BUS (USB):-

It was developed by several communication companies like compaq , hewlett packard, Intel Microsoft etc.
The USB supports 2 speeds of connection:-
-> Low speed (1.5 megabits/ second)
->Full speed (12 megabits/ second)
The most recent version of the bus (USB 2.0) introduced a 3rd speed of operation called high speed (480
megabits/second)
The USB is designed to meet Several key objectives:

->It provides a simple , low cost , and easy to the interconnection system that overcomes
the difficulties due to the limited number of I/O ports available on a computer.
->Accommodates a wide range of data transfer characteristics for I/O devices, including
telephone and internet connection.
->Enhance user convenience through a plug and play mode of operation.

SMALL COMPUTER SYSTEM INTERFACE BUS(SCSI BUS):-

It refers to a standard bus defined by the ANSI.

A controller connected to SCSI bus is one of two types – an initiator or a target.
An initiator has the ability to select a particular target and to send commands specifying the
operations to be performed.
The disk controller operates as a target. It carries out the commands it receives from the initiator. The
initiator establishes a logical connection with the intended target.Once the connection as been
established, it can be suspended and restored as needed to transfer commands and bursts of data.
While a particular connection is suspended , other devices can use the bus to
transfer information.This ability to overlap data transfer request is one of the key features of the SCSI
bus that leads to its high performance.
Data transfer on SCSI bus is controlled by the target controller. To send a command to a target, an
initiator controller requests control of the bus and after, and , after winning arbitration , selects the
controller it wants to communicate with and hands control of the bus over to it. Then the controller
starts a data transfer operation to receive a command from the initiator.